INTEGRATED CIRCUITS PCK2023 CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator Product data File under Integrated Circuits — ICL03 2001 Sep 07 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator FEATURES PCK2023 PIN CONFIGURATION • 3.3 V operation • Three differential CPU clock pairs • Ten PCI clocks at 3.3 V • Six 66 MHz clocks at 3.3 V • Two 48 MHz clocks at 3.3 V • One 14.318 MHz reference clock • 66,100, 133 or 200 MHz operation • Power management control pins • CPU clock skew less than 200 ps cycle-to-cycle • CPU clock skew less than 150 ps pin-to-pin • 1.5 ns to 3.5 ns delay on PCI pins • Spread Spectrum capability VDD 1 DESCRIPTION The PCK2023 is a clock synthesizer/driver for a Pentium IV and other similar processors. The PCK2023 has three differential pair CPU current source outputs. There are ten PCI clock outputs running at 33 MHz and two 48 MHz clocks. There are six 3V66 outputs. Finally, there is one 3.3 V reference clock at 14.318 MHz. All clock outputs meet Intel’s drive strength, rise/fall times, jitter, accuracy, and skew requirements. The part possesses a dedicated power-down input pin for power management control. This input is synchronized on-chip and ensures glitch-free output transitions. 56 REF_0 XTAL_In 2 55 S0 XTAL_Out 3 54 CPU3 VSS 4 53 CPU3 PCIF0 5 52 CPU0 PCIF1 6 51 CPU0 PCIF2 7 50 VDD VDD 8 49 CPU1 VSS 9 48 CPU1 PCI0 10 47 VSS PCI1 11 46 VDD PCI2 12 45 CPU2 PCI3 13 44 CPU2 VDD 14 43 Mult0 VSS 15 42 IREF PCI4 16 41 VSS Iref PCI5 17 40 S2 PCI6 18 39 USB 48 MHz VDD 19 38 DOT 48 MHz VSS 20 37 VDD 48 MHz 66Buff0/3V66_2 21 36 VSS 48 MHz 66Buff1/3V66_3 22 35 3V66_1/VCH 66Buff2/3V66_4 23 34 PCI_Stop 66In/3V66_5 24 33 3V66_0 PWRDWN 25 32 VDD VDDA 26 31 VSS VSSA 27 Vtt_Pwrgd 28 30 SCLK 29 SDATA SW00695 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 56-Pin Plastic SSOP 0 to +70 °C PCK2023DL SOT371-1 56-Pin Plastic TSSOP 0 to +70 °C PCK2023DGG SOT364-1 Intel and Pentium are registered trademarks of Intel Corporation. 2001 Sep 07 2 853-2278 27052 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 56 ref 2 XTAL_In 3.3 V 14.318 MHz clock output. 3 XTAL_Out 44, 45, 48, 49, 51, 52 CPU & CPU [2:0] 33 3V66_0 35 3V66_1/VCH 3.3 V selectable through I2C to be 66 MHz or 48 MHz 24 66In/3V66_5 66 MHz input to buffered 66Buff and PCI or 66 MHz clock from internal VCO. 21, 22, 23 66Buff [2:0] / 3V66 [4:2] 66 MHz buffered outputs from 66 input or 66 MHz clocks from internal VCO. 5, 6, 7 PCIF [2:0] 33 MHz clocks divided down from 66 input or divided down from 3V66. 10, 11, 12, 13, 16, 17, 18 PCI [6:0] PCI clock outputs divided down from 66 input or divided down from 3V66. 39 USB Fixed 48 MHz clock output. 38 DOT Fixed 48 MHz clock output. 14.318 MHz crystal input. 14.318 MHz crystal output. Differential CPU clock outputs. 3.3 V 66 MHz clock output. 40 S2 54, 55 S1, S0 42 Iref 43 Mult0 25 PWRDWN 3.3 V LVTTL input for PowerDown active low. 34 PCI_Stop 3.3 V LVTTL input for PCI_Stop active low. 53 CPU_Stop 3.3 V LVTTL input for CPU_Stop active low. 28 Vtt_Pwrgd 3.3 V LVTTL input is a level sensitive strobe used to determine when S [2:0] and Mult0 inputs are valid and ok to be sampled (active low). 29 SDATA 30 SCLOCK 1, 8, 14, 19, 32, 37, 46, 50 VDD 26 VDDA 4, 9, 15, 20, 31, 36, 41, 47 VSS 27 VSSA 2001 Sep 07 Special 3.3 V 3 level input for mode selection. 3.3 V LVTTL inputs for CPU frequency selection. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3 V LVTTL input for selecting the current multiplier for the CPU outputs. I2C compatible SDATA. I2C compatible SCLOCK. 3.3 V power supply for outputs. 3.3 V power supply for PLL. Ground for outputs. Ground for PLL. 3 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 BLOCK DIAGRAM XIN X XOUT X 14.318 MHZ OSC USBPLL PWRDWN X REF [0](14.318 MHz) PWRDWN X DOT/USB 48 MHz PWRDWN X 3V66_1/VCH(48/66 MHz) PWRDWN X SYSPLL IREF X CPU [0–2](100/133 MHz) IBIAS PWRDWN X CPU [0–2](100/133 MHz) PWRDWN X 3V66 [2–4] (66 MHz) X 66ln/3V66_5(66 MHz) PWRDWN X 3V66_0 (66 MHz) PWRDWN X PCI [0–6](33 MHz) X PCIF [0–2] (33 MHz) CPU STOP X PWRDWN PCI STOP X PWRDWN X S2 X S1 X LOGIC S0 X MULT0 X Vtt Pwrgd X SDA X SCL X SW00861 2001 Sep 07 4 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 FREQUENCY SELECT/FUNCTION TABLE CPU 3V66 66BUFF/ 3V66 66In/ 3V66_5 PCIF/PCI REF 0 USB/DOT 3V66_1/ VCH 0 66 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 1 100 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 1 0 200 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 1 1 133 MHz 66 MHz 66 In 66 input 66 In/2 14.318 MHz 48 MHz 66/48 MHz 0 0 0 66 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz 0 0 1 100 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz 0 1 0 200 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz 66/48 MHz 66/48 MHz S2 S1 S0 1 0 1 0 1 1 0 1 1 133 MHz 66 MHz 66 MHz 66 MHz 33 MHz 14.318 MHz 48 MHz Mid 0 0 Low Hi Z Hi Z Hi Z Hi Z Hi Z Hi Z Hi-Z Mid 0 1 Tclk/2 Tclk/4 Tclk/4 Tclk/4 Tclk/8 Tclk Tclk/2 Tclk/4 NOTE: 1. Mid is defined as a voltage level between 1.0 V and 1.8 V for 3 level input functionality. Low is below 0.8 V. High is above 2.0 V. 2. 3V66_1/VCH output frequency is set by the I2C. 3. Frequency of the 48 MHz outputs must be +167 ppm to match USB default. 4. Rref output min = 14.316 MHz, nominal = 14.31818, max = 14.32 MHz. 5. Tclk is a test clock over-driven on the XTAL_In input during test mode. POWER DOWN MODE PWRDWN CPU CPU 3V66 66BUFF/ 3V66 66In/ 3V66_5 PCIF/PCI REF 0 USB/DOT 3V66_1/ VCH 1 Normal Normal Normal Normal Normal Normal Normal Normal Normal 0 Iref*2 Float Low Low Low Low Low Low Low HOST SWING SELECT FUNCTIONS – CK408 MULT 0 BOARD IMPEDANCE 0 1 Iref IOH VOH @ 50 W 50 Ω Rref = 221.1% Iref = 5.00 mA IOH = 4*Iref 1.0 V 50 Ω Rref = 475.1% I ref = 2.32 mA IOH = 6*Iref 0.7 V CONDITIONS CONFIGURATION LOAD MIN. MAX. IOUT VDD = 3.3 V All combinations, see Table above Nominal test load for given configuration –7% of IOH See Table above +7% of IOH See Table above IOUT VDD = 3.3 V ±5% All combinations, see Table above Nominal test load for given configuration –12% of IOH See Table above +12% of IOH See Table above 2001 Sep 07 5 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL PARAMETER VDD3 DC 3.3 V supply IIK DC input diode current LIMITS CONDITION MIN MAX UNIT –0.5 +4.6 V VI < 0 — –50 mA VI DC input voltage Note 2 — — V IOK DC output diode current VO > VDD or VO < 0 — ±50 mA VO DC output voltage Note 2 –0.5 VDD + 0.5 V IO DC output source or sink current VO = 0 to VDD — ±50 mA Tstg Storage temperature range –65 +150 °C Ptot Power dissipation per package plastic medium-shrink (SSOP) — 850 mW For temperature range: –40 to +125°C above +55°C derate linearly with 11.3 mW/K NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS LIMITS MIN MAX UNIT VDD3 DC 3.3 V supply voltage 3.135 3.465 V AVDD DC 3.3 V analog supply voltage 3.135 3.465 V 2.0 VDD + 0.3 V VIH 3.3 V input high voltage VIL 3.3 V input high voltage VOL3 3.3 V input low voltage VOH3 VSS – 0.3 0.8 V IOL = 1.0 mA — 0.4 V 3.3 V input high voltage IOH = 1.0 mA 2.4 — V IIL Input leakage current 0 < VIN < VDD –5 +5 µA fref reference frequency, oscillator normal value 14.31818 14.31818 MHz NOTES 1 CIN Input pin capacitance — 5 pF 2 CXTAL Xtal pin capacitance 13.5 22.5 pF 3 COUT Output pin capacitance — 6 pF 2 LPIN Pin inductance — 7 nH 2 Tamb Operating ambient temperature range in free air 0 +70 °C NOTES: 1. Input leakage current does not include inputs with pull up or pull down resistors. 2. This is a recommendation, not an absolute requirement. 3. As seen by the crystal. Device is intended to be used with a 17–20 pF AT crystal. 2001 Sep 07 6 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 POWER MANAGEMENT MAXIMUM 3.3 V SUPPLY CONSUMPTION MAXIMUM DISCRETE CAP LOADS, VDDL= 3.465 V ALL STATIC INPUTS = VDD3 OR VSS CONDITION Power-down mode (PWRDWN = 0) 25 mA @ Iref = 2.32 mA 46 mA @ Iref = 5.0 mA Full active 280 mA CPU STOP FUNCTIONALITY CPU_STOP CPU CPU 3V66 66BUFF PCIF/PCI USB/DOT 1 Normal Normal 66 MHz 66 input 66 input/2 48 MHz 0 Iref*2 Float 66 MHz 66 input 66 input/2 48 MHz DC CHARACTERISTICS SYMBOL LIMITS TEST CONDITIONS PARAMETER VDD (V) Tamb = 0 to +70 °C OTHER 3.135 VOUT = 1.0 V 3.465 VOUT = 3.135 V 3.135 VOUT = 1.95 V 3.465 VOUT = 0.4 V 3.135 VOUT = 1.0 V 3.465 VOUT = 3.135 V 3.135 VOUT = 1.95 V 3.465 VOUT = 0.4 V UNIT MIN TYP Type y 3A 12–60 Ω –29 — MAX — — — –23 Type y 3A 12–60 Ω 29 — — — — 27 Type y 3B 12–60 Ω –29 — — — — –23 Type y 3B 12–60 Ω 29 — — — — 27 Type y 5 12–55 Ω –33 — — — — –33 Type y 5 12–55 Ω 30 — — — — 38 IOH O 48 MHz USB, USB VCH IOL O 48 MHz USB, USB VCH IOH O 48 MHz DOT IOL O 48 MHz DOT IOH O REF,, PCI,, PCIF,, 3V66, 66BUFF 3.135 VOUT = 1.0 V 3.465 VOUT = 3.135 V IOL O REF,, PCI,, PCIF,, 3V66, 66BUFF 3.135 VOUT = 1.95 V 3.465 VOUT = 0.4 V VOL CPU/CPU VSS = 0.0 RS = 33.2 Ω RP= 49.9 Ω Type X1 0.0 — 0.05 V 3.365 0 < VIN < VDD3 — –5 — 5 µA 3.465 VOUT = VDD or GND IO = 0 — — 10 µA ±II ±IOZ Input leakage current 3-State output OFF-State current NOTE: 1. All clock outputs loaded with maximum lump capacitance test load specified in AC characteristics section. 2001 Sep 07 7 mA mA mA mA mA mA Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 AC CHARACTERISTICS VDD3 = 3.3 V –5%; fcrystal = 14.31818 MHz 3V66 66 MHz TIMING REQUIREMENTS SYMBOL LIMITS Tamb = 0 to +70 °C PARAMETER MIN MAX UNIT NOTES TPERIOD period 15.0 15.3 ns 8, 13 tHIGH HIGH time 4.95 N/A ns 9 tLOW LOW time 4.55 N/A ns 10 tRISE rise time 0.5 2.0 ns 12 tFALL fall time 0.5 2.0 ns 12 tJITTER cycle-to-cycle jitter — 250 ps Edge rate rising edge rate 1.0 4.0 V/ns 12 Edge rate falling edge rate 1.0 4.0 V/ns 12 tSKEW pin-to-pin skew 3V66 [1:0] 0.0 250 ps tSKEW pin-to-pin skew 3V66 [5:2] 0.0 250 ps tSKEW pin-to-pin skew 3V66 [5:0] 0.0 450 ps 66 MHz BUFFERED TIMING REQUIREMENTS SYMBOL LIMITS Tamb = 0 to +70 °C PARAMETER MIN MAX UNITS NOTES tRISE rise time 0.5 2.0 ns 12 tFALL fall time 0.5 2.0 ns 12 tPD propagation delay from 66In to 66BUFF [2:0] 2.5 4.5 ns Edge rate rising edge rate 1.0 4.0 V/ns 12 Edge rate falling edge rate 1.0 4.0 V/ns 12 tSKEW 66 MHz buffered pin-to-pin skew 0.0 175 ps PCIF/PCI AC TIMING REQUIREMENTS SYMBOL LIMITS Tamb = 0 to +70 °C PARAMETER MIN MAX UNITS NOTES 8, 13 TPERIOD period 30.0 N/A ns tHIGH HIGH time 12.0 N/A ns 9 tLOW LOW time 12.0 N/A ns 10 tRISE rise time 0.5 2.0 ns 12 tFALL fall time 0.5 2.0 ns 12 tJITTER cycle-to-cycle jitter — — ps Edge rate rising edge rate 1.0 4.0 V/ns 12 Edge rate falling edge rate 1.0 4.0 V/ns 12 tSKEW pin-to-pin skew 0.0 500 ps tPCI 3V66 [5:0] leads 33 MHz PCI 1.5 3.5 ns 2001 Sep 07 8 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 USB 48 MHz AC TIMING REQUIREMENTS SYMBOL LIMITS Tamb = 0 to +70 °C PARAMETER MIN UNITS NOTES MAX TPERIOD (average) period nominal = 20.829 ns tHIGH HIGH time 8.094 10.036 tLOW LOW time 7.694 9.836 ns f frequency 48.000 48.008 MHz 8 tRISE rise time 1.0 2.0 ns 12 tFALL fall time 1.0 2.0 ns 12 ns tJITTER cycle-to-cycle jitter 0 350 ps Edge rate rising edge rate 1.0 2.0 V/ns Edge rate falling edge rate 1.0 2.0 V/ns DOT 48 MHz AC TIMING REQUIREMENTS SYMBOL LIMITS Tamb = 0 to +70 °C PARAMETER MIN UNITS NOTES MAX TPERIOD (average) period tHIGH HIGH time tLOW LOW time 7.694 9.836 ns f frequency 48.000 48.008 MHz 8 tRISE rise time 0.5 1.0 ns 12 tFALL fall time 0.5 1.0 ns 12 tJITTER cycle-to-cycle jitter — 350 ps Edge rate rising edge rate 2.0 4.0 V/ns Edge rate falling edge rate 2.0 4.0 V/ns tSKEW USB to DOT — 1000 ps 2001 Sep 07 nominal = 20.829 8.094 9 ns 10.036 ns Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 CPU 0.7 V AC TIMING REQUIREMENTS CPU 200 MHz CPU 133 MHz CPU 100 MHz MIN MAX MIN MAX MIN MAX MIN MAX average period 5.0 5.1 7.5 7.65 10.0 10.2 15.0 tABSMIN absolute minimum host clock period 4.8 — 7.3 — 9.8 — tRISE rise time 175 600 175 600 175 tFALL fall time 175 600 175 600 175 ∆tRISE rise time variation — 150 — 150 ∆tFALL fall time variation — 150 — VCROSS absolute crossing point voltages 280 430 ∆VCROSS total variation of VCROSS for rising edge of host — Total ∆VCROSS total variation of VCROSS over all edges tCCJITTER cycle-to-cycle jitter SYMBOL PARAMETER TPERIOD Duty Cycle CPU 66 MHz UNITS NOTES 15.3 ns 1, 7 14.8 — ns 1, 7 600 175 600 ps 2, 7, 14 600 175 600 ps 2, 7, 14 — 150 — 150 ps 2, 7 150 — 150 — 150 ps 2, 7 280 430 280 430 280 430 mV 7 90 — 90 — 90 — 90 mV 3, 7 — 110 — 110 — 110 — 110 mV 4, 7 — 150 — 150 — 150 — 150 ps 7, 15 45 55 45 55 45 55 45 55 % 7 Overshoot maximum voltage allowed at output — 850 — 850 — 850 — 850 mV 7 Undershoot minimum voltage allowed at output — –150 — –150 — –150 — –150 mV 7 tSKEW pin-to-pin — 150 — 150 — 150 — 150 ps 2001 Sep 07 10 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 CPU 1.0 V AC TIMING REQUIREMENTS CPU 200 MHz CPU 133 MHz CPU 100 MHz MIN MAX MIN MAX MIN MAX MIN MAX average period 5.0 5.1 7.5 7.65 10.0 10.2 15.0 tABSMIN absolute minimum host clock period 4.85 — 7.35 — 9.85 — Diff-tRISE rise time 175 467 175 467 300 Diff-tFALL fall time 175 467 175 467 175 SE ∆SKEW Absolute single-ended rise/fall waveform symmetry — 325 — 325 VCROSS absolute crossing point voltages 0.51 0.76 0.51 tCCJITTER cycle-to-cycle jitter — 150 Duty Cycle — 45 SE-VOH maximum voltage allowed at output SYMBOL PARAMETER TPERIOD CPU 66 MHz UNITS NOTES 15.3 ns 1, 15 14.85 — ns 1, 15 467 300 467 ps 15, 16 467 175 467 ps 15, 16 — 325 — 325 ps 17, 18 76 0.51 76 — — V 18 — 150 — 150 — 150 ps 15, 19 55 45 55 45 55 45 55 % 15 .92 1.45 .92 1.45 .92 1.45 .92 1.45 V 18 SE-VOL minimum voltage allowed at output –200 350 –200 350 –200 350 –200 350 mV 18 DiffVRING_RISE rising edge ringback 0.35 — 0.35 — 0.35 — 0.35 — V 15 DiffVRING_FALL falling edge ringback — –0.35 — –0.35 — –0.35 — –0.35 V 15 2001 Sep 07 11 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 ALL OUTPUTS SYMBOL LIMITS Tamb = 0 to +70 °C PARAMETER UNITS MIN MAX output enable delay (all outputs) 1.0 10.0 tPZL/tPZH output disable delay (all outputs) 1.0 10.0 ns tSTABLE all clock stabilization from power-up — 3 ms tPZL/tPZH NOTES ns 11 NOTES: 1. Measured at crossing points or where subtraction of CLK-CLK crosses 0 V. 2. Measured from VOL = 0.175 V to VOH = 0.525 V. 3. These crossing points refer to only crossing points containing a rising edge of a CPU output (as opposed to a CPU output). 4. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. 5. Measured from VOL = 0.2 V to VOH = 0.8 V. 6. Determined as a fraction of 2* (tRISE–tFALL)/(tRISE+tFALL). 7. Test load is RS = 33.2 Ω, RP = 49.9 Ω. 8. Period, jitter, offset and skew measured at rising edge @ 1.5 V for 3.3 V clocks. 9. THIGH is measured at 2.4 V for non-CPU outputs. 10. TLOW is measured at 0.4 V for all outputs. 11. The time specified is measured from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable and operating within specification. 12. The 3.3 V clock tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification. 13. The average period over any 1 µs period of time must be greater than the minimum specified period. 14. Designed for 150–420 ps (1 V/ns minimum rise time across 0.42 V). 15. Measurement taken from differential waveform. 16. Measurement taken from differential waveform from –0.35 to +0.35 V. 17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time matching is defined as “the instantaneous difference between maximum CLK rise (fall) and minimum CLK fall (rise) time, or minimum CLK rise (fall) and maximum CLK fall (rise) time”. This parameter is designed for waveform symmetry. 18. Measured in absolute voltage, single ended. 19. Cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-CPU outputs. 2001 Sep 07 12 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator AC WAVEFORMS PCK2023 VI VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH – 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. SEL1, SEL0 VM GND tPLZ tPZL VDD VOH OUTPUT LOW-to-OFF OFF-to-LOW 50% HOST CLK VSS VM VX VOL tPHZ VOH VOH 50% HOST CLK tPZH VY OUTPUT HIGH-to-OFF OFF-to-HIGH VSS tSKEW VSS tPERIOD SW00850 VM Outputs enabled Outputs disabled Outputs enabled SW00571 Figure 1. Host clock Figure 3. State enable and disable times COMPONENT MEASUREMENT POINTS VOH = 2.4 V VOL = 0.4 V VDDL VIH = 2.0 V 1.5 V VIL = 0.7 V VSS SYSTEM MEASUREMENT POINTS SW00851 Figure 2. 3.3 V clock waveforms 2001 Sep 07 13 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 S1 VDD 2 VDD Open VSS 500Ω VI VO PULSE GENERATOR D.U.T. CL RT TEST 500Ω S1 tPLH/tPHL Open tPLZ/tPZL 2 VDD tPHZ/tPZH VSS VDD = VDDL or VDD3, DEPENDS ON THE OUTPUT SW00852 Figure 4. Load circuitry for switching times PWRDWN HOST CLK (INTERNAL) PCICLK (INTERNAL) PWRDWN HOST CLK (EXTERNAL) PCICLK (EXTERNAL) OSC & VCO USB (48 MHz) ÁÁ ÁÁ ÁÁ ÁÁ Figure 5. Power management 2001 Sep 07 14 SW00853 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 POWER-UP SEQUENCE Figure 6 shows the power-up sequence for the PCK2023. Once power is applied to the device, an internal sense circuit generates a signal when the supply is above approximately 2 volts. This signal generates a series of timed signals that control the sequential event inside the device. First, the multifunction pins are latched into the device. These latched signals are then used to define the mode of operation of the device. A short time later, the PLL is enabled and begins running. After XX ms, the clock outputs are enabled and begin running INTERNAL 3.3 V SUPPLY INTERNAL POWER GOOD SIGNAL LATCH OPERATING MODE SET/PLL START OUTPUTS ENABLED SW00854 Figure 6. Power-up sequence VDD CL RP = 500 Ω RS HOST CRYSTAL 14.318 MHz DUT RS = 33.2 Ω HOST RS RP = 50 Ω SW00855 Figure 7. Host clock measurements 2001 Sep 07 15 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 TPKP DUTY CYCLE TPKH 3.3 V CLOCKING INTERFACE 2.4 V 1.5 V 0.4 V TPKL TRISE TFALL SW00856 Figure 8. 3.3 V clock waveforms 2001 Sep 07 16 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 I2C SPECIFICATION 1 2 3 4 5 6 7 8 9 DUMMY BYTE 1 SLAVE ADDRESS S 1 1 0 1 0 0 1 START CONDITION 0 R/W BYTE 1 AS 0 0 0 0 0 0 SLAVE ACKNOWLEDGE 0 0 0 0 0 0 BYTE 3 AS SLAVE ACKNOWLEDGE AS AS SLAVE ACKNOWLEDGE BYTE 2 AS BYTE 5 DUMMY BYTE 2 SLAVE ACKNOWLEDGE BYTE 6 AS 0 0 0 0 AS SLAVE ACKNOWLEDGE AS SLAVE ACKNOWLEDGE BYTE 0 AS SLAVE ACKNOWLEDGE BYTE 4 AS SLAVE ACKNOWLEDGE P STOP CONDITION SLAVE ACKNOWLEDGE SLAVE ACKNOWLEDGE SW00848 Figure 9. I2C write 1 2 3 4 5 6 7 8 9 BYTE COUNT BYTE (ALWAYS 8) SLAVE ADDRESS S 1 1 0 1 0 START CONDITION BYTE 2 0 1 1 R/W AS 0 0 0 0 SLAVE ACKNOWLEDGE BYTE 3 AM MASTER ACKNOWLEDGE BYTE 6 0 AM 1 1 0 AM BYTE 0 MASTER ACKNOWLEDGE BYTE 4 AM MASTER ACKNOWLEDGE AM MASTER ACKNOWLEDGE AM MASTER ACKNOWLEDGE BYTE 1 AM MASTER ACKNOWLEDGE BYTE 5 AM MASTER ACKNOWLEDGE P STOP CONDITION MASTER ACKNOWLEDGE SW00849 Figure 10. I2C read 2001 Sep 07 17 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 BYTE 0 BIT DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN AFFECTED SOURCE PIN 0 S0 reflects the value of the Sel_0 pin sampled on power-up R externally selected N/A N/A 54 1 S1 reflects the value of the Sel_1 pin sampled on power-up R externally selected N/A N/A 55 2 S2 reflects the value of the Sel_2 pin sampled on power-up R externally selected N/A N/A 40 3 PCI_stop. This bit is ANDed with the PCI_STOP pin for I2C readback and control of PCI outputs RW externally selected All PCI clock outputs except PCI[2:0] pins 10, 11, 12, 13, 16, 17, 18 34 4 CPU_stop reflects the current value of the external CPU_Stop pin R externally selected All CPU clock pairs 44, 45, 48, 49, 51, 52 53 5 VCH select 66 MHz/48MHz enabled RW 0 = 66MHz enabled 3V66_1/VCH 35 N/A 6 not used — 0 — — — 7 spread spectrum enabled RW 0 = spread off CPU[2:0], 3V66[1:0] 5, 6, 7, 10, 11, 12, 13, 16, 17, 18, 33, 35 N/A BIT DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN AFFECTED SOURCE PIN 0 CPU0 output enable 1 = enabled 0 = disabled RW 1 = enabled CPU0 CPU0 51, 52 N/A 1 CPU1 output enable 1 = enabled 0 = disabled RW 1 = enabled CPU1 CPU1 48, 49 55 2 CPU2 output enable 1 = enabled 0 = disabled RW 1 = enabled CPU2 CPU2 44, 45 40 3 allow control of CPU0 with assertion of CPU_Stop 1 = enabled 0 = disabled RW 0 = not free running, is affected by CPU_Stop CPU0 CPU0 51, 52 34 4 allow control of CPU1 with assertion of CPU_Stop 1 = enabled 0 = disabled RW 0 = not free running, is affected by CPU_Stop CPU1 CPU1 48, 49 53 5 allow control of CPU2 with assertion of CPU stop 1 = enabled 0 = disabled RW 0 = not free running, is affected by CPU_Stop CPU2 CPU2 44, 45 N/A 6 not used — 0 — — — 7 CPU Mult0 value sampled at startup R externally selected N/A N/A 43 BYTE 1 2001 Sep 07 18 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 BYTE 2 BIT DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN AFFECTED SOURCE PIN 0 PCI0 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI0 10 N/A 1 PCI1 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI1 11 N/A 2 PCI2 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI2 12 N/A 3 PCI3 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI3 13 N/A 4 PCI4 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI4 16 N/A 5 PCI5 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI5 17 N/A 6 PCI6 output enabled 1 = enabled 0 = disabled RW 1 = enabled PCI6 18 N/A 7 not used — 0 N/A N/A N/A BIT DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN AFFECTED SOURCE PIN 0 PCIF0 output enabled RW 1 = enabled PCIF0 5 N/A 1 PCIF1 output enabled RW 1 = enabled PCIF1 6 N/A 2 PCIF2 output enabled RW 1 = enabled PCIF2 7 N/A 3 allow control of PCIF0 with assertion of PCI_Stop 0 = free running 1 = stopped with PCI_Stop RW 0 = free running not affected by PCI_Stop PCIF0 5 N/A 4 allow control of PCIF1 with assertion of PCI_Stop 0 = free running 1 = stopped with PCI_Stop RW 0 = free running not affected by PCI_Stop PCIF1 6 N/A 5 allow control of PCIF2 with assertion of PCI_Stop 0 = free running 1 = stopped with PCI_Stop RW 0 = free running not affected by PCI_Stop PCIF2 7 N/A 6 USB 48MHz output enabled RW 1 = enabled USB 48MHz 39 N/A 7 DOT 48 MHz output enabled RW 1 = enabled DOT 48MHz 38 N/A BYTE 3 2001 Sep 07 19 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 BYTE 4 BIT DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN NUMBER 0 66Buff0/3V66_2 output enabled 1 = enabled 0 = disabled RW 1 = enabled 66Buff0/3V66_2 21 1 66Buff1/3V66_3 output enabled 1 = enabled 0 = disabled RW 1 = enabled 66Buff1/3V66_3 22 2 66Buff2/3V66_4 output enabled 1 = enabled 0 = disabled RW 1 = enabled 66Buff2/3V66_4 23 3 3V66_5 output enabled 1 = enabled 0 = disabled RW 1 = enabled 3V66_5 24 4 3V66_1/VCH output enabled 1 = enabled 0 = disabled RW 1 = enabled 3V66_1/VCH 35 5 3V66_0 output enabled 1 = enabled 0 = disabled RW 1 = enabled 3V66_0 33 6 not used — 0 — — 7 not used — 0 — — DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN NUMBER RW 0 USB 39 RW 0 USB 39 RW 0 DOT 38 RW 0 DOT 38 BYTE 5 BIT 0 USB edge rate control 1 2 DOT edge rate control 3 4 not used — 0 — — 5 not used — 0 — — 6 not used — 0 — — 7 not used — 0 — — BIT DESCRIPTION/FUNCTION TYPE POWER UP CONDITION OUTPUT(S) AFFECTED PIN NUMBER 0 vendor ID bit 0 R 1 N/A N/A 1 vendor ID bit 1 R 1 N/A N/A 2 vendor ID bit 2 R 1 N/A N/A 3 vendor ID bit 3 R 0 N/A N/A 4 revision code bit 0 R 0 N/A N/A 5 revision code bit 1 R 0 N/A N/A 6 revision code bit 2 R 0 N/A N/A 7 revision code bit 3 R 0 N/A N/A BYTE 6 2001 Sep 07 20 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 The components associated with the clocks should be placed on the same layer as the PCK2023 IC. This will allow the layout to avoid the use of vias for interconnect, thereby reducing node capacitance and trace inductance. All components should be placed as close to the IC as possible. APPLICATION NOTES Optimum performance of the PCK2023 can only be achieved through correct implementation in the system board. This application note addresses many of the issues associated with integrating the PCK2023 on a system board. Descriptions for circuit board layout and decoupling are provided in this application note. Circuit board layout It is possible to generate a circuit board with the proper characteristics using four-layer configuration. Figure 11 shows the layer stack-up. It is critical to keep the clock signals on a plane next to a ground plane to ensure they are ground referenced otherwise the clock signals may experience significant distortion and added jitter. Static signals (such as SPREAD, PWRDWN, etc.) can be placed on a layer next to the power plane. CLOCK SIGNALS GROUND POWER STATIC SIGNALS SW00857 Figure 11. Optimum board layout 2001 Sep 07 21 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator capacitor manufacture’s datasheet to determine the optimum material type to use. Component decoupling Decoupling is another important consideration to ensure optimum operation of the PCK2023. A first pass decoupling capacitor value may be determined by applying the following equation: C bypass + Additional filtering on the Analog supplies (AVDD) may be used to reduce the noise coupled from the circuit board global VDD to the internal VDD of the PCK2023. One way to do this is to use a PI filter. The specific values should be selected to allow proper decoupling on the pin side while rejecting the digital switching noise. A spectrum analyzer can provide considerable insight to ensure optimum values are selected. Measure the frequency content of the supply on either side of the inductor to verify the values selected reduce the noise on the component side of the filter. To provide the maximum isolation, each AVDD line should have a separate filter since the internal circuitry using these lines have very different switching requirements. In general, pin 25 is strictly a static current draw and should not have any switching noise. Great care has been taken to reduce the sensitivity to supply noise, but there is a finite limit to the capability to do this, therefore added filtering on the board should enhance performance. Pin 46 is used as a supply to the internal PLLs. This node will contain some high frequency switching noise since the internal PLLs operate up to 200 MHz. Again, additional filtering will improve the performance of the part. If a single filter is used for both supplies, noise from the PLL supply (pin 46) can couple int the Iref supply (pin 25) and increase the jitter of the HOST outputs. 1 where 2pF pswX max X max + DV DI F psw + PCK2023 X max 2pL psw ∆V is the maximum supply noise permitted (20 mV, for example) ∆I is the maximum current draw for the clock Lpsw is the power supply lead inductance Fpsw is the frequency below which the power supply wiring is adequate The maximum current may be determined by considering the switching of the clock outputs and the capacitive load on these outputs. The following equation may be used to determine the current per output. Once the current for each clock output is determined, they can be summed to determine the total switching current. i + C load dV dt AVDD Most of these values can be determined from the usage in the board design. For example, the IOCLK has a specified edge rate of 1.25 ns typical when slewing between 0.7 and 2.4 volts and the maximum Cload is 30 pF. The HOST outputs are a special case since, although the output either drives current or is off, only one drives at a time, so the current is really steered rather than switched. The act of steering the current reduces switching noise on these supplies, therefore the HOST supplies require less decoupling. As a starting point, assume the supply current for each HOST output is equal to 1/2 the programmed output current. SW00858 Figure 12. PI filter for all analog VDD lines Decoupling capacitors should be located as close to the power pins on the IC as possible. The use of too much decoupling should be avoided since it could cause oscillations on the part because of the LC circuit (the IC leads act as inductors). Also, it is possible to cause oscillations from resonance between the board inductance and board capacitance. Two capacitors may be placed in parallel to effectively extend the capacitance range of the decoupling since the larger capacitor will have a self-resonance at a lower frequency than the smaller capacitor. When using this method, the split between values should be 100 (i.e., 0.1 µF and 0.001 µF). Iref decoupling Filtering on the Iref supply has already been discussed, but additional filtering can be added on the Iref pin (pin 26) to perform additional filtering of the reference current. This reference current is critical to the performance of the HOST outputs since variation in this current is directly proportional to jitter on the HOST outputs. On-die decoupling has been included to reduce noise on this node, but additional decoupling could also be used to further reduce any noise. Care must be taken with this approach to ensure the capacitor and reference resistor share the same ground. Placing both components side by side is an optimum configuration. This external capacitor should not exceed TBD pF to ensure the current source inside the PCK2023 can supply enough charge for this node to reach reference value (1.1 volt). Another consideration when selecting the decoupling capacitors is the dielectric material of the capacitor. This will depend on the frequency range of concern. For lower frequencies, Z5U material may be used since this type of capacitor has a self-resonance in the 1 MHz to 20 MHz range. Capacitors of NPO have a self-resonance much higher and are more for high frequency decoupling. Consult a 2001 Sep 07 VDD3.3 22 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator Functional connection PCK2023 V max + (R s ) R P)N mult 1.1 R ref Figure 13 shows a partial diagram of the PCK2023 in an application. The host outputs are differential current drivers, therefore the output current is converted to a voltage by using some type of load resistor (in this case, RS and RP). The output current is based on two, the value of Rref and the setting on MULTSEL0 and MULTSEL1 pins. The Iref pin is actually a reference voltage which is fixed at 1.1 volts, therefore, Iref is 1.1/Rref. There are limitations on how large the current can be made. This is coupled to the termination resistors used. The maximum voltage which should be observed at the HOST or HOST pins of the PCK2023 is 1.1 volts. This value may be determined by using: where RS and RP are the termination resistor values, Nmult is the current multiplier set by MULTSEL0 and MULTSEL1, and Rref is the current reference resistor. Vmax should not exceed 1.1 volts because of the internal current source configuration. RS HI HCLK RS HCLKB HI RP RP LOAD Iref Rref PCK2023 SW00859 Figure 13. PCK2023 implementation in a circuit board 2001 Sep 07 23 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 S1 VDD 2<VDD Open VSS 500Ω VI VO PULSE GENERATOR D.U.T. RT CL TEST 500Ω S1 tPLH/tPHL Open tPLZ/tPZL 2<VDD tPHZ/tPZH VSS VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT SW00574 Figure 14. Host clock measurements TPERIOD DUTY CYCLE THIGH 2.5 V CLOCKING INTERFACE 2.0 V 1.25 V 0.4 V TLOW TRISE TFALL TPERIOD DUTY CYCLE THIGH 3.3 V CLOCKING INTERFACE (TTL) 2.4 V 1.5 V 0.4 V TLOW TRISE TFALL SW00860 Figure 15. 2.5 V/3.3 V clock waveforms 2001 Sep 07 24 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator AC WAVEFORMS PCK2023 VI VM = 1.25 V @ VDDL and 1.5 V @ VDD3 VX = VOL + 0.3 V VY = VOH – 0.3 V VOL and VOH are the typical output voltage drop that occur with the output load. SEL1, SEL0 VM GND tPLZ tPZL VDD VDDQ2 OUTPUT LOW-to-OFF OFF-to-LOW 1.25V CPUCLK @133MHz VM VX VOL VSS tPHZ VDDQ3 3v66 @66MHz tPZH VOH 1.5V VY OUTPUT HIGH-to-OFF OFF-to-HIGH VSS CPU leads 3V66 VSS THPOFFSET VM Outputs enabled Outputs disabled SW00569 SW00571 Figure 18. State enable and disable times Figure 16. Host clock COMPONENT MEASUREMENT POINTS 2.5VOLT MEASURE POINTS VOH = 2.0V VOL = 0.4V VDDQ2 VIH = 1.7V 1.25V VIL = 0.7V SYSTEM MEASUREMENT POINTS VSS COMPONENT MEASUREMENT POINTS 3.3VOLT MEASURE POINTS VOH = 2.4V VOL = 0.4V VDDQ3 VIH = 2.0V 1.5V VIL = 0.7V VSS SYSTEM MEASUREMENT POINTS SW00570 Figure 17. 3.3 V clock waveforms 2001 Sep 07 Outputs enabled 25 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 S1 VDD 2<VDD Open VSS 500Ω VI VO PULSE GENERATOR D.U.T. RT CL TEST 500Ω S1 tPLH/tPHL Open tPLZ/tPZL 2<VDD tPHZ/tPZH VSS VDD = VDDQ2 or VDDQ3, DEPENDS ON THE OUTPUT CL includes jig and probe capacitance SW00572 Figure 19. Load circuitry for switching times PWRDWN CPUCLK (INTERNAL) PCICLK (INTERNAL) PWRDWN CPUCLK (EXTERNAL) PCICLK (EXTERNAL) OSC & VCO USB (48 MHz) ÁÁ ÁÁ ÁÁ Figure 20. Power management 2001 Sep 07 26 SW00573 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 2001 Sep 07 27 PCK2023 SOT371-1 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm 2001 Sep 07 28 PCK2023 SOT364-1 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator NOTES 2001 Sep 07 29 PCK2023 Philips Semiconductors Product data CK408 (66/100/133/200 MHz) spread spectrum differential system clock generator PCK2023 Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-01 For sales offices addresses send e-mail to: [email protected]. Document order number: 2001 Sep 07 30 9397 750 09142