INTEGRATED CIRCUITS DATA SHEET TDA8785 8-bit high-speed analog-to-digital converter with gain and offset controls Product specification Supersedes data of 1996 Jan 17 File under Integrated Circuits, IC02 1997 Dec 18 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 • Gain, slow offset control inputs and DAC output swing of 1.5 V (p-p) range (2.75 ±0.75 V) FEATURES • 8-bit analog-to-digital converter (ADC) • 2.75 V reference voltage • 8-bit digital-to-analog converter (DAC) • Internal references for ADC and DAC. • Sampling rate up to 30 Msps for both ADC and DAC • Binary or two’s complement 3-state TTL outputs APPLICATIONS • TTL compatible inputs and outputs • 100 MHz variable gain amplifier (0 to 20 dB) externally controlled • CCD type of systems • All analog inputs and outputs are differential (can also be used in single-ended format) • Copier • Scanner • Video acquisition. • Analog input signal from 0.1 to 1.0 V (p-p) differential • Offset amplifier with: GENERAL DESCRIPTION – Slow offset control (±250 mV) The TDA8785 is an 8-bit analog-to-digital converter with gain and offset controls for the input signal. An internal 8-bit DAC provides fast offsets control. – Fast offset control (±500 mV) eventually driven by internal DAC. • ADC output code of 8 (typ.) when analog input signal and offset correction inputs are 0 V QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCCA1 analog supply voltage 1 4.75 5.0 5.25 V VCCA2 analog supply voltage 2 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO TTL output supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 80 − mA ICCD digital supply current − 30 − mA ICCO TTL output supply current − 9 − mA INL integral non-linearity 0 to 20 dB gain; ramp input − ±0.7 ±1.8 LSB DNL differential non-linearity 0 to 20 dB gain; ramp input − ±0.2 ±0.7 LSB fclk(max) maximum clock frequency ADC and DAC 30 − − MHz B controlled gain amplifier bandwidth − 100 − MHz Ptot total power dissipation − 600 − mW ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION TDA8785H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2 1997 Dec 18 2 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 BLOCK DIAGRAM handbook, full pagewidth VCCA1 VCCA2 1 AGND1 2 3 VRB Vref B AGND2 4 6 7 DEC2 OF DEC1 36 5 35 34 REGULATORS Vi(p) Vi(n) VSOFF(p) VSOFF(n) VFOFF(p) VFOFF(n) VFSAD(p) VFSAD(n) 43 44 37 38 42 41 OFFSET AMPLIFIER GAIN ADC 8 TTL OUTPUTS 26 to 33 39 40 VCCA 150 Ω VDACO(p) VDACO(n) 9 8 VFSDAC(p) 10 VFSDAC(n) 11 25 150 Ω 24 TDA8785 VCCO OGND DAC CLOCK DRIVER 8 12 to 19 DA7 to DA0 CLOCK DRIVER 20 22 CLKDAC CLKADC Fig.1 Block diagram. 1997 Dec 18 AD0 to AD7 8 3 23 21 VCCD DGND MBG681 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 PINNING SYMBOL PIN DESCRIPTION SYMBOL PIN DESCRIPTION VCCA1 1 analog supply voltage 1 (+5 V) OGND 24 output ground VCCA2 2 analog supply voltage 2 (+5 V) VCCO 25 output supply voltage (+5 V) AGND1 3 analog ground 1 AD0 26 output data; bit 0 (LSB) AGND2 4 analog ground 2 AD1 27 output data; bit 1 DEC2 5 decoupling input 2 AD2 28 output data; bit 2 B 6 bandwidth adjustment node input AD3 29 output data; bit 3 VRB 7 ADC reference voltage output bottom (decoupling) AD4 30 output data; bit 4 AD5 31 output data; bit 5 VDACO(n) 8 DAC negative voltage output AD6 32 output data; bit 6 VDACO(p) 9 DAC positive voltage output AD7 33 output data; bit 7 (MSB) VFSDAC(p) 10 DAC full-scale positive control voltage input OF 34 output format input DEC1 35 decoupling input 1 Vref 36 reference voltage output (2.75 V) VSOFF(p) 37 slow offset amplifier positive voltage input VSOFF(n) 38 slow offset amplifier negative voltage input VFSDAC(n) 11 DAC full-scale negative control voltage input DA7 12 DAC TTL input; bit 7 (MSB) DA6 13 DAC TTL input; bit 6 DA5 14 DAC TTL input; bit 5 DA4 15 DAC TTL input; bit 4 VFSAD(p) 39 gain control positive voltage input DA3 16 DAC TTL input; bit 3 VFSAD(n) 40 gain control negative voltage input DA2 17 DAC TTL input; bit 2 VFOFF(n) 41 DA1 18 DAC TTL input; bit 1 fast offset amplifier negative voltage input DA0 19 DAC TTL input; bit 0 (LSB) VFOFF(p) 42 CLKDAC 20 DAC clock input fast offset amplifier positive voltage input DGND 21 digital ground Vi(p) 43 analog positive voltage input Vi(n) 44 analog negative voltage input CLKADC 22 ADC clock input VCCD 23 digital supply voltage (+5 V) 1997 Dec 18 4 Philips Semiconductors Product specification 34 OF VCCA1 1 33 AD7 VCCA2 2 32 AD6 AGND1 3 31 AD5 AGND2 4 30 AD4 DEC2 5 29 AD3 TDA8785 26 AD0 VDACO(p) 9 25 VCCO VFSDAC(p) 10 24 OGND VFSDAC(n) 11 23 VCCD 5 CLKADC 22 DGND 21 CLKDAC 20 28 AD2 DA0 19 DA1 18 8 DA2 17 VDACO(n) DA3 16 27 AD1 DA4 15 7 DA5 14 VRB DA6 13 6 DA7 12 B Fig.2 Pin configuration. 1997 Dec 18 35 DEC1 TDA8785 36 Vref 37 VSOFF(p) 38 VSOFF(n) 39 VFSAD(p) 40 VFSAD(n) 41 VFOFF(n) 43 Vi(p) 44 Vi(n) handbook, full pagewidth 42 VFOFF(p) 8-bit high-speed analog-to-digital converter with gain and offset controls MBG680 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 The internal 8-bit DAC operates at the ADC clock rate to allow dynamic corrections on the input signal chain based on the signal processing information carried out after the digital conversion. The output voltage amplitude of the DAC can be controlled via a different input voltage (which can also be single) in a range of ±25% with a 150 Ω DAC output load. FUNCTIONAL DESCRIPTION The TDA8785 is composed of an 8-bit ADC (30 Msps), a wide-band gain amplifier, an input offset amplifier and an 8-bit dynamic adjustment DAC. Input signal Two input pins are provided to apply a differential input signal with a wide range (100 to 1000 mV differential). It is also possible to apply a single signal by setting a DC voltage on one of the differential pins and supplying the signal to the other. The DAC can also be used for the gain or the slow offset control with some external DC voltage adaptations and can be considered as a separate function of the ADC chain. The DAC can be used independently, for example as a video DAC. Controlled gain amplifier 8-bit ADC The gain amplifier is used to adjust the wide input signal range to the fixed ADC input range of 1 V (p-p). The 8-bit ADC converts a signal of 1 V (p-p) from the controlled gain amplifier into an 8-bit coded digital word at a maximum rate of 30 Msps. Its reference voltage is supplied by the general voltage regulator. The output data format can either be binary, two’s complement or 3-state by selecting pin OF. A large gain of 20 dB can be achieved with low-noise behaviour and a large bandwidth of 100 MHz to correctly amplify square type signals with step edges. Using pin 6, it is possible to reduce the internal bandwidth of the gain amplifier via an external capacitor and thus improve its noise behaviour. The gain amplifier is controlled via an external differential voltage (single input can also be applied). When all the differential inputs on the offset amplifier (VSOFF(p), VSOFF(n), VFOFF(n), VFOFF(p), Vi(p) and Vi(n)) are at 0 V (equivalent to both inputs short-circuited), the output code of the ADC is code 8. Input offset amplifier and adjustment DAC Internal voltage regulator The Input offset amplifier contains two different control inputs (which can also be single): An internal voltage regulator provides all the references for the different blocks. A stable 2.75 V voltage reference output is provided for use in the application environment. One application is to connect all the slow control inputs (VFSDAC(p), VFSDAC(n), VSOFF(p), VSOFF(n), VFSAD(p) and VFSAD(n)) to this reference, either to their two differential inputs to get the nominal settings or to one of the differential inputs to have easy single-input control. • Slow offset control, for slow variation characteristics (e.g. temperature, supply voltage, etc.) • Fast offset control, for correction related to the clock rate. Slow offset control is carried out by an external voltage while fast offset control is digitally carried out via the internal 8-bit DAC with external connections of the respective pins VDACO(n), VDACO(p), VFOFF(n) and VFOFF(p). 1997 Dec 18 All these control inputs have the same control range. 6 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCCA analog supply voltage −0.3 +7.0 V VCCD digital supply voltage −0.3 +7.0 V VCCO output supply voltage −0.3 +7.0 V ∆VCC supply voltage difference between VCCA and VCCD −1.0 +1.0 V VCCD and VCCO −1.0 +1.0 V −1.0 +1.0 V referenced to AGND −0.3 +7.0 V VCCD V VCCA and VCCO Vi input voltage Vclk(p-p) clock input voltage for switching (peak-to-peak value) referenced to DGND − Io output current − 6 mA Tstg storage temperature −55 +150 °C Tamb operating ambient temperature 0 70 °C Tj junction temperature − 150 °C THERMAL CHARACTERISTICS SYMBOL Rth j-a 1997 Dec 18 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 7 VALUE UNIT 75 K/W Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 CHARACTERISTICS VCCA1 = VCCA2 = VCCD = VCCO = 4.75 to 5.25 V; AGND, DGND and OGND short-circuited together; VCCA to VCCD = VCCD to VCCO = VCCA to VCCO = −0.25 to +0.25 V; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VCCA1 analog supply voltage 1 4.75 5.0 5.25 V VCCA2 analog supply voltage 2 4.75 5.0 5.25 V VCCD digital supply voltage 4.75 5.0 5.25 V VCCO TTL output supply voltage 4.75 5.0 5.25 V ICCA analog supply current − 80 − mA ICCD digital supply current − 37 − mA ICCO TTL output supply current − 9 − mA Reference voltages (pins Vref and VRB) Vo(ref) output reference voltage Vline line regulation voltage Io(L) 2.60 2.75 2.90 V − 4 − mV output load current −0.5 − +0.5 mA VRB reference voltage output bottom (decoupling) − VCCA − 2.5 − V Voffset(B) offset voltage bottom code 0 − VRB − 250 − mV ∆VADC ADC reference voltage difference between code 0 and 255 − 1 − V VCCA = 4.75 to 5.25 V Analog inputs (pins Vi(p) and Vi(n)); see Table 1 Vi(diff)(p-p) differential input voltage Vi(p) − Vi(n) (peak-to-peak value) 0 dB gain − 1000 − mV 20 dB gain − 100 − mV VI DC input voltage 2.5 3.0 3.5 V Ii input current − 7 − µA Zi input impedance − 20 − kΩ Ci input capacitance − 1 − pF Fast offset amplifier inputs (pins VFOFF(p) and VFOFF(n)); DC parameters VFOFF(p) positive input voltage 0 dB gain − 500 − mV 20 dB gain − 50 − mV 0 dB gain − 500 − mV 20 dB gain − 50 − mV VFOFF(n) negative input voltage VI DC input voltage VCCA − 0.75 VCCA − 0.25 VCCA V Ii input current − 4 − µA Zi input impedance − 20 − kΩ Ci input capacitance − 1 − pF 1997 Dec 18 8 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls SYMBOL PARAMETER TDA8785 CONDITIONS MIN. TYP. MAX. UNIT Slow offset amplifier inputs (pins VSOFF(p) and VSOFF(n)) gain amplifier at 0 dB; note 1 Voffset(ADC) offset voltage at ADC input Ii VSOFF(p) = 2 V; VSOFF(n) = 2.75 V − −0.25 − V VSOFF(p) = 2.75 V; VSOFF(n) = 2.75 V − 0 − V VSOFF(p) = 3.5 V; VSOFF(n) = 2.75 V − 0.25 − V − 10 − µA − 8 − code −15 0 +15 code input current Offset reference code; Tamb = 25 °C OFSRE offset reference (ADC output code) OFSER offset reference error on code 8 Vi(p) = Vi(n); VFOFF(p) = VFOFF(n); VSOFF(p) = VSOFF(n); amplifier gain set at 0 dB Gain control inputs (pins VFSAD(p) and VFSAD(n)); see Fig.7 Gv(min) minimum voltage gain VFSAD(p) = 2 V; VFSAD(n) = 2.75 V − − 0 dB Gv(max) maximum voltage gain VFSAD(p) = 3.5 V; VFSAD(n) = 2.75 V 20 − − dB Ii input current − 10 − µA DAC full-scale control inputs (pins VFSDAC(p) and VFSDAC(n)) 150 Ω output load on pins VDACO(p) and VDACO(n); see Table 3 VDACO(n) Ii DAC negative output voltage (pin 8) VCCA − V code 255 at DAC inputs; − VFSDAC(p) = 2 V; VFSDAC(n) = 2.75 V VCCA − 0.4 − V code 255 at DAC inputs; − VFSDAC(p) = 2.75 V; VFSDAC(n) = 2.75 V VCCA − 0.5 − V code 255 at DAC inputs; − VFSDAC(p) = 3.5 V; VFSDAC(n) = 2.75 V VCCA − 0.6 − V − 1 − µA − 500 − Ω − 150 − Ω code 0 at DAC inputs input current − Bandwidth adjustment node input (pin B); see Fig.6 Zi input impedance 8-bit DAC; fclk = 30 MHz, ramp input; Tamb = 25 °C Zo output impedance INL integral non-linearity − ±0.4 ±0.8 LSB DNL differential non-linearity − ±0.4 ±1.0 LSB 1997 Dec 18 9 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls SYMBOL PARAMETER TDA8785 CONDITIONS MIN. TYP. MAX. UNIT Digital inputs (pins CLKDAC, CLKADC and DA7 to DA0) VIL LOW-level input voltage 0 − 0.8 VIH HIGH-level input voltage 2.0 − VCCD V IIL LOW-level input current VIL = 0.4 V −400 − − µA V IIH HIGH-level input current VIH = 2.7 V − − 100 µA Zi input impedance fclk = 10 MHz − 4 − kΩ Ci input capacitance fclk = 10 MHz − 4.5 − pF V ADC output format (pin OF); see Table 2 VIL LOW-level input voltage 0 − 0.2 VIH HIGH-level input voltage 2.6 − VCCD V Vi(Z) input voltage in high impedance state − 1.20 − V IIL LOW-level input current VIL = 0.4 V −370 −130 − µA IIH HIGH-level input current Vclk = 2.7 V − 300 450 µA V ADC digital outputs VOL LOW-level output voltage IOL = 2 mA 0 − 0.6 VOH HIGH-level output voltage IOH = −0.4 mA 2.4 − VCCO V note 2 30 − − MHz ADC and DAC switching; see Fig.4 fclk(max) maximum clock frequency tCPH clock pulse width HIGH 12 − − ns tCPL clock pulse width LOW 12 − − ns − ±0.7 ±1.8 LSB ±0.2 ±0.7 LSB 47 − dB Analog processing; note 3 INL integral non-linearity ramp input (full-scale); 0 to 20 dB gain DNL differential non-linearity ramp input (full-scale); 0 to 20 dB gain S/N signal-to-noise ratio (without harmonics) fi = 2 MHz B 1997 Dec 18 bandwidth 0 dB gain − 10 dB gain − 45 − dB 20 dB gain − 43 − dB − 100 − MHz −3 dB 10 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls SYMBOL PARAMETER TDA8785 CONDITIONS MIN. TYP. MAX. UNIT Timing ADC DIGITAL OUTPUTS (CL = 15 pF) tds sampling delay time − 1.5 − ns th output hold time 7 − − ns td output delay time − − 16 ns DAC OUTPUTS (PINS VDACO(p) AND VDACO(n)) tSU; DAT data set-up time note 4 −0.3 − − ns tHD; DAT data hold time note 4 − − 2 ns tS DAC setting time (10 to 90%) RL = 150 Ω; CL = 15 pF − 8 − ns RSA residual setting accuracy note 5; see Fig.8 0.1 2.5 % 3-STATE OUTPUT DELAY TIMES (see Fig.5) tdZH enable HIGH − 15 20 ns tdZL enable LOW − 15 20 ns tdHZ disable HIGH − 13 20 ns tdLZ disable LOW − 10 20 ns Notes 1. Vos is proportional to the amplifier gain. For instance, Vos at 20 dB is the one indicated at 0 dB multiplied by 10. 2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and analog grounds is recommended. 3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; fclk = 30 MHz; no external filtering on pin 6 (B). 4. The data set-up time (tSU; DAT) is the minimum period preceding the rising edge of the clock, that the input data must be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the rising edge and still be recognized. The data set hold time (tHD; DAT) is the minimum period following the rising edge of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that the data may be released prior to the rising edge and still be recognized. 5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour. The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time tX. 1997 Dec 18 11 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls Table 1 TDA8785 Output coding and input voltage (typical values; referenced to AGND, Vi(p) − Vi(n) = 1 V (p-p), 0 dB gain, no offset correction Vi(p) − Vi(n) STEP BINARY OUTPUT BITS TWO’S COMPLEMENT OUTPUT BITS D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Underflo w →0.032 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 −0.032 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 − 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 . − . . . . . . . . . . . . . . . . 8 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 . − . . . . . . . . . . . . . . . . 254 − 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 255 0.968 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Overflow >0.968 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Table 2 OF input coding OF AD0 to AD7 0 active, two’s complement 1 high impedance open circuit; note 1 active, binary Note 1. Use C ≥ 10 pF to DGND. Table 3 Input coding and DAC output voltages (typical values; referenced to VCCA regardless of the offset voltage); VFSDAC(p) = VFSDAC(n) BINARY INPUT DATA DAC OUTPUT VOLTAGES (V) CODE DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 ZL = 10 kΩ ZL = 150 Ω VDACO(p) VDACO(n) VDACO(p) VDACO(n) 0 0 0 0 0 0 0 0 0 −1.0 0 −0.5 0 1 0 0 0 0 0 0 0 1 − − − − . . . . . . . . . . . . . 128 1 0 0 0 0 0 0 0 −0.5 −0.5 −0.25 −0.25 . . . . . . . . . . . . . 254 1 1 1 1 1 1 1 0 − − − − 255 1 1 1 1 1 1 1 1 0 −1.0 0 −0.5 1997 Dec 18 12 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls t SU; DAT handbook, full pagewidth TDA8785 t HD; DAT 3.0 V input data stable 1.4 V 0V 3.0 V 1.4 V CLKDAC 0V MBG682 The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns, after the first rising edge of the clock (tSU; DAT is negative; −0.3 ns). Data must be held at least 2 ns after the rising edge (tHD; DAT = +2 ns). Fig.3 Data set-up and hold times (DAC). t CPL handbook, full pagewidth t CPH 1.4 V CLKADC sample N sample N + 1 sample N + 2 Vi(p) − Vi(n) t ds th 2.4 V DATA AD0 to AD7 DATA N-2 DATA N-1 DATA N DATA N+1 1.4 V 0.4 V td Fig.4 Timing diagram. 1997 Dec 18 13 MBG683 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 V CCD handbook, full pagewidth 50 % OF 1.15 V t dHZ t dZH HIGH 90 % output data 50 % HIGH Z t dLZ t dZL HIGH Z output data 50 % LOW 10 % V CCD 3.3 kΩ S1 TDA8785 15 pF TEST S1 t dLZ t dZL VCCD VCCD t dHZ GND t dZH GND OF MBG684 fOF = 100 kHz. Fig.5 Timing diagram and test conditions of 3-state output delay time. MBG691 102 handbook, halfpage (1) f−3 dB handbook, halfpage Gv (dB) S/N (dB) (MHz) MBG692 25 48 20 46 10 15 (2) 10 1 44 5 10−1 10−1 1 10 102 CB (pF) 42 103 0 −0.75 −0.50 −0.25 0 0.50 0.75 0.25 VFSAD(p) − VFSAD(n) (V) (1) f−3 dB. (2) Signal-to-noise ratio. The controlled gain amplifier is set at 20 dB gain. Fig.6 Gain amplifier bandwidth and acquisition chain S/N ratio as a function of the external capacitance on pin 6. 1997 Dec 18 Fig.7 14 Typical amplifier gain (Gv) as a function of the differential input voltage; VFSAD(p) − VFSAD(n). Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 MBK516 handbook, full pagewidth VDACO RSA (%) 100 90 10 0 ts t tx Fig.8 DAC time response when a full-scale step is applied. INTERNAL PIN CONFIGURATIONS handbook, halfpage ook, halfpage VCCO VCCA VFSDAC(p), VSOFF(p), VFSAD(p), VFOFF(p), Vi(p) or VFSDAC(n), VSOFF(n), VFSAD(n), VFOFF(n), Vi(n) AD0 to AD7 AGND DGND MBG686 MBG685 Fig.10 Analog inputs. Fig.9 TTL data outputs. 1997 Dec 18 15 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 andbook, halfpage dbook, halfpage VCCA VCCA 500 Ω RLAD B VRB AGND AGND MBG688 MBG687 Fig.11 Bandwidth input (B). Fig.12 VRB. ndbook, halfpage VCCD handbook, halfpage 40 kΩ DA7 to DA0 or CLKDAC or CLKADC 200 Ω 150 Ω 150 Ω VDACO(p) VDACO(n) MBG690 DGND MBG689 Fig.13 DAC inputs. 1997 Dec 18 Fig.14 DAC outputs. 16 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 APPLICATION INFORMATION handbook, full pagewidth B AGND1 VCCA1 AGND2 VCCA2 1 VCCA1 2 pF 2 3 4 6 Vref DEC2 DEC1 OF 3.3 nF VRB 100 nF 7 36 10 pF 100 nF 5 35 1 nF 34 REGULATORS Vi(p) Vi(n) VSOFF(p) VSOFF(n) VFOFF(p) VFOFF(n) VFSAD(p) VFSAD(n) VCCA 150 Ω 150 Ω VDACO(p) 43 44 37 38 OFFSET AMPLIFIER GAIN ADC AD0 to AD7 42 41 39 40 VCCA 150 Ω 25 150 Ω 24 9 8 VDACO(n) VFSDAC(p) 10 VFSDAC(n) 11 TDA8785 VCCO OGND DAC CLOCK DRIVER 8 12 to 19 DA7 to DA0 CLOCK DRIVER 20 22 CLKDAC CLKADC Fig.15 Application diagram. 1997 Dec 18 26 to 33 TTL OUTPUTS 8 8 17 23 21 VCCD DGND MBG693 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 10 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT307-2 1997 Dec 18 EUROPEAN PROJECTION 18 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction •A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. •The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1997 Dec 18 TDA8785 19 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls TDA8785 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Dec 18 20 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls NOTES 1997 Dec 18 21 TDA8785 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls NOTES 1997 Dec 18 22 TDA8785 Philips Semiconductors Product specification 8-bit high-speed analog-to-digital converter with gain and offset controls NOTES 1997 Dec 18 23 TDA8785 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/02/pp24 Date of release: 1997 Dec 18 Document order number: 9397 750 03005