DS92LV8028 8 Channel 10:1 Serializer General Description Features The DS92LV8028 integrates eight serializer devices into a single chip. The DS92LV8028 can simultaneously serialize up to eight 10-bit data streams. The 10-bit parallel inputs are LVTTL signal levels. The serialized outputs are LVDS signals with extra drive current for point-to-point and lightly loaded multidrop applications. Each serializer block in the DS92LV8028 operates independently by using strobes from a single shared PLL. The DS92LV8028 uses a single +3.3V power supply with a typical power dissipation of 740mW (3.3V / PRBS / 66 MHz). Each serializer channel has a unique power down control to further conserve power consumption. For high-speed LVDS serial data transmission, line quality is essential, thus the DS92LV8028 includes an @SPEED TEST function. Each Serializer channel has the ability internally generated a PRBS data pattern. This pattern is received by specific deserializers (SCAN921224) which have the complement PRBS verification circuit. The deserializer checks the data pattern for bit errors and reports any errors on the test verification pins on the deserializer. For additional information - please see the Applications Information section in this datasheet. n All 8 channels synchronous to one parallel clock rate, from 25 to 66 MHz n Duplicates function of multiple DS92LV1021 and ’1023 10-bit Serializer devices n Serializes from one to eight 10-bit parallel inputs into data streams with embedded clock n Eight 5 mA modified Bus LVDS outputs that are capable to drive double terminations n @Speed Test - PRBS generation to check LVDS transmission path to SCAN921224 or SCAN921260 n On chip filtering for PLL n 740mW typ power dissipation (loaded, PRBS, 66MHz, 3.3V) n High impedance inputs and outputs on power off n Single power supply at +3.3V (+/-10%) n 196-pin LBGA package n JTAG pins reserved for next version of device n Industrial temperature range operation: -40 to +85 ˚C Block Diagram 20027201 © 2003 National Semiconductor Corporation DS200272 www.national.com DS92LV80288 Channel 10:1 Serializer August 2003 DS92LV8028 Absolute Maximum Ratings Junction Temperature (Note 1) Lead Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Soldering, 10 seconds) −0.3V to +4V Reliability Information LVCMOS/LVTTL Input Voltage −0.3V to (VCC +0.3V) Transistor Count: −0.3V to +3.9V Bus LVDS Output Short Circuit Duration 10ms 34˚C/W θJC 196 LBGA: Storage Temperature ± 3.0kV 37.5k Recommended Operating Conditions Package Thermal Resistance θJA 196 LBGA: +225˚C ESD Rating (HBM) Supply Voltage (VCC) Bus LVDS Driver Output Voltage +125˚C 8˚C/W Min Typ Max Units Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Clock Rate 25 66 MHz −65˚C to +150˚C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.(Note 2) (Note 3) Symbol Parameter Conditions Pin/Freq. Min DINn[0-9], TCLK, MS_PWDN, PWDNn, SYNCn, DEN, BIST_ACT, BIST_SEL < 0:3 > (Note 4) Typ Max Units 2.0 VCC V GND 0.8 V −0.87 −1.5 V +/− 1 +10 µA 500 550 mV 3 35 mV 1.2 1.3 V 2 35 mV −50 -90 mA LVCMOS/LVTTL DC Specifications VIH High Level Input Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage ICL = −18 mA IIN Input Current VIN = 0V or 3.6V −10 Bus LVDS DC SpecificationsOver recommended operating supply and temperature unless otherwise specified. VOD Output Differential Voltage (DO+) - (DO-) ∆VOD Output Differential Voltage Unbalance VOS Offset Voltage ∆VOS Offset Voltage Unbalance 350 RL = 100Ω, CL = 10pF to GND 1.1 IOS Output Short Circuit Current DO = 0V, Din = H, MS_PWDN and DEN = 2.4V IOZ Tri-State Output Current MS_PWDN or DEN = 0.8V, DO = 0V OR VDD -10 +/-1 10 µA IOX Power-Off Output Current VDD = 0V, DO = 0V or 3.6V -10 +/− 1 10 µA www.national.com 2 DOn+, DOn- (Continued) Over recommended operating supply and temperature ranges unless otherwise specified.(Note 2) (Note 3) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units SER/DES SUPPLY CURRENT (apply to pins DVDD, PVDD and AVDD)Over recommended operating supply and temperature ranges unless otherwise specified. ICCD ICCXD Supply Current (SYNC pattern) VCC = 3.6V, RL = 100 Ω f = 25MHz 145 mA f = 66MHz 175 mA Worst Case Supply Current (Checker-board pattern) VCC = 3.6V, RL = 100 Ω Figure 1 f = 25 MHz 148 166 mA f = 66 MHz 263 350 mA Supply Current Powered Down MS_PWDN = 0.1V, DEN = 0V 22 200 µA Worst Cast Power Saving Per Channel Disabled MS_PWDN = 3V, PWDNn = 0V (Master) ICCXD (Ind. Ch) 66 MHz 6 mA 25 MHz 3.6 mA Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 2, 3) Symbol Parameter tTCP Transmit Clock Period Conditions 15.15 tTCIH Transmit Clock High Time 40 tTCIL Transmit Clock Low Time 40 tCLKT TCLK Input Transition Time tJIT TCLK Input Jitter Figure 3 Pin/Freq. TCLK Min Typ Max Units 40 ns 50 60 % 50 60 % 3 6 ns 80 psrms Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 2, 3) Symbol Parameter tLLHT Bus LVDS Low-to-High Transition Time tLHLT Bus LVDS High-to-Low Transition Time tDIS DIN (0-9) Setup to TCLK tDIH DIN (0-9) Hold from TCLK tHZD DO ± HIGH to TRI-STATE Delay tLZD DO ± LOW to TRI-STATE Delay tZHD DO ± TRI-STATE to HIGH Delay tZLD DO ± TRI-STATE to LOW Delay tSPD SYNC Pattern Delay, Figure 8 tPLD Serializer PLL Lock Time, Figure 6 Conditions RL = 100Ω CL=10pF to GND (Note 5) Figure 2 RL = 100Ω, CL=10pF to GND Figure 4 RL = 100Ω, CL=10pF to GND Figure 5 RL = 100Ω CL=10pF to GND Pin/Freq. Min Typ Max Units 198 236 400 ps 115 232 400 ps DOn+, DOn- 1.5 ns 1.5 ns DINn(0-9), TCLK 5.7 12 ns 6.9 12 ns 6.2 12 ns 5.8 12 ns 4*tTCP 5*tTCP ns 510*tTCP 513*tTCP ns DOn+, DOn-, DEN TCLK, SYNCn, DOn+, DOn-, MS_PWDN 3 www.national.com DS92LV8028 Electrical Characteristics DS92LV8028 Serializer Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 2, 3) Symbol Parameter Conditions Pin/Freq. Min Typ Max Units tSD Serializer Delay RL = 100Ω CL=10pF to GND Figure 7 DINn(0-9), TCLK, DOn+, DOn- tTCP + 3.2 tTCP + 3.5 tTCP + 6 ns tICR Individual Channel Power up Time TCLK, DOn+, DOn-, PWDNn 60*tTCP 63*tTCP 70*tTCP ns TCLK, DOn+, DOn-, MS_PWDN Figure 6 510*tTCP 513*tTCP ns tMCR tSTE tSTD tSKEW Master Power up Time @ Speed Test Enable RL = 100Ω Time @ Speed Test Disable RL = 100Ω Time Channel to Channel Skew RL = 100Ω, CL=10pF to GND Random Jitter RL = 100Ω, CL=10pF to GND (Note 5) (Note 6) tRJIT tDJIT RL = 100Ω, CL=10pF to GND Deterministic Jitter, Figure 9 RL = 100Ω, CL=10pF to GND (Note 5) (Note 7) BIST_ACT, BIST_SEL (0:3), TCLK, DOn+, DOn- 10*tTCP ns 7*tTCP ns 25 MHz 130 ps 66 MHz 80 ps 25MHz 18.4 20.7 ps 66MHz 7.5 8.8 ps 25MHz −130 −45 40 ps 66MHz −190 −92 −40 ps Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, and ∆VOD which are differential voltages. Note 4: BIST_SEL pins are pull-up internally. Note 5: tLLHT, tLHLT, tDJIT and tRJIT specifications are Guaranteed by Design using statistical analysis. Note 6: tRJIT specification is the rms jitter measurement of the serializer output when the device is transmitting SYNC pattern. Note 7: tDJIT specification is measured with the serializer output transmitting PRBS pattern from the internal BIST mode. It is a measurement of the center distribution of 0V (differential) crossing in comparsion with the ideal bit position. See Figure 9 AC Timing Diagrams and Test Circuits 20027203 FIGURE 1. ’Worst Case Icc Test Pattern www.national.com 4 DS92LV8028 AC Timing Diagrams and Test Circuits (Continued) 20027204 FIGURE 2. Serializer Bus LVDS Output Load and Transition Times 20027205 FIGURE 3. Serializer Input Clock Transition Time 20027206 FIGURE 4. Serializer Setup/Hold Times 5 www.national.com DS92LV8028 AC Timing Diagrams and Test Circuits (Continued) 20027207 FIGURE 5. Serializer Input Clock Transition Time TRI-STATE Test Circuit and Timing 20027208 FIGURE 6. Serializer PLL lock Time and MS_PWDN TRI-STATE Delays 20027209 FIGURE 7. Serializer Delay www.national.com 6 DS92LV8028 AC Timing Diagrams and Test Circuits (Continued) 20027212 FIGURE 8. SYNC Timing Delays 20027211 FIGURE 9. Deterministic Jitter and Ideal Bit Position 20027213 FIGURE 10. Icc vs Freq 7 www.national.com DS92LV8028 Functional Description The DS92LV8028 combines eight 10:1 serializers into a single chip. Each of the eight serializers accepts 10 or less data bits. The serializers then multiplex the data into a serial stream with embedded clock bits and route to the LVDS output. The LVDS output is a 5 mA current loop driver. It provides enough drive for point-to-point and lightly loaded multidrop applications. The serialized data stream is compatible with the DS92LV1210, DS92LV1212A, DS92LV1224, DS92LV1260 10-bit deserializers from National Semiconductor. Each of the eight channels on the DS92LV8028 has their own serializer function but share a single PLL. There is a single Transmit Clock (TCLK) for all eight channels. The data on all eight 10-bit interfaces is latched into the device with the rising edge of TCLK. Each of the serialized data streams is independent of the others and includes the embedded clock information. The skew between the serializer outputs is minimal. There is a master power-down signal (MS_PWDN) to put the entire device into a low power consumption state. In addition, there is a power-down control signal for each of the eight channels. This allows the device to efficiently operate as one to eight 10-bit serializers. The @SPEED TEST signal initiates the sending of a random data pattern over the LVDS links. This allows for testing the links for bit error rates at the frequency they will be carrying data. In addition, the JTAG boundary scan circuits will be added to the device at a later date. The JTAG signal pins are reserved on this version. See package connection diagram. The DS92LV8028 has four operating modes. They are the Initialization, Data Transfer, Resynchronization, @SPEED TEST states. In addition, there are two passive states: Power-down and TRI-STATE. The following sections describe each operating mode and passive state. from the Serializer after some delay. At the point where the Deserializer’s PLL locks to the embedded clock, the LOCK pin goes low and valid data appears on the output. The user’s application determines control of the SYNC signal input. One recommendation is a direct feedback loop from the LOCK pin on the deserializer. The serializer stops sending SYNC patterns when the SYNC input returns to a low state. Data Transfer After initialization, the serializer accepts data from the inputs DINn0 to DINn9. The serializer uses the rising edge of the TCLK input to latch incoming data. If the SYNCn input is high for 4 TCLK cycles, the data on DINn0-DINn9 is ignored and SYNC pulses are transferred. The serial data stream includes a start bit and stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial ’payload’ rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data rate is 40 X 10 = 400 Mbps. TCLK is provided by the data source and must be in the range 25 MHz to 66 MHz nominal. The serializer outputs (DO0 ± – DO7 ± ) can drive a point-topoint connection or lightly loaded multidrop connections. The outputs transmit data when the driver enable pin (DEN) is high, MS_PWDN and PWDNn are high, and SYNCn is low. When DEN is driven low, all the serializer output pins will enter TRI-STATE. When any one of eight attached Deserializer channels synchronizes to the input from the Serializer, it drives its LOCK pin low and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to generate multiple internal data strobes, and drives the embedded clock on the RCLK pin. The RCLK is synchronous to the data on the ROUT pins. While LOCK is low, data on ROUT is valid. Otherwise, ROUT is invalid. Initialization Before the ’8028 serializes and transmits data, it and the receiving deserializer device(s) must initialize the link. Initialization refers to synchronizing the Serializer’s and the Deserializer’s PLLs to local clocks. The local clocks should be the same frequency, or within the specified range if from different sources. After all devices synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step. Step 1: After applying power to the serializer, the outputs are held in TRI-STATE and the on-chip power-sequencing circuitry disables the internal circuits. When Vcc reaches VccOK (2.1V), the PLL in the serializer begins locking to the local clock (TCLK). A local on-board data source or other source provides the specified clock input to the TCLK pin. After locking to TCLK, the serializer is now ready to send data or SYNC patterns, depending on the level of the SYNC input or a data stream at the data inputs. The SYNC pattern sent by the serializer consists of six ones and six zeros switching at the input clock rate. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. (Refer to the deserializer data sheet for operation details during this step of the Initialization State.) The Deserializer identifies the rising clock edge in a synchronization pattern or non-repetitive data pattern. Depending on the data pattern that it is being transmitted, the Deserializer will synchronize to the data stream www.national.com Resynchronization Whenever one of the connected DS92LV1212, ’1212A, ’1224, or ’1260 deserializers loses lock, it will automatically try to resynchronize to the data stream from the serializer. If the data stream is not a repetitive pattern, then the deserializer will automatically lock. For example, if the deserializer’s received embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCK pin is driven high. The ’1212, ’1212A, ’1224, or ’1260 deserializers will automatically begin searching for the embedded clock edge. If it is a random data pattern, the deserializer will lock to that stream. If the data pattern is repetitive, the deserializer’s PLL will not lock in order to prevent the deserializer to lock to the data pattern rather than the clock. We refer to such patterns as repetitivemultiple-transition, RMT. Therefore, if the data stream is not random data or the deserializer is the DS92LV1210, there needs to be a feedback path from the deserializer to the serializer. This feedback path can be as simple as connecting the deserializer’s 8 serializers will return to the previous state as long as all other control pins remain static (PWDNn, TCLK, SYNCn, and DINn[0:9]). (Continued) LOCK pin to the serializer’s SYNC pin. This will automatically signal the serializers to send SYNC patterns whenever the deserializer loses lock. @ SPEED Test Feature Since the high-speed LVDS serial data transmission line quality is essential to the chipset operation, a means of checking this signal integrity is built into the DS92LV8028 serializer. Each Serializer channel has the ability to transfer an internally generated PRBS data pattern. This pattern traverses the transmission line to the deserializer. Specific deserializers (SCAN921224 for example) have the complement PRBS pattern verification circuit. The deserializer checks the data pattern for bit errors and reports any errors on the test verification pins on the deserializer. The @SPEED feature uses 5 signal pins. The BIST_SEL[0:3] and BIST_ACT pins together determine the functions of the BIST mode. The BIST_ACT signal activates the test feature. The BIST_SEL[0:2] select 1 of 8 channels as the output for the BIST pattern. All channels perform BIST when BIST_ACT = H and BIST_SEL[0:3]=08H. The user has the choice of allowing the deserializer to resynchronize to the data stream, or to force synchronization by pulsing the Serializer SYNC pin. This scheme is left up to the user discretion. Power-down The Power-down state is a low power sleep mode that the Serializer and Deserializer typically occupy while waiting for initialization, or to reduce power when there are no pending data transfers. The DS92LV8028 serializers enter Powerdown when MS_PWDN is driven low. In Power-down, the PLL stops and the outputs go into TRI-STATE. To exit Powerdown, the system drives MS_PWDN high. Each of the serializers in the ’8028 also has an individual power down, PWDNn control pin. This control enables the deactivation of individual serializers while allowing others to operate normally. The benefit is that spare serializers can be allocated for backup operation, but not consuming power until employed for data transfers. Upon exiting Power-down, the Serializer enters the Initialization state. The system must then allow time to initialize before data transfer can begin. The JTAG pins are reserved on this version of the serializer. They will be JTAG compliant functionality on the next version. The @SPEED test will also be available through a JTAG command when available. TRI-STATE When the system drives DEN pin low, the serializer outputs enter TRI-STATE. This will TRI-STATE the output pins (DO0 ± to DO7 ± ). When the system drives DEN high, the TABLE 1. Truth Table (BIST mode) No BIST function performed when BIST_SEL (0:3) are set from 9H to FH even when BIST_ACT is set at HIGH. See (Note 4) BIST_ACT BIST_SEL < 3 > BIST_SEL < 2 > BIST_SEL < 1 > BIST_SEL < 0 > MODE H L L L L BIST on channel 0 H L L L H BIST on channel 1 H L L H L BIST on channel 2 H L L H H BIST on channel 3 H L H L L BIST on channel 4 H L H L H BIST on channel 5 H L H H L BIST on channel 6 H L H H H BIST on channel 7 H H L L L BIST on ALL CHANNELS L X X X X NO BIST L H H H H Default - NO BIST 9 www.national.com DS92LV8028 Functional Description DS92LV8028 Functional Block Diagram 20027201 FIGURE 11. DS92LV8028 Functional Block Diagram www.national.com 10 USING THE DS92LV8028 The DS92LV8028 is an easy to use serializer that combines eight 10:1 serializers into a single chip with a maximum payload of 5.28Gbps. Each of the eight serializers accepts 10 or less data bits. The serializers then multiplex the data into a serial data stream with embedded clock bits and route to the LVDS output at up to 660Mbps per channels. The LVDS output is a 5 ma current loop driver that can be used for point-to-point and lightly loaded multidrop applications. Each of the eight channels has their own serializer function but share a single Transmit Clock (TCLK) with a single PLL for the entire chip. The data on all eight channels is latched into the device with the rising edge of TCLK and the data stream is compatible with the DS92LV1210, DS92LV1212A, DS92LV1224, DS92LV1260 deserializers from National Semiconductor. If using less than 10 bits of data, it is recommended to tie off adjacent bits to the embedded clock bits to prevent causing a RMT in the data payload. For example, if only using 8 bits, tie D0 High and D9 Low. Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) swings away from the LVDS lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closelycoupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. Also the tight coupled lines will radiate less. Power Considerations All CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the constant current source nature of the LVDS outputs minimize the slope of the speed vs. ICC curve of CMOS designs. TRANSMISSION MEDIA The DS92LV8028 Serializers can be used in point-to-point configuration of a backplane across PCB traces or through cable interconnect. In point-to-point configurations the transmission media needs only to be terminated at the receiver end. The DS92LV8028 may also be used with double terminations for a total load or 50 Ohms for use in certain limited multidrop applications. Termination impedances lower than 50 Ohms is not recommended. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate highfrequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitic, especially proven effective at high frequencies above approximately 50MHz, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins straight to the power and ground plane, with the bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting a power or ground pin to an external bypass capacitor will increase the inductance of the path. TERMINATION Termination of the LVDS interconnect is required. For pointto-point applications termination should be located at the load end. Nominal value is 100 Ohms to match the line’s differential impedance. Place the resistor as close to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver. Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the national web site at: www.national.com/lvds DS92LV8028 BLVDS SERIALIZER BYPASS RECOMMENDATIONS General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated circuit power supply needs. For a typical application circuit, please see Figure 12. DVDD = DIGITAL SECTION POWER SUPPLY These pins supply the digital portion of the device. A 0.1uF capacitor is sufficient for these pins. 11 www.national.com DS92LV8028 A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. User must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30MHz range. To provide effective bypassing, very often, multiple capacitors are used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two via from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Application Information DS92LV8028 Application Information capacitor is sufficient for these pins. If space is available, a 0.01uF may be used in parallel with the 0.1uF capacitor for additional high frequency filtering. (Continued) PVDD = PLL SECTION POWER SUPPLY The PVDD pin supplies the PLL circuit. The PLL(s) require clean power for the minimization of Jitter. A supply noise frequency in the 300kHZ to 1MHz range can cause increased output jitter. Certain power supplies may have switching frequencies or high harmonic content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter response is best to provide a stable VDD, suppression of the noise band, and good highfrequency response (clock fundamental). This may be accomplished with a pie filter (CRC or CLC). The pie filter should be located close to the PVDD power pin. Separate power planes for the PVDD pins is typically not required. GROUNDs The AGND pin should be connected to the signal common in the cable for the return path of any common-mode current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of current may be even-mode due to coupled noise, and driver imbalances. This current should return via a low impedance known path. A solid ground plane is recommended for DVDD, PVDD and AVDD. Using a split plane may have a potential problem of ground loops, or difference in ground potential at various ground pins of the device. AVDD = LVDS SECTION POWER SUPPLY The AVDD pin supplies the LVDS portion of the circuit. The DS92LV8028 has nine AVDD pins. Due to the nature of the design, current draw is not excessive on these pins. A 0.1uF Application Diagram 20027210 FIGURE 12. Typical Application Circuit www.national.com 12 DS92LV8028 Pin Diagram 20027202 Top View of DS92LV8028 (196-pin LBGA) 13 www.national.com DS92LV8028 Pin Descriptions Pin Number Name Type Description C7, C9, C10, D6, D7, D9, E5, E7, G7 AGND Analog ground. C6, C8, C11, D5, D8, D10, E6, E8, F7 AVDD Analog power supply. B12 BIST_ACT 3.3 V CMOS I BIST Active. Control pin for BIST mode enable.When BIST_ACT = H and BIST_SEL (0:3) = 0H to 8H, device will go to BIST mode accordingly. See Table 1 Default at Low A13, B13, D11, E11 BIST_SEL (0:3) 3.3 V CMOS I BIST select. Control pins for which serializer is set for BIST mode. See Table 1(Note 4) Default at VDD DEN 3.3 V CMOS I Serializer output data enable. Enable data output DOUTn (0:9). n = serializer number. When driven low, puts the Bus LVDS outputs in TRI-STATE. Default at Low. M14 A2, A3, A12, B2, B3, C2, C4, D12, E1, E2, E9, E10, E12, E13, E14, F6, F10, H10, K6, K10, M13, P1 DGND E3, E4, F1, F2, F3, F4, F11, F12, G1, G2, G3, G4, G11, G12, G14, H1, H2, H3, H4, H11, H12, H13, H14, J1, J2, J3, J4, J11, J12, J13, J14, K1, K2, K3, K4, K11, K12, K13, K14, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, M3, M4, M5, M6, M7, M8, M9, M10, M11, N3, N4, N5, N6, N7, N8, N9, N10, N11, P2, P3, P4, P5, P6, P7, P8, P9, P10 P11, P12 DINnx 3.3 V CMOS I B11-A11, B10-A10, B9-A9, B8-A8, B7-A7, A6-B6, A5-B5, A4-B4 Doutn ± Bus LVDS O A1, B1, C3, C5, D4, D13, D14, F5, F8, F9, F13, G6, G10, G13, H7, DVDD N14 MS_PWDN www.national.com Digital Ground. Data input. Inputs for the ten bit serializers. n = serializer number, x = bit number. Default at Low. Bus LVDS differential outputs. n = serializer number. Digital power supply. 3.3 V CMOS I Master Powerdown. MS_PWDN driven low shuts down the PLL and TRI-STATE all outputs, putting the device into a low power ’sleep’ mode. Default at Low. 14 DS92LV8028 Pin Descriptions (Continued) Pin Number Name G5, G8, G9, H5, H6, H8, H9, J5, J6, J7, J9, J10 NC (1:12) No connect. C1, D1 PGND PLL ground. D2, D3 PVDD N1, N2, N13, M1, M2, M12, PWDN (0:7) P13, P14 J8, K5, K7, K8, K9, L1, L2, SYNC (0:7) N12 Type Description PLL power supply. 3.3 V CMOS I Individual Powerdown. PWDN (0:7) driven low puts individual serializer into TRI-STATE, low power ’sleep’ mode. Default at Low. 3.3 V CMOS I SYNC pattern enable. When driven high for a mininum of 4 cycles, SYNC patterns will be transmitted on the Bus LVDS serial output. The SYNC pattern sent by the serializer consists of six ones and six zeros switching at the input clock rate. SYNC pattern continues to be sent if SYNC continues at high. Default at Low. See Functional Description. C13 TCK JTAG pin. Reserved for future use. Leave this pin floating. B14 TDI JTAG pin. Reserved for future use. Leave this pin floating. C14 TDO JTAG pin. Reserved for future use. Leave this pin floating. A14 TMS JTAG pin. Reserved for future use. Leave this pin floating. C12 TRSTN F14 TCLK JTAG pin. Reserved for future use. Leave this pin floating. 3.3 V CMOS I Transmit Clock. Input for 25MHz - 66 MHz (nominal) system clock. 15 www.national.com DS92LV80288 Channel 10:1 Serializer Physical Dimensions inches (millimeters) unless otherwise noted Dimensions show in millimeters Order Number DS92LV8028TUF NS Package Number UJB196A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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