NSC SCAN921025SLC

SCAN921025 and SCAN921226
30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
General Description
The SCAN921025 transforms a 10-bit wide parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921226 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for
Boundary Scan Test. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port
(TAP) to the backplane or cable interconnects and the ability
to verify differential signal integrity. The pair of devices also
features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified
at-speed.
The SCAN921025 transmits data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits clock and data bits serially, it eliminates clock-todata and data-to-data skew. The powerdown pin saves
power by reducing supply current when not using either
device. Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the Deserializer to
use the synchronization-to-random-data feature. By using
the synchronization mode, the Deserializer will establish lock
to a signal within specified lock times. In addition, the embedded clock guarantees a transition on the bus every 12-bit
cycle. This eliminates transmission errors due to charged
cable conditions. Furthermore, you may put the
SCAN921025 output pins into TRI-STATE to achieve a high
impedance state. The PLL can lock to frequencies between
30 MHz and 80 MHz.
Features
n IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption < 600 mW (typ)
@ 80 MHz
n Single differential pair eliminates multi-channel skew
n 800 Mbps serial Bus LVDS data rate (at 80 MHz clock)
n 10-bit parallel interface for 1 byte data plus 2 control bits
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Bus LVDS serial output rated for 27Ω load
n Small 49-lead BGA package
Block Diagrams
DS200248-1
© 2001 National Semiconductor Corporation
DS200248
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SCAN921025/SCAN921226 30-80 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1
(JTAG) and at-speed BIST
December 2001
SCAN921025/SCAN921226
Block Diagrams
(Continued)
Application
DS200248-2
The user’s application determines control of the SYNC1 and
SYNC 2 pins. One recommendation is a direct feedback loop
from the LOCK pin. Under all circumstances, the Serializer
stops sending SYNC patterns after both SYNC inputs return
low.
When the Deserializer detects edge transitions at the Bus
LVDS input, it will attempt to lock to the embedded clock
information. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low, the
Deserializer outputs represent incoming Bus LVDS data.
Functional Description
The SCAN921025 and SCAN921226 are a 10-bit Serializer
and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from 30 to 80 MHz. The
chipset is also capable of driving data over Unshielded
Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE. In addition to the active
and passive states, there are also test modes for JTAG
access and at-speed BIST.
The following sections describe each operation and passive
state and the test modes.
Data Transfer
After initialization, the Serializer will accept data from inputs
DIN0–DIN9. The Serializer uses the TCLK input to latch
incoming Data. The TCLK_R/F pin selects which edge the
Serializer uses to strobe incoming data. TCLK_R/F high
selects the rising edge for clocking data and low selects the
falling edge. If either of the SYNC inputs is high for 5*TCLK
cycles, the data at DIN0-DIN9 is ignored regardless of clock
edge.
After determining which clock edge to use, a start and stop
bit, appended internally, frame the data bits in the register.
The start bit is always high and the stop bit is always low.
The start and stop bits function as the embedded clock bits
in the serial stream.
The Serializer transmits serialized data and clock bits (10+2
bits) from the serial data output (DO ± ) at 12 times the TCLK
frequency. For example, if TCLK is 80 MHz, the serial rate is
80 x 12 = 960 Mega-bits-per-second. Since only 10 bits are
from input data, the serial “payload” rate is 10 times the
TCLK frequency. For instance, if TCLK = 80 MHz, the payload data rate is 80 x 10 = 800 Mbps. The data source
provides TCLK and must be in the range of 30 MHz to 80
MHz nominal.
The Serializer outputs (DO ± ) can drive a point-to-point connection or in limited multi-point or multi-drop backplanes.
The outputs transmit data when the enable pin (DEN) is
high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the Serializer output pins will enter
TRI-STATE.
When the Deserializer synchronizes to the Serializer, the
LOCK pin is low. The Deserializer locks to the embedded
Initialization
Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of the
Serializer and Deserializer PLL’s to local clocks, which may
be the same or separate. Afterwards, synchronization of the
Deserializer to Serializer occurs.
Step 1: When you apply VCC to both Serializer and/or Deserializer, the respective outputs enter TRI-STATE, and on-chip
power-on circuitry disables internal circuitry. When VCC
reaches VCCOK (2.5V) the PLL in each device begins locking to a local clock. For the Serializer, the local clock is the
transmit clock (TCLK) provided by the source ASIC or other
device. For the Deserializer, you must apply a local clock to
the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer is
now ready to send data or SYNC patterns, depending on the
levels of the SYNC1 and SYNC2 inputs or a data stream.
The SYNC pattern sent by the Serializer consists of six ones
and six zeros switching at the input clock rate.
Note that the Deserializer LOCK output will remain high
while its PLL locks to the incoming data or to SYNC patterns
on the input.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will lock to
non-repetitive data patterns. However, the transmission of
SYNC patterns enables the Deserializer to lock to the Serializer signal within a specified time. See Figure 9.
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2
the serial data stream. Graphical representations of RMT are
shown in Figure 1. Please note that RMT only applies to bits
DIN0-DIN8.
(Continued)
clock and uses it to recover the serialized data. ROUT data
is valid when LOCK is low. Otherwise ROUT0–ROUT9 is
invalid.
Powerdown
The ROUT0-ROUT9 pins use the RCLK pin as the reference
to data. The polarity of the RCLK edge is controlled by the
RCLK_R/F input. See Figure 13.
When no data transfer occurs, you can use the Powerdown
state. The Serializer and Deserializer use the Powerdown
state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown when you drive
PWRDN and REN low. The Serializer enters Powerdown
when you drive PWRDN low. In Powerdown, the PLL stops
and the outputs enter TRI-STATE, which disables load current and reduces supply current to the milliampere range. To
exit Powerdown, you must drive the PWRDN pin high.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum
of three CMOS input gates (15 pF load) with a 80 MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock
edge, the Deserializer LOCK pin asserts a low. If the Deserializer loses lock, the LOCK pin output will go high and the
outputs (including RCLK) will enter TRI-STATE.
The user’s system monitors the LOCK pin to detect a loss of
synchronization. Upon detection, the system can arrange to
pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.
Multiple resynchronization approaches are possible. One
recommendation is to provide a feedback loop using the
LOCK pin itself to control the sync request of the Serializer
(SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop application. Sending sync patterns for resynchronization is desirable when lock times
within a specific time are critical. However, the Deserializer
can lock to random data, which is discussed in the next
section.
Before valid data exchanges between the Serializer and
Deserializer, you must reinitialize and resynchronize the devices to each other. Initialization of the Serializer takes 510
TCLK cycles. The Deserializer will initialize and assert LOCK
high until lock to the Bus LVDS clock occurs.
TRI-STATE
The Serializer enters TRI-STATE when the DEN pin is driven
low. This puts both driver output pins (DO+ and DO−) into
TRI-STATE. When you drive DEN high, the Serializer returns
to the previous state, as long as all other control pins remain
static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters
TRI-STATE. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The
LOCK output remains active, reflecting the state of the PLL.
Random Lock Initialization and
Resynchronization
TABLE 1.
The initialization and resynchronization methods described
in their respective sections are the fastest ways to establish
the link between the Serializer and Deserializer. However,
the SCAN921226 can attain lock to a data stream without
requiring the Serializer to send special SYNC patterns. This
allows the SCAN921226 to operate in “open-loop” applications. Equally important is the Deserializer’s ability to support
hot insertion into a running backplane. In the open loop or
hot insertion case, we assume the data stream is essentially
random. Therefore, because lock time varies due to data
stream characteristics, we cannot possibly predict exact lock
time. However, please see Table 1 for some general random
lock times under specific conditions. The primary constraint
on the “random” lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up. As described in the next paragraph, the
data contained in the data stream can also affect lock time.
If a specific pattern is repetitive, the Deserializer could enter
“false lock” - falsely recognizing the data pattern as the
clocking bits. We refer to such a pattern as a repetitive
multi-transition, RMT. This occurs when more than one
Low-High transition takes place in a clock cycle over multiple
cycles. This occurs when any bit, except DIN 9, is held at a
low state and the adjacent bit is held high, creating a 0-1
transition. In the worst case, the Deserializer could become
locked to the data pattern rather than the clock. Circuitry
within the SCAN921226 can detect that the possibility of
“false lock” exists. The circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon
detection, the circuitry will prevent the LOCK output from
becoming active until the potential “false lock” pattern
changes. The false lock detect circuitry expects the data will
eventually change, causing the Deserializer to lose lock to
the data pattern and then continue searching for clock bits in
Random Lock Times for the SCAN921226
80 MHz
Units
Maximum
18
µs
Mean
3.0
µs
Minimum
0.43
µs
Conditions:
15
PRBS 2 , VCC = 3.3V
1) Difference in lock times are due to different starting points in the data
pattern with multiple parts.
Test Modes
In addition to the IEEE 1149.1 test access to the digital TTL
pins, the SCAN921025 and SCAN921226 have two instructions to test the LVDS interconnects. The first is EXTEST.
This is implemented at LVDS levels and is only intended as
a go no-go test (e.g. missing cables). The second method is
the RUNBIST instruction. It is an ’at-system-speed’ interconnect test. It is executed in approximately 33mS with a system
clock speed of 66MHz. There are two bits in the RX BIST
data register for notification of PASS/FAIL and TEST_COMPLETE. Pass indicates that the BER (Bit-Error-Rate) is better than 10-7.
An important detail is that once both devices have the RUNBIST instruction loaded into their respective instruction registers, both devices must move into the RTI state within 4K
system clocks (At a SCLK of 66Mhz and TCK of 1MHz this
allows for 66 TCK cycles). This is not a concern when both
devices are on the same scan chain or LSP, however, it can
be a problem with some multi-drop devices. This test mode
has been simulated and verified using National’s SCANSTA111.
3
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SCAN921025/SCAN921226
Data Transfer
SCAN921025/SCAN921226
Ordering Information
NSID
Function
Package
SCAN921025SLC
Serializer
SLC49a
SCAN921226SLC
Deserializer
SLC49a
DS200248-24
DIN0 Held Low-DIN1 Held High Creates an RMT Pattern
DS200248-25
DIN4 Held Low-DIN5 Held High Creates an RMT Pattern
DS200248-26
DIN8 Held Low-DIN9 Held High Creates an RMT Pattern
FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output
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4
11.8 mW/˚C above
+25˚C
85˚C/W
49L BGA
θja
ESD Rating
HBM
MM
Supply Voltage (VCC)
−0.3V to +4V
LVCMOS/LVTTL Input
Voltage
−0.3V to (VCC +0.3V)
LVCMOS/LVTTL Output
Voltage
−0.3V to (VCC +0.3V)
Bus LVDS Receiver Input
Voltage
−0.3V to +3.9V
Bus LVDS Driver Output
Voltage
−0.3V to +3.9V
Bus LVDS Output Short
Circuit Duration
10mS
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 seconds)
+220˚C
Maximum Package Power Dissipation Capacity
@ 25˚C Package:
49L BGA
1.47 W
Package Derating:
> 2kV
> 250V
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (VCC)
3.0
3.3
3.6
V
Operating Free Air
Temperature (TA)
−40
+25
+85
˚C
2.4
V
Receiver Input Range
0
Supply Noise Voltage
(VCC)
100 mVP-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to DIN0-9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, DEN)
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
ICL = −18 mA
-0.86
−1.5
V
IIN
Input Current
VIN = 0V or 3.6V
±1
+10
µA
−10
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply to
pins ROUT, RCLK, LOCK = outputs)
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
ICL = −18 mA
−0.62
−1.5
V
IIN
Input Current
VIN = 0V or 3.6V
−10
±1
+15
µA
VOH
High Level Output Voltage
IOH = −9 mA
2.2
3.0
VCC
V
VOL
Low Level Output Voltage
IOL = 9 mA
GND
0.25
0.5
V
IOS
Output Short Circuit Current
VOUT = 0V
−15
−47
−85
mA
IOS
Output Short Circuit Current,
TDO output
-15
-70
-100
mA
IOZ
TRI-STATE Output Current
−10
± 0.1
+10
µA
200
290
PWRDN or REN = 0.8V, VOUT = 0V or VCC
SERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins DO+ and DO−)
VOD
Output Differential Voltage
(DO+)–(DO−)
∆VOD
Output Differential Voltage
Unbalance
RL = 27Ω, Figure 17
mV
35
VOS
Offset Voltage
∆VOS
Offset Voltage Unbalance
IOS
Output Short Circuit Current
D0 = 0V, DIN = High,PWRDN and DEN = 2.4V
IOZ
TRI-STATE Output Current
PWRDN or DEN = 0.8V, DO = 0V or VCC
−10
IOX
Power-Off Output Current
VCC = 0V, DO=0V or 3.6V
−20
1.05
5
mV
1.1
1.3
V
4.8
35
mV
−56
−90
mA
±1
±1
+10
µA
+25
µA
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SCAN921025/SCAN921226
Absolute Maximum Ratings (Note 1)
SCAN921025/SCAN921226
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
+6
+50
mV
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
Differential Threshold High
Voltage
VTL
Differential Threshold Low
Voltage
IIN
Input Current
VCM = +1.1V
−50
−12
mV
VIN = +2.4V, VCC = 3.6V or 0V
−10
±1
+10
µA
VIN = 0V, VCC = 3.6V or 0V
−10
± 0.05
+10
µA
SERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCD
ICCXD
Serializer Supply Current
RL = 27Ω
f = 30 MHz
45
60
mA
Worst Case
Figure 2
f = 80 MHz
90
105
mA
Serializer Supply Current
Powerdown
PWRDN = 0.8V, f = 80MHz
0.2
1.0
mA
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCR
Deserializer Supply Current
ICCXR
CL = 15 pF
f = 30 MHz
50
75
mA
Worst Case
Figure 3
f = 80 MHz
100
120
mA
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
0.36
1.0
mA
SCAN CIRCUITRY DC SPECIFICATIONS, SERIALIZER AND DESERIALIZER (applies to SCAN pins as noted)
VIH
High Level Input Voltage
VCC = 3.0 to 3.6V, pins TCK, TMS, TDI, and TRST
2.0
VCC
V
GND
0.8
V
−0.85
−1.5
V
1
+10
µA
VIL
Low Level Input Voltage
VCC = 3.0 to 3.6V, pins TCK, TMS, TDI, and TRST
VCL
Input Clamp Voltage
VCC = 3.0V, ICL = −18 mA, pins TCK, TMS, TDI,
and TRST
IIH
Input Current
VCC = 3.6V, VIN = 3.6V, pins TCK, TMS, TDI, and
TRST
IIL
Input Current
VCC = 3.6V, VIN = 0.0V, TCK Input
-10
-1
µA
IILR
Input Current
VCC = 3.6V, VIN = 0V, pins TMS, TDI, and TRST
-20
-10
µA
2.2
2.6
VOH
High Level Output Voltage
VCC = 3.0V, IOH = −12 mA, TDO output
VOL
Low Level Output Voltage
VCC = 3.0V, IOL = 12 mA, TDO output
IOS
Output Short Circuit Current
VCC = 3.6V, VOUT = 0.0V, TDO output
IOZ
TRI-STATE Output Current
PWRDN or REN = 0.8V, VOUT = 0V or VCC
V
0.3
0.5
V
-15
-90
-120
mA
−10
0
+10
µA
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tTCP
Transmit Clock Period
12.5
T
33.3
ns
tTCIH
Transmit Clock High Time
0.4T
0.5T
0.6T
ns
tTCIL
Transmit Clock Low Time
0.4T
0.5T
0.6T
ns
tCLKT
TCLK Input Transition Time
3
6
ns
tJIT
TCLK Input Jitter
150
ps (RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tLLHT
Bus LVDS Low-to-High
Transition Time
tLHLT
Bus LVDS High-to-Low
Transition Time
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Conditions
RL = 27Ω
CL=10pF to GND
Figure 4
(Note 4)
6
Min
Typ
Max
Units
0.2
0.4
ns
0.25
0.4
ns
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tDIS
DIN (0-9) Setup to TCLK
tDIH
DIN (0-9) Hold from
TCLK
tHZD
DO ± HIGH to
TRI-STATE Delay
tLZD
DO ± LOW to
TRI-STATE Delay
tZHD
Min
RL = 27Ω,
CL=10pF to GND
Figure 7
Typ
Max
Units
0
ns
4.0
ns
RL = 27Ω,
CL=10pF to GND
Figure 8
(Note 5)
3
10
ns
3
10
ns
DO ± TRI-STATE to
HIGH Delay
5
10
ns
tZLD
DO ± TRI-STATE to
LOW Delay
6.5
10
ns
tSPW
SYNC Pulse Width
tPLD
Serializer PLL Lock Time
RL = 27Ω
Figure 10
tSD
Serializer Delay
RL = 27Ω, Figure 11
tDJIT
Deterministic Jitter
tRJIT
Random Jitter
RL =
27Ω,
CL=10pF
to GND,
(Note 6)
5*tTCP
ns
510*tTCP
513*tTCP
ns
tTCP+
1.0
tTCP+
2.5
tTCP+
3.5
ns
-130
-40
+60
ps
6
10
ps
(RMS)
Typ
Max
Units
80 MHz
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
tRFCP
REFCLK Period
12.5
T
33.3
ns
tRFDC
REFCLK Duty Cycle
30
50
70
%
tRFCP / tTCP
Ratio of REFCLK to TCLK
95
1
105
tRFTT
REFCLK Transition Time
3
6
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
tRCP
Receiver out Clock
Period
tRCP = tTCP
Figure 11
tCLH
CMOS/TTL Low-to-High
Transition Time
CL = 15 pF
Figure 5
tCHL
CMOS/TTL High-to-Low
Transition Time
tDD
Deserializer Delay
Figure 12
tROS
tRDC
RCLK Duty Cycle
RCLK
RCLK
12.5
Rout(0-9),
LOCK,
RCLK
Typ
Max
Units
33.3
ns
1.2
4
ns
1.1
4
ns
1.75*tRCP+1.25 1.75*tRCP+5.0 1.75*tRCP+8.5
ns
Room Temp./3.3V/30MHz
1.75*tRCP+2.25 1.75*tRCP+5.0 1.75*tRCP+8.0
ns
Room Temp./3.3V/80MHz
1.75*tRCP+2.25 1.75*tRCP+5.0 1.75*tRCP+8.0
ns
RCLK
ROUT Data valid after
Min
All Temp./ All Freq.
ROUT Data Valid before Figure 13
tROH
Pin/Freq.
Figure 13
RCLK
30MHz
0.4*tRCP
0.5*tRCP
ns
RCLK
80MHz
0.35*tRCP
0.5*tRCP
ns
30MHz
−0.4*tRCP
−0.5*tRCP
ns
80MHz
−0.35*tRCP
−0.5*tRCP
45
50
7
ns
55
%
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SCAN921025/SCAN921226
Serializer Switching Characteristics
SCAN921025/SCAN921226
Deserializer Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Typ
Max
Units
2.8
10
ns
LOW to TRI-STATE
Delay
2.8
10
ns
tZHR
TRI-STATE to HIGH
Delay
4.2
10
ns
tZLR
TRI-STATE to LOW
Delay
4.2
10
ns
tDSR1
Deserializer PLL Lock
Time from PWRDWN
(with SYNCPAT)
30MHz
1.7
3.5
µs
80MHz
1.0
2.5
µs
30MHz
0.65
1.5
µs
80MHz
0.29
0.8
µs
LOCK
3.7
12
ns
+350
ps
tHZR
HIGH to TRI-STATE
Delay
tLZR
Figure 14
Pin/Freq.
Figure 15
Figure 16
(Note 7)
tDSR2
Deserializer PLL Lock
time from SYNCPAT
tZHLK
TRI-STATE to HIGH
Delay (power-up)
tRNMI-R
Ideal Noise Margin
Right
Figure 20
tRNMI-L
Ideal Noise Margin Left
Figure 20
Min
Rout(0-9)
80 MHz
80 MHz
-385
ps
SCAN Circuitry Timing Requirements
Symbol
Parameter
fMAX
Maximum TCK Clock
Frequency
Conditions
Min
Typ
RL = 500Ω, CL = 35 pF
25.0
50.0
Max
Units
MHz
tS
TDI to TCK, H or L
1.0
ns
tH
TDI to TCK, H or L
2.0
ns
tS
TMS to TCK, H or L
2.5
ns
tH
TMS to TCK, H or L
1.5
ns
tW
TCK Pulse Width, H or L
10.0
ns
tW
TRST Pulse Width, L
2.5
ns
tREC
Recovery Time, TRST to TCK
2.0
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: tLLHT and tLHLT specifications are Guaranteed By Design (GBD) using statistical analysis.
Note 5: Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 6: tDJIT specifications are Guaranteed By Design using statistical analysis.
Note 7: For the purpose of specifying deserializer PLL performance, tDSR1 and tDSR2 are specified with the REFCLK running and stable, and with specific
conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the
time required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from
not receiving data to receiving synchronization patterns (SYNCPATs).
Note 8: tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise
Margin is Guaranteed By Design (GBD) using statistical analysis.
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8
SCAN921025/SCAN921226
AC Timing Diagrams and Test Circuits
DS200248-3
FIGURE 2. “Worst Case” Serializer ICC Test Pattern
DS200248-4
FIGURE 3. “Worst Case” Deserializer ICC Test Pattern
DS200248-5
FIGURE 4. Serializer Bus LVDS Output Load and Transition Times
DS200248-6
FIGURE 5. Deserializer CMOS/TTL Output Load and Transition Times
DS200248-7
FIGURE 6. Serializer Input Clock Transition Time
9
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SCAN921025/SCAN921226
AC Timing Diagrams and Test Circuits
(Continued)
DS200248-8
Timing shown for TCLK_R/F = LOW
FIGURE 7. Serializer Setup/Hold Times
DS200248-9
FIGURE 8. Serializer TRI-STATE Test Circuit and Timing
DS200248-10
FIGURE 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays
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10
SCAN921025/SCAN921226
AC Timing Diagrams and Test Circuits
(Continued)
DS200248-23
FIGURE 10. SYNC Timing Delays
DS200248-11
FIGURE 11. Serializer Delay
DS200248-12
FIGURE 12. Deserializer Delay
11
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SCAN921025/SCAN921226
AC Timing Diagrams and Test Circuits
(Continued)
DS200248-13
Timing shown for RCLK_R/F = LOW
Duty Cycle (tRDC) =
FIGURE 13. Deserializer Data Valid Out Times
DS200248-14
FIGURE 14. Deserializer TRI-STATE Test Circuit and Timing
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12
SCAN921025/SCAN921226
AC Timing Diagrams and Test Circuits
(Continued)
DS200248-15
FIGURE 15. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
DS200248-22
FIGURE 16. Deserializer PLL Lock Time from SyncPAT
13
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SCAN921025/SCAN921226
AC Timing Diagrams and Test Circuits
(Continued)
DS200248-16
VOD = (DO+)–(DO−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
FIGURE 17. VOD Diagram
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14
Using the SCAN921025 and SCAN921226
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
LVTTL data over a serial Bus LVDS link up to 800 Mbps. An
on-board PLL serializes the input data and embeds two clock
bits within the data stream. The Deserializer uses a separate
reference clock (REFCLK) and an onboard PLL to extract
the clock information from the incoming data stream and
then deserialize the data. The Deserializer monitors the
incoming clock information, determines lock status, and asserts the LOCK output high when loss of lock occurs.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by random locking, which can take more time,
depending on the data patterns being received.
Hot Insertion
All the BLVDS devices are hot pluggable if you follow a few
rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When
removing, the I/O pins should be unplugged first, then the
VCC, then the Ground. Random lock hot insertion is illustrated in Figure 21.
PCB Considerations
The Bus LVDS Serializer and Deserializer should be placed
as close to the edge connector as possible. In multiple
Deserializer applications, the distance from the Deserializer
to the slot connector appears as a stub to the Serializer
driving the backplane traces. Longer stubs lower the impedance of the bus, increase the load on the Serializer, and
lower the threshold margin at the Deserializers. Deserializer
devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the
Serializer Bus LVDS outputs, reducing stub lengths as much
as possible is the best method to ensure signal integrity.
Transmission Media
The Serializer and Deserializer can also be used in
point-to-point configuration of a backplane, through a PCB
trace, or through twisted pair cable. In point-to-point configuration, the transmission media need only be terminated at
the receiver end. Please note that in point-to-point configuration, the potential of offsetting the ground levels of the
Serializer vs. the Deserializer must be considered. Also, Bus
LVDS provides a +/− 1.2V common mode range at the
receiver inputs.
Failsafe Biasing for the SCAN921226
The SCAN921226 has an improved input threshold sensitivity of +/− 50mV versus +/− 100mV for the DS92LV1210 or
DS92LV1212. This allows for greater differential noise margin in the SCAN921226. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the SCAN921226 can pickup noise as a signal and
cause unintentional locking. For example, this can occur
when the input cable is disconnected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. the pull-up and pull-down
resistors (R1 and R2) provide a current path through the
termination resistor (RL) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 18 for the Failsafe
Biasing Setup.
Using tDJIT and tRNM to Validate Signal Quality
Power Considerations
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. In addition, the constant
current source nature of the Bus LVDS outputs minimizes
the slope of the speed vs. ICC curve of conventional CMOS
designs.
Powering Up the Deserializer
The SCAN921226 can be powered up at any time by following the proper sequence. The REFCLK input can be running
before the Deserializer powers up, and it must be running in
order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its inputs and locks to
the incoming data stream.
Transmitting Data
Once you power up the Serializer and Deserializer, they
must be phase locked to each other to transmit data. Phase
locking occurs when the Deserializer locks to incoming data
or when the Serializer sends patterns. The Serializer sends
SYNC patterns whenever the SYNC1 or SYNC2 inputs are
high. The LOCK output of the Deserializer remains high until
it has locked to the incoming data stream. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid, except for the specific
case of loss of lock during transmission which is further
discussed in the ’Recovering from LOCK Loss’ section below.
Noise Margin
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, VCC noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
Recovering from LOCK Loss
In the case where the Deserializer loses lock during data
transmission, up to 3 cycles of data that were previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 4 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. There-
The parameter tRNM is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling. After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called tRNM. tRNM includes transmitter jitter.
Please refer to Figure 19 and Figure 20 for a graphic representation of tDJIT and tRNM. Also, for a more detailed expla15
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SCAN921025/SCAN921226
fore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCK pin goes low, at least
three previous data cycles should be suspect for bit errors.
Application Information
SCAN921025/SCAN921226
Application Information
The vertical limits of the mask are determined by the
SCAN921226 receiver input threshold of +/− 50mV.
(Continued)
nation of tRNM, please see the Application Note titled ’How to
Validate BLVDS SER/DES Signal Integrity Using an Eye
Mask’.
DS200248-27
FIGURE 18. Failsafe Biasing Setup
DS200248-29
FIGURE 19. Deterministic Jitter and Ideal Bit Position
DS200248-28
tRNMI-L is the ideal noise margin on the left of the figure, it is a negative value to indicate early with respect to ideal.
tRNMI-R is the ideal noise margin on the right of the above figure, it is a positive value to indicate late with respect to ideal.
FIGURE 20. Ideal Deserializer Noise Margin (tRNMI) and Sampling Window
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16
SCAN921025/SCAN921226
Application Information
(Continued)
DS200248-17
FIGURE 21. Random Lock Hot Insertion
17
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SCAN921025/SCAN921226
Pin Diagrams
SCAN921025SLC - Serializer
(Top View)
DS200248-30
SCAN921226SLC - Deserializer
(Top View)
DS200248-31
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18
I/O
Ball Id.
DIN
Pin Name
I
A3, B1, C1,
D1, D2, D3,
E1, E2, F2,
F4
Data Input. LVTTL levels inputs. Data on these pins are loaded
into a 10-bit input register.
Description
TCLKR/F
I
G3
Transmit Clock Rising/Falling strobe select. LVTTL level input.
Selects TCLK active edge for strobing of DIN data. High selects
rising edge. Low selects falling edge.
DO+
O
D7
+ Serial Data Output. Non-inverting Bus LVDS differential output.
DO−
O
D5
− Serial Data Output. Inverting Bus LVDS differential output.
DEN
I
D6
Serial Data Output Enable. LVTTL level input. A low puts the Bus
LVDS outputs in TRI-STATE.
PWRDN
I
C7
Powerdown. LVTTL level input. PWRDN driven low shuts down
the PLL and TRI-STATEs outputs putting the device into a low
power sleep mode.
TCLK
I
E4
Transmit Clock. LVTTL level input. Input for 30MHz – 80MHz
system clock.
SYNC
I
A4, B3
Assertion of SYNC (high) for at least 1024 synchronization
symbols to be transmitted on the Bus LVDS serial output.
Synchronization symbols continue to be sent if SYNC continues to
be asserted. TTL level input. The two SYNC pins are ORed.
DVCC
I
C3, C4, E5
Digital Circuit power supply.
DGND
I
A1, C2, F5,
E6, G4
Digital Circuit ground.
AVCC
I
A5, A6, B4,
B7, G5
Analog power supply (PLL and Analog Circuits).
AGND
I
B5, B6, C6,
E7, F7
Analog ground (PLL and Analog Circuits).
TDI
I
F1
Test Data Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
TDO
O
G1
Test Data Output to support IEEE 1149.1
TMS
I
E3
Test Mode Select Input to support IEEE 1149.1. There is an
internal pullup resistor that defaults this input to high per IEEE
1149.1.
TCK
I
F3
Test Clock Input to support IEEE 1149.1
TRST
I
G2
Test Reset Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
N/A
A2, A7, B2,
C5, D4, F6,
G6, G7
N/C
Leave open circuit, do not connect
19
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SCAN921025/SCAN921226
Serializer Pin Description
SCAN921025/SCAN921226
Deserializer Pin Description
I/O
Ball Id.
ROUT
Pin Name
O
A5, B4, B6,
C4, C7, D6,
F5, F7, G4,
G5
Description
RCLKR/F
I
B3
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High
selects rising edge. Low selects falling edge.
RI+
I
D2
+ Serial Data Input. Non-inverting Bus LVDS differential input.
RI−
I
C1
− Serial Data Input. Inverting Bus LVDS differential input.
PWRDN
I
D3
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs outputs putting the device into a low power
sleep mode.
LOCK
O
E1
LOCK goes low when the Deserializer PLL locks onto the
embedded clock edge. CMOS level output. Totem pole output
structure, does not directly support wired OR connections.
RCLK
O
E2
Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT, CMOS level output.
REN
I
D1
Output Enable. TTL level input. When driven low, TRI-STATEs
ROUT0–ROUT9 and RCLK.
DVCC
I
A7, B7, C5,
C6, D5
Digital Circuit power supply.
DGND
I
A1, A6, B5,
D7, E4, E7,
G3
Digital Circuit ground.
AVCC
I
B1, C2, F1,
F2, G1
Analog power supply (PLL and Analog Circuits).
AGND
I
A4, B2, F3,
F4, G2
Analog ground (PLL and Analog Circuits).
REFCLK
I
A3
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
TDI
I
F6
Test Data Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
TDO
O
G6
Test Data Output to support IEEE 1149.1
TMS
I
G7
Test Mode Select Input to support IEEE 1149.1. There is an
internal pullup resistor that defaults this input to high per IEEE
1149.1.
Data Output. ± 9 mA CMOS level outputs.
TCK
I
E5
Test Clock Input to support IEEE 1149.1
TRST
I
E6
Test Reset Input to support IEEE 1149.1. There is an internal
pullup resistor that defaults this input to high per IEEE 1149.1.
N/A
A2, C3, D4,
E3
N/C
Leave open circuit, do not connect
Deserializer Truth Table
INPUTS
PWRDN
1)
2)
3)
4)
OUTPUTS
REN
ROUT [0:9]
LOCK
RCLK
H (4)
H
Z
H
Z
H
H
Active
L
Active
L
X
Z
Z
Z
H
L
Z
Active
Z
LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
ROUT and RCLK are TRI-STATED when LOCK is asserted High.
During Power-up.
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20
inches (millimeters) unless otherwise noted
Order Number SCAN921025SLC or SCAN921226SLC
NS Package Number SLC49A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
SCAN921025/SCAN921226 30-80 MHz 10 Bit BLVDS Serializer and Deserializer with IEEE 1149.1
(JTAG) and at-speed BIST
Physical Dimensions