PHILIPS SAA7187

INTEGRATED CIRCUITS
DATA SHEET
SAA7187
Digital video encoder (DENC2-SQ)
Preliminary specification
File under Integrated Circuits, IC22
1995 Sep 21
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
FEATURES
• CMOS 5 V device
• Digital PAL/NTSC encoder
• System pixel frequency selectable for 12.27 MHz (60 Hz
fields) or 14.75 MHz (50 Hz fields)
• 24-bit wide YUV input port or
• Down-mode of DACs
• 16-bit wide YUV input port or
• CVBS and S-Video output simultaneously
• Input data format Cb, Y, Cr, etc. (CCIR 656)
• PLCC68 package.
• I2C-bus control port
• MPU parallel control port
• Encoder can be master or slave
GENERAL DESCRIPTION
• Programmable horizontal and vertical input
synchronization phase
The SAA7187 encodes digital YUV video data to an
NTSC, PAL CVBS or S-Video signal.
• Programmable horizontal sync output phase
The circuit accepts differently formatted YUV data with 640
or 768 active pixels per line. It includes a sync/clock
generator and on-chip Digital-to-Analog Converters
(DACs).
• OSD overlay with Look-Up Tables (LUTs) 8 × 3 bytes
• Line 21 Closed Caption encoder
• Cross-colour reduction
The circuit is compatible to the DIG-TV2 chip family
(Square Pixel).
• DACs operating at twice oversampling with 10-bit
resolution
• Controlled rise/fall times of output syncs and blanking
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
5.0
MAX.
5.25
UNIT
VDDA
analog supply voltage
4.75
V
VDDD
digital supply voltage
4.5
5.0
5.5
V
IDDA
analog supply current
−
50
55
mA
IDDD
digital supply current
−
175
210
mA
Vi
input signal voltage levels
Vo(p-p)
analog output signal voltages Y, C and CVBS without load −
(peak-to-peak value)
2
−
V
RL
load resistance
80
−
−
Ω
ILE
LF integral linearity error
−
−
±2
LSB
DLE
LF differential linearity error
−
−
±1
LSB
Tamb
operating ambient temperature
0
−
+70
°C
TTL compatible
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
SAA7187
1995 Sep 21
PLCC68
DESCRIPTION
plastic leaded chip carrier; 68 leads
2
VERSION
SOT188-2
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
BLOCK DIAGRAM
KEY
OSD0
to OSD2
VP1
(7 to 0)
VP2
(0 to 7)
VDDD1
to VDDD4
RTCI
32 to 34
31
VDDA1
to
VrefH VDDA4
II
47 55 48,50,
54,56
53
A
51
17,37,42,67
43
20 to 27
8
DATA
MANAGER
9 to 16
8
OUTPUT
INTERFACE
ENCODER
8
8
D
49
8
internal control bus
RCM1
RCM2
8
clock timing signals
VSSA
46
VrefL
8
1,8,19
28,35,
62
63 to 66
2 to 5
CONTROL
INTERFACE
68
61
59
60
SAA7187
8
SYNC
CLK
58
57
41
RESET
XTALI
40
38
39
36
6
7
18
MBG253
VP3
(0 to 7)
CS/SA
SEL_MPU
A0/SDA
RW/SCL
DTACK
XTALO
handbook, full pagewidth
VSSD1
to
VSSD6
Fig.1 Block diagram.
1995 Sep 21
3
LLC
CDIR
CREF
RCV2
RCV1
n.c.
Y
CHROMA
52
29
30
CVBS
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
PINNING
SYMBOL
PIN
DESCRIPTION
VSSD1
1
VP3(4)
2
digital ground 1
VP3(5)
3
VP3(6)
4
VP3(7)
5
RCV1
6
Raster Control 1 for Video port. Depending on the synchronization mode, this pin
receives/provides a VS/FS/FSEQ signal.
RCV2
7
Raster Control 2 for Video port. Depending on the synchronization mode, this pin
receives/provides an HS/HREF/CBL signal.
VSSD2
8
digital ground 2
VP2(0)
9
VP2(1)
10
Upper 4 bits of the Video Port VP3. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the
parallel MPU interface. If it is LOW, there can be multiplexed UV lines (422) or the U signal
(444) of the Video input.
VP2(2)
11
VP2(3)
12
VP2(4)
13
VP2(5)
14
VP2(6)
15
VP2(7)
16
VDDD1
17
digital supply voltage 1
n.c.
18
reserved, do not connect
VSSD3
19
digital ground 3
VP1(7)
20
VP1(6)
21
VP1(5)
22
VP1(4)
23
VP1(3)
24
VP1(2)
25
VP1(1)
26
VP1(0)
27
VSSD4
28
digital ground 4
RCM1
29
Raster Control Master 1. This pin provides a VS/FS/FSEQ signal.
RCM2
30
Raster Control Master 2. This pin provides a programmable HS pulse.
KEY
31
Key signal for OSD. It is active HIGH.
OSD0
32
OSD1
33
OSD2
34
VSSD5
35
digital ground 5
CDIR
36
Clock direction. If the CDIR input is HIGH, the circuit receives a clock signal, otherwise LLC
and CREF are generated by the internal crystal oscillator.
VDDD2
37
digital supply voltage 2
1995 Sep 21
Video Port VP2. In 444 input mode, this is input for the V-signal.
Video Port VP1. This is an input for CCIR 656 compatible, multiplexed video data, or during
other input modes, this is the Y-signal.
On-Screen Display data. This is the index for the internal OSD look-up table.
4
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
SYMBOL
PIN
DESCRIPTION
LLC
38
Line-Locked Clock. This is the 24.54 MHz or 29.5 MHz master clock for the encoder. The
direction is set by the CDIR pin.
CREF
39
Clock Reference signal. This is the clock qualifier for DIG-TV2 compatible signals.
XTALO
40
Crystal oscillator output (to crystal).
XTALI
41
Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected
to ground.
VDDD3
42
digital supply voltage 3
RTCI
43
Real Time Control Input. If the clock is provided by an SAA7191B, RTCI should be connected
to the RTCO pin of the decoder to improve the signal quality.
AP
44
Test pin. Connected to digital ground for normal operation.
SP
45
Test pin. Connected to digital ground for normal operation.
VrefL
46
Lower reference voltage input for the DACs.
VrefH
47
Upper reference voltage input for the DACs.
VDDA1
48
Analog supply voltage 1 for the DACs and output amplifiers.
CHROMA
49
Analog output of the chrominance signal.
VDDA2
50
Analog supply voltage 2 for the DACs and output amplifiers.
Y
51
Analog output of the luminance signal.
VSSA
52
Analog ground for the DACs and output amplifiers.
CVBS
53
Analog output of the CVBS signal.
VDDA3
54
Analog supply voltage 3 for the DACs and output amplifiers.
II
55
Current input for the output amplifiers, connect via a 15 kΩ resistor to VDDA.
VDDA4
56
Analog supply voltage 4 for the DACs and output amplifiers.
RESET
57
Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode.
The I2C-bus receiver waits for the START condition.
DTACK
58
Data acknowledge output of the parallel MPU interface, active LOW, otherwise high
impedance.
RW/SCL
59
If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface,
otherwise it is the I2C-bus serial clock input.
A0/SDA
60
If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface,
otherwise it is the I2C-bus serial data input/output.
CS/SA
61
If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface,
otherwise it is the I2C-bus slave address select pin. LOW: slave address = 88H, HIGH = 8CH.
VSSD6
62
digital ground 6
VP3(0)
63
VP3(1)
64
VP3(2)
65
VP3(3)
66
VDDD4
67
digital supply voltage 4
SEL_MPU
68
Select MPU interface input. If it is HIGH, the parallel MPU interface is active, otherwise the
I2C-bus interface will be used.
1995 Sep 21
Lower 4 bits of the Video Port VP3. If pin 68 (SEL_MPU) is HIGH, this is the data bus of the
parallel MPU interface. If it is LOW, there can be multiplexed UV lines (422) of the U-signal
(444) of the Video input.
5
Philips Semiconductors
Preliminary specification
44 AP
VrefL
46
45 SP
VrefH
47
48 VDDA1
49 CHROMA
50 VDDA2
51 Y
SAA7187
52 VSSA
53 CVBS
54 VDDA3
55 II
56 VDDA4
57 RESET
58 DTACK
60 A0/SDA
handbook, full pagewidth
59 RW/SCL
Digital video encoder (DENC2-SQ)
CS/SA 61
43 RTCI
VSSD6 62
42 VDDD3
VP3(0) 63
41 XTALI
VP3(1) 64
40 XTALO
VP3(2) 65
39 CREF
VP3(3) 66
38 LLC
VDDD4 67
37 VDDD2
SEL_MPU 68
36 CDIR
SAA7187
VSSD1 1
35 VSSD5
2
34 OSD2
VP3(5) 3
33 OSD1
VP3(6)
4
32 OSD0
VP3(7)
5
31 KEY
VP3(4)
Fig.2 Pin configuration.
1995 Sep 21
6
VP1(1) 26
VP1(2) 25
VP1(3) 24
VP1(4) 23
VP1(5) 22
VP1(6) 21
VP1(7) 20
27 VP1(0)
VSSD3 19
9
n.c. 18
VP2(0)
VDDD1 17
28 VSSD4
VP2(7) 16
8
VP2(6) 15
VSSD2
VP2(5) 14
29 RCM1
VP2(4) 13
7
VP2(3) 12
RCV2
VP2(2) 11
30 RCM2
VP2(1) 10
RCV1 6
MBG252
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
The IC can be programmed via I2C-bus or 8-bit MPU
interface, but only one interface configuration can be
active at a time; if 422 or 444 input format is being used,
only the I2C-bus interface can be selected.
FUNCTIONAL DESCRIPTION
The digital video encoder (DENC2-SQ) encodes digital
luminance and chrominance into analog CVBS and
simultaneously S-Video (Y/C) signals. NTSC-M and PAL
B/G standards also sub-standards are supported.
A number of possibilities are provided for setting of
different video parameters such as:
The basic encoder function consists of subcarrier
generation and colour modulation also insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements RS-170-A and CCIR 624.
Black and blanking level control
Colour subcarrier frequency
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the control interfaces to abort any running bus transfer and
to set register 3AH to contents 00H, register 61H to
contents 15H, and register 6CH to contents 00H. All other
control registers are not influenced by a reset.
For ease of analog post filtering the signals are twice
oversampled with respect to pixel clock before
digital-to-analog conversion.
For total filter transfer characteristics see Figs 3 to 6 for
60 Hz field rate, and Figs 7 to 10 for 50 Hz field rate. The
DACs are realized with full 10-bit resolution. The encoder
provides three 8-bit wide data ports, that serve different
applications.
Data manager
In the data manager, the demultiplexing scheme is chosen
in accordance with the input format.
The VP1 port accepts 8 lines multiplexed Cb-Y-Cr data
(CCIR 656 mode), or Y data only (444 mode).
Depending on hardware conditions (signals on pins KEY,
OSD2 to OSD0), and software programming either data
from the VP ports or from the OSD port are selected to be
encoded to CVBS and Y/C signals.
The VP2 port accepts Cr data in 444 input mode.
The VP3 port accepts Cb data (444 input mode) or
multiplexed Cb/Cr data (422 input mode). If not used for
video input data, it can alternatively also handle the data of
an 8-bit wide microprocessor interface.
Optionally, the OSD colour look-up tables located in this
block, can be read out in a pre-defined sequence (8 steps
per active video line), achieving e.g. a colour bar test
pattern generator without need for an external data
source. The colour bar function is only under software
control.
Minimum suppression of output chrominance alias
components approximately 1 MHz due to high frequency
444 input is better than 12 dB.
The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656
(D1 format) compatible, but the SAV, EAV, etc. codes are
not decoded.
Encoder
VIDEO PATH
A crystal-stable master clock (LLC) of 24.54 or 29.5 MHz,
which is twice the line-locked pixel clock, needs to be
supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided. Additionally, a DMSD2 compatible clock
interface, using CREF (input or output) and RTC (see
“data sheet SAA7191B” ) is available.
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y/C signals.
Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After having been inserted a fixed
synchronization level, in accordance with standard
composite synchronization schemes, a variable blanking
level, programmable also in a certain range, is inserted.
The DENC2-SQ synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock. DENC2-SQ can be timing master
or slave.
Transients of both synchronization pulses and start/stop of
blanking are reduced compared to overall luminance
bandwidth.
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21); it also supports OSD via
KEY and three-bit overlay techniques by a 24 × 8 LUT.
1995 Sep 21
7
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
In order to enable easy analog post filtering, luminance is
interpolated from square pixel data rate to twice that rate
(24.54 or 29.5 MHz respectively), providing luminance in
10-bit resolution. For transfer characteristic of the
luminance interpolation filter see Figs 5 and 6 for 60 Hz
field rate and Figs 9 and 10 for 50 Hz field rate.
Output interface
In the output interface encoded Y and C signals are
converted from digital-to-analog in 10-bit resolution both Y
and C signals are combined to a 10-bit CVBS signal, also;
in front of the summation point, the luminance signal can
optionally be fed through a further filter stage, suppressing
components in the range of subcarrier frequency. Thus, a
type of cross colour reduction is provided, which is useful
in a standard TV set with CVBS input.
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
correctly to 24.54 or 29.5 MHz data rate. One of the
interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for Y/C
output. For transfer characteristics of the chrominance
interpolation filter see Figs 3 and 4 for 60 Hz field rate and
Figs 7 and 8 for 50 Hz field rate.
Slopes of synchronization pulses are not affected with any
cross colour reduction active.
Three different filter characteristics or bypass are
available, see Fig.5 for 60 Hz field rate and Fig.9 for 50 Hz
field rate.
The amplitude of inserted burst is programmable in a
certain range, suitable for standard signals and for special
effects. Behind the succeeding quadrature modulator,
colour in 10-bit resolution is provided on subcarrier.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitudes at the input
of the DAC for CVBS is reduced by 15⁄16 with respect to Y
and C DACs to make maximum use of conversion ranges.
The numeric ratio between Y and C outputs is in
accordance with set standards.
Outputs of all DACs can be set together via software
control to minimum output voltage for either purpose.
CLOSED CAPTION ENCODER
Synchronization
Using this circuit, data in accordance with the specification
of Closed Caption or Extended Data Service, delivered by
the control interface, can be encoded (Line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
The synchronization of the DENC2-SQ is able to operate
in two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to the video signal on VP ports
can be influenced by programming the polarity and on-chip
delay of RCV1. Active slope of RCV1 defines the vertical
phase and optionally the odd/even and colour frame phase
to be initialized, it can be also used to set the horizontal
phase.
The actual line number where data is to be encoded in, can
be modified in a certain range.
Data clock frequency is in accordance with definition for
NTSC-M standard 32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
If the horizontal phase is not be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin.
Timing and trigger behaviour can also be influenced for
RCV2.
It is also possible to encode Closed Caption Data for 50 Hz
field frequencies at 32 times horizontal line frequency.
1995 Sep 21
8
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Two I2C-bus slave addresses can be selected
(pin SEL_MPU must be LOW):
If there are missing pulses at RCV1 and/or RCV2, the time
base of DENC2-SQ runs free, thus an arbitrary number of
synchronization slopes may miss, but no additional pulses
(such with wrong phase) must occur.
88H: LOW at pin 61
8CH: HIGH at pin 61.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
The parallel interface is defined by:
D7 to D0 data bus
CS active-LOW chip select signal
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
RW read/not write signal, LOW for a write cycle
DTACK 680xx style data acknowledge (handshake),
active-LOW
• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or
A0 register select, LOW selects address, HIGH selects
data.
• An ODD/EVEN signal which is LOW in odd fields, or
• A field sequence signal (FSEQ) which is HIGH in the first
of 4 respectively 8 fields.
The parallel interface uses two registers, one
auto-incremental containing the current address of a
control register (equals subaddress with I2C-bus control),
one containing actual data. The currently addressed
register is mapped to the corresponding control register.
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up e.g. a
composite blanking signal.
The status byte can be read optionally via a read access
to the address register, no other read access is provided.
The phase of the pulses output on RCV1 or RCV2 are
referenced to the VP ports, polarity of both signals is
selectable.
Input levels and formats
DENC2-SQ expects digital YUV data with levels (digital
codes) in accordance with CCIR 601.
On the RCM1 port the same signals as on RCV1 (as
output) are available; on RCM2 the IC provides a
horizontal pulse with programmable start and stop phase.
The length of a field also start and end of its active part can
be programmed. The active part of a field always starts at
the beginning of a line.
Deviating amplitudes of the colour difference signals can
be compensated by independent gain control setting,
while gain for luminance is set to predefined values,
distinguishable for 7.5 IRE set-up or without set-up.
Control interface
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
DENC2-SQ contains two control interfaces: an I2C-bus
slave transceiver and 8-bit parallel microprocessor
interface. The interfaces cannot be used simultaneously.
When the IC is operating with input data in accordance
with CCIR 656, programming can be carried out
alternatively via the parallel interface using VP3 port for
data transfer.
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 100 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
1995 Sep 21
For other input modes, the I2C-bus interface has to be
used for programming.
9
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
Table 1
CCIR signal component levels
SIGNAL
Y
IRE
DIGITAL LEVEL
0
16
50
126
100
235
bottom peak
16
colourless
128
top peak
240
Cb
bottom peak
16
colourless
128
top peak
240
Cr
Table 2
SAA7187
CODE
straight binary
straight binary
straight binary
8-bit multiplexed format (similar to CCIR 656)
FORMAT
TIME
0
Sample
Cb0
Luminance pixel number
1
2
Y0
Cr0
0
4
Y1
Cb2
1
Colour pixel number
Table 3
3
5
6
Y2
Cr2
2
7
Y3
3
0
2
16-bit multiplexed format (DTV2 format)
FORMAT
TIME
0
Sample Y line
Sample UV line
Luminance pixel number
1
3
4
5
6
7
Y0
Y1
Y2
Y3
Cb0
Cr0
Cb2
Cr2
0
1
2
3
Colour pixel number
Table 4
2
0
2
24-bit direct 444 format
FORMAT
TIME
0
1
2
3
4
5
6
7
Sample Y line
Y0
Y1
Y2
Y3
Sample U line
Cb0
Cb1
Cb2
Cb3
Sample V line
Cr0
Cr1
Cr2
Cr3
Luminance pixel number
0
1
2
3
Colour pixel number
0
1
2
3
1995 Sep 21
10
1995 Sep 21
00
3A
42
43
44
Input port control
OSD LUT Y0
OSD LUT U0
OSD LUT V0
5B
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
Gain U MSB, black level
Gain V MSB, blanking level
Null
Cross-colour select
Standard control
Burst amplitude
Subcarrier 0
Subcarrier 1
Subcarrier 2
Subcarrier 3
Line 21 odd 0
Line 21 odd 1
Line 21 even 0
Line 21 even 1
CC line
5A
Chrominance phase
5C
59
OSD LUT V7
Gain V
58
OSD LUT U7
Gain U
57
OSD LUT Y7
45 to 56
39
01 to 38
Null
Null
SUB
ADDRESS
11
0
L21E17
L21E07
L21O17
0
L21E16
L21E06
L21O16
L21O06
FSC30
FSC22
FSC14
FSC06
BSTA6
DOWN
CCRS0
0
0
0
GAINV6
GAINU6
CHPS6
OSDV76
OSDU76
OSDY76
OSDV06
OSDU06
OSDY06
0
0
0
D6
0
L21E15
L21E05
L21O15
L21O05
FSC29
FSC21
FSC13
FSC05
BSTA5
INPI1
0
0
BLNNL5
BLCKL5
GAINV5
GAINU5
CHPS5
OSDV75
OSDU75
OSDY75
OSDV05
OSDU05
OSDY05
0
0
0
D5
SCCLN4
L21E14
L21E04
L21O14
L21O04
FSC28
FSC20
FSC12
FSC04
BSTA4
YGS
0
0
BLNNL4
BLCKL4
GAINV4
GAINU4
CHPS4
OSDV74
OSDU74
OSDY74
OSDV04
OSDU04
OSDY04
0
0
0
D4
↓
↓
SCCLN3
L21E13
L21E03
L21O13
L21O03
FSC27
FSC19
FSC11
FSC03
BSTA3
RTCE
0
0
BLNNL3
BLCKL3
GAINV3
GAINU3
CHPS3
OSDV73
OSDU73
OSDY73
OSDV03
OSDU03
OSDY03
VY2C
0
0
D3
DATA BYTE
SCCLN2
L21E12
L21E02
L21O12
L21O02
FSC26
FSC18
FSC10
FSC02
BSTA2
SCBW
0
0
BLNNL2
BLCKL2
GAINV2
GAINU2
CHPS2
OSDV72
OSDU72
OSDY72
OSDV02
OSDU02
OSDY02
VUV2C
0
0
D2
SCCLN1
L21E11
L21E01
L21O11
L21O01
FSC25
FSC17
FSC09
FSC01
BSTA1
PAL
0
0
BLNNL1
BLCKL1
GAINV1
GAINU1
CHPS1
OSDV71
OSDU71
OSDY71
OSDV01
OSDU01
OSDY01
FMT1
0
0
D1
SCCLN0
L21E10
L21E00
L21O10
L21O00
FSC24
FSC16
FSC08
FSC00
BSTA0
FISE
0
0
BLNNL0
BLCKL0
GAINV0
GAINU0
CHPS0
OSDV70
OSDU70
OSDY70
OSDV00
OSDU00
OSDY00
FMT0
0
0
D0
Digital video encoder (DENC2-SQ)
L21O07
FSC31
FSC23
FSC15
FSC07
SQP
0
CCRS1
0
GAINV8
GAINU8
GAINV7
GAINU7
CHPS7
OSDV77
OSDU77
OSDY77
OSDV07
OSDU07
OSDY07
CBENB
0
0
D7
Slave receiver (slave address 88H or 8CH)
REGISTER FUNCTION
Table 5
Bit allocation map
Philips Semiconductors
Preliminary specification
SAA7187
1995 Sep 21
74
75
76
77
78
79
Null
Null
Null
Begin RCV2 output
End RCV2 output
MSBs RCV2 output
7D
73
MSBs master request
7C
72
End master request
MSBs field control
71
Begin master request
Last active line
70
fsc reset mode, Vertical trigger
7B
6F
Horizontal trigger
First active line
6E
Horizontal trigger
7A
6D
Field length
6C
RCM, CC mode
SUB
ADDRESS
RCV port control
REGISTER FUNCTION
12
0
LAL7
FAL7
FLEN7
0
ERCV7
BRCV7
0
0
0
0
EMRQ7
BMRQ7
PHRES1
0
HTRIG7
0
SRCV11
D7
0
LAL6
FAL6
FLEN6
ERCV10
ERCV6
BRCV6
0
0
0
EMRQ10
EMRQ6
BMRQ6
PHRES0
0
HTRIG6
0
SRCV10
D6
LAL8
LAL5
FAL5
FLEN5
ERCV09
ERCV5
BRCV5
0
0
0
EMRQ09
EMRQ5
BMRQ5
SBLBN
0
HTRIG5
0
TRCV2
D5
FAL8
LAL4
FAL4
FLEN4
ERCV08
ERCV4
BRCV4
0
0
0
EMRQ08
EMRQ4
BMRQ4
VTRIG4
0
HTRIG4
0
ORCV1
D4
0
LAL3
FAL3
FLEN3
0
ERCV3
BRCV3
0
0
0
0
EMRQ3
BMRQ3
VTRIG3
0
HTRIG3
SRCM11
PRCV1
D3
DATA BYTE
0
LAL2
FAL2
FLEN2
BRCV10
ERCV2
BRCV2
0
0
0
BMRQ10
EMRQ2
BMRQ2
VTRIG2
HTRIG10
HTRIG2
SRCM10
CBLF
D2
FLEN9
LAL1
FAL1
FLEN1
BRCV09
ERCV1
BRCV1
0
0
0
BMRQ09
EMRQ1
BMRQ1
VTRIG1
HTRIG09
HTRIG1
CCEN1
ORCV2
D1
FLEN8
LAL0
FAL0
FLEN0
BRCV08
ERCV0
BRCV0
0
0
0
BMRQ08
EMRQ0
BMRQ0
VTRIG0
HTRIG08
HTRIG0
CCEN0
PRCV2
D0
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
I2C-bus format
I2C-bus address; see Table 7
Table 6
S
SLAVE ADDRESS
Table 7
ACK
SUBADDRESS
ACK
DATA 0
ACK
--------
DATA n
ACK
P
Explanation of Table 6
PART
DESCRIPTION
S
START condition
Slave address
1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1)
ACK
acknowledge, generated by the slave
Subaddress (note 2)
subaddress byte
DATA
data byte
--------
continued data bytes and ACKs
P
STOP condition
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
Slave receiver
Table 8
Subaddress 3A
DATA BYTE
FMT
LOGIC LEVEL
see Table 9
VUV2C
VY2C
CBENB
Table 9
DESCRIPTION
Select input data format.
0
Cb/Cr data input to VP ports is two’s complement. Default after reset.
1
Cb/Cr data input to VP ports is straight binary.
0
Y data input to VP1 port is two’s complement. Default after reset.
1
Y data input to VP1 port is straight binary.
0
Data from input ports is encoded. Default after reset.
1
Colour bar with programmable colours (entries of OSD_LUTs) is encoded.
The LUTs are read in upward order from index 0 to index 7.
Logic levels and function of FMT
DATA BYTE
FUNCTION
FMT1
FMT0
0
0
Input data YUV 444, 24 lines, Y on VP1, Cr on VP2, Cb on VP3. Default after reset.
0
1
Input data YUV 422, 16 lines, Y on VP1, multiplexed CbCr on VP3.
1
0
Input data YUV 422, 8 lines, multiplexed in accordance with CCIR 656 on VP1.
1
1
Input data YUV 422, 8 lines, multiplexed in accordance with CCIR 656 on VP1.
1995 Sep 21
13
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 10 Subaddress 42 to 59
DATA BYTE (note 1)
COLOUR
INDEX (note 2)
OSDY
White
Yellow
Cyan
Green
Magenta
Red
Blue
Black
OSDU
OSDV
107 (6BH)
0 (00H)
0 (00H)
107 (6BH)
0 (00H)
0 (00H)
82 (52H)
144 (90H)
18 (12H)
34 (22hH
172 (ACH)
14 (0EH)
42 (2AH)
38 (26H)
144 (90H)
03 (03H)
29 (1DH)
172 (ACH)
17 (11H)
182 (B6H)
162 (A2H)
240 (F0H)
200 (C8H)
185 (B9H)
234 (EAH)
74 (4AH)
94 (5EH)
212 (D4H)
56 (38H)
71 (47H)
209 (D1H)
218 (DAH)
112 (70H)
193 (C1H)
227 (E3H)
84 (54H)
169 (A9H)
112 (70H)
238 (EEH)
163 (A3H)
84 (54H)
242 (F2H)
144 (90H)
0 (00H)
0 (00H)
144 (90H)
0 (00H)
0 (00H)
0
1
2
3
4
5
6
7
Notes
1. Contents of OSD Look-up tables. All 8 entries are 8-bits. Data representation is in accordance with CCIR 601
(Y, Cb, Cr), but two’s complement, e.g. for a 100⁄100 (upper number) or 100⁄75 (lower number) colour bar.
2. For normal colour bar with CBENB = logic 1.
Table 11 Subaddress 5A
DATA BYTE
CHPS
DESCRIPTION
Phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in
steps of 360 or 256 degrees.
Table 12 Subaddress 5B and 5D
DATA BYTE
GAINU
DESCRIPTION
CONDITIONS
variable gain for Cb signal; white-to-black = 92.5
input representation
GAINU = 0
accordance with CCIR 601
GAINU = 118 (76H)
white-to-black = 100
output subcarrier of U contribution = 0
output subcarrier of U contribution = nominal
IRE(2)
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 125 (7DH)
output subcarrier of U contribution = nominal
Notes
1. GAINU = −2.17 × nominal to +2.16 × nominal.
2. GAINU = −2.05 × nominal to +2.04 × nominal.
1995 Sep 21
REMARKS
IRE(1)
14
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 13 Subaddress 5C and 5E
DATA BYTE
GAINV
DESCRIPTION
CONDITIONS
variable gain for Cr signal; white-to-black = 92.5 IRE(1)
input representation
GAINV = 0
accordance with CCIR 601
GAINV = 165 (A5H)
white-to-black = 100
REMARKS
output subcarrier of V contribution = 0
output subcarrier of V contribution = nominal
IRE(2)
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 175 (AFH)
output subcarrier of V contribution = nominal
Notes
1. GAINV = −1.55 × nominal to +1.55 × nominal.
2. GAINV = −1.46 × nominal to +1.46 × nominal.
Table 14 Subaddress 5D
DATA BYTE
BLCKL
DESCRIPTION
CONDITIONS
variable black level; input white-to-sync = 140 IRE(1)
representation accordance
BLCKL = 0
with CCIR 601
BLCKL = 63 (3FH)
REMARKS
output black level = 24 IRE
output black level = 49 IRE
white-to-sync = 143 IRE(2)
BLCKL = 0
output black level = 24 IRE
BLCKL = 63 (3FH)
output black level = 50 IRE
Notes
1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal.
2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
Table 15 Subaddress 5E
DATA BYTE
BLNNL
DESCRIPTION
variable blanking level
CONDITIONS
REMARKS
white-to-sync = 140 IRE(1)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 42 IRE
white-to-sync = 143 IRE(2)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 43 IRE
Notes
1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal.
2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal.
1995 Sep 21
15
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 16 Subaddress 60 (CCRS; select cross colour reduction filter in luminance)
DATA BYTE
FUNCTION
CCRS1
CCRS0
0
0
no cross colour reduction (for transfer characteristic of luminance see Figs 5 and 9)
0
1
cross colour reduction #1 active (for transfer characteristic see Figs 5 and 9)
1
0
cross colour reduction #2 active (for transfer characteristic see Figs 5 and 9)
1
1
cross colour reduction #3 active (for transfer characteristic see Figs 5 and 9)
Table 17 Subaddress 61
DATA BYTE
FISE
PAL
SCBW
RTCE
YGS
INPI
DOWN
1995 Sep 21
LOGIC LEVEL
DESCRIPTION
0
944 total pixel clocks per line
1
780 total pixel clocks per line; default after reset
0
NTSC encoding (non-alternating V component); default after reset
1
PAL encoding (alternating V component)
0
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3, 4, 7 and 8)
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3, 4, 7 and 8); default after reset
0
no real time control of generated subcarrier frequency; default after reset
1
real time control of generated subcarrier frequency through SAA7191B
(timing see Fig.13)
0
luminance gain for white-to-black 100 IRE
1
luminance gain for white-to-black 92.5 IRE including 7.5 IRE set-up of black;
default after reset
0
PAL switch phase is nominal; default after reset
1
PAL switch phase is inverted compared to nominal
0
DACs in normal operational mode; default after reset
1
DACs forced to lowest output voltage
16
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 18 Subaddress 62
DATA BYTE
BSTA
DESCRIPTION
amplitude of colour burst;
input representation
accordance with
CCIR 601
CONDITIONS
REMARKS
white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding
BSTA = 0 to 1.25 × nominal(1)
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding
BSTA = 0 to 1.76 × nominal(2)
white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding
BSTA = 0 to 1.20 × nominal(3)
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding
BSTA = 0 to 1.67 × nominal(4)
SQP
subcarrier real time
logic 0
not supported in current version,
do not use
logic 1
control from SAA7191B digital
colour decoder
Notes
1. Recommended value: BSTA = 102 (66H).
2. Recommended value: BSTA = 72 (48H).
3. Recommended value: BSTA = 106 (6AH).
4. Recommended value: BSTA = 75 (4BH).
Table 19 Subaddress 63 to 66 (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
CONDITIONS
FSC0 to FSC3 fsc = subcarrier frequency
 f sc
32 
FSC = round  ---------- × 2 
(in multiples of line
 f LLC

frequency);
fLLC = clock frequency (in see note 1
multiples of line frequency)
Note
1. Examples:
a) NTSC-M: fsc = 227.5, fLLC = 1560 → FSC = 626349397 (25555555H).
b) PAL-B/G: fsc = 283.7516, fLLC = 1888 → FSC = 645499916 (26798C0CH).
1995 Sep 21
17
REMARKS
FSC3 = most significant byte
FSC0 = least significant byte
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 20 Subaddress 67 to 6A
DATA BYTE(1)
DESCRIPTION
L21O0
first byte of captioning data, odd field
L21O1
second byte of captioning data, odd field
L21E0
first byte of extended data, even field
L21E1
second byte of extended data, even field
Note
1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format.
Table 21 Subaddress 6B
DATA BYTE
SCCLN
DESCRIPTION
selects the actual line, where closed caption or extended data are encoded; see note 1
Note
1. Line = (SCCLN + 4) for M systems; line = (SCCLN + 1) for other systems.
Table 22 Subaddress 6C
DATA BYTE
PRCV2
LOGIC LEVEL
DESCRIPTION
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
ORCV2
0
pin RCV2 is switched to input; default after reset
1
pin RCV2 is switched to output
CBLF
0
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse
that is HIGH during active portion of line, also during vertical blanking Interval);
default after reset
1
if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only
(if TRCV2 = 1); default after reset
if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization
(if TRCV2 = 1) also as an internal blanking signal
PRCV1
ORCV1
TRCV2
SRCV1
1995 Sep 21
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
1
polarity of RCV1 as output is active LOW, falling edge is taken when input,
respectively
0
pin RCV1 is switched to input; default after reset
1
pin RCV1 is switched to output
0
horizontal synchronization is taken from RCV1 port; default after reset
1
horizontal synchronization is taken from RCV2 port
−
defines signal type on pin RCV1; see Table 23
18
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 23 Logic levels and function of SRCV1
DATA BYTE
AS OUTPUT
AS INPUT
VS
VS
SRCV11
SRCV10
0
0
0
1
FS
FS
1
0
FSEQ
FSEQ
1
1
−
−
FUNCTION
Vertical Sync each field; default after reset
Frame Sync (odd/even)
Field Sequence, vertical sync every fourth field
(FISE = 1) or eighth field (FISE = 0)
not applicable
Table 24 Subaddress 6D
DATA BYTE
DESCRIPTION
CCEN
enables individual line 21 encoding; see Table 25
SRCM
defines signal type on pin RCM1; see Table 26
Table 25 Logic levels and function of CCEN
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
line 21 encoding off
0
1
enables encoding in field 1 (odd)
1
0
enables encoding in field 2 (even)
1
1
enables encoding in both fields
Table 26 Logic levels and function of SRCM
DATA BYTE
AS OUTPUT
SRCM1
SRCM0
0
0
0
1
FS
1
0
FSEQ
1
1
−
VS
FUNCTION
Vertical Sync each field
Frame Sync (odd/even)
Field Sequence, vertical sync every fourth field (FISE = 1) or
eighth field (FISE = 0)
not applicable
Table 27 Subaddress 6E to 6F
DATA BYTE
HTRIG
DESCRIPTION
sets the Horizontal Trigger phase related to signal on RCV1 or RCV2 input
values above 1559 (FISE = 1) or 1887 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = 031H (033H)
1995 Sep 21
19
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 28 Subaddress 70
DATA BYTE
LOGIC LEVEL
−
VTRIG
DESCRIPTION
sets the Vertical Trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
SBLBN
PHRES
0
vertical blanking is defined by programming of FAL and LAL
1
vertical blanking is forced automatically at least during field synchronization and
equalization pulses; note 1
−
selects the phase reset mode of the colour subcarrier generator; see Table 29
Note
1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events.
Table 29 Logic levels and function of PHRES
DATA BYTE
FUNCTION
PHRES1
PHRES0
0
0
no reset
0
1
reset every two lines
1
0
reset every eight fields
1
1
reset every four fields
Table 30 Subaddress 71 to 73
DATA BYTE
BMRQ
DESCRIPTION
beginning of master request signal (RCM2)
values above 1559 (FISE = 1) or 1887 (FISE = 0) are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at
BMRQ = 0E1H (130H)
EMRQ
end of master request signal (RCM2)
values above 1559 (FISE = 1) or 1887 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at
EMRQ = 5E9H (72AH)
Table 31 Subaddress 77 to 79
DATA BYTE
BRCV
DESCRIPTION
beginning of output signal on RCV2 pin
values above 1559 (FISE = 1) or 1887 (FISE = 0) are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
BRCV = 0E1H (130H)
ERCV
end of output signal on RCV2 pin
values above 1559 (FISE = 1) or 1887 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
ERCV = 5E9H (72AH)
1995 Sep 21
20
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
Table 32 Subaddress 7A to 7D
DATA BYTE
FLEN
DESCRIPTION
Length of a Field = FLEN + 1, measured in half lines
valid range is limited to 524 to 1022 (FISE = 1) respectively 624 to 1022 (FISE = 0),
FLEN should be even
FAL
First Active Line, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
Last Active Line, measured in lines
LAL = 0 coincides with the first field synchronization pulse
SUBADDRESSES
In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.
Slave transmitter
Table 33 Slave transmitter (slave address 89H or 8DH)
REGISTER
FUNCTION
DATA BYTE
SUBADDRESS
−
Status byte
D7
D6
D5
VER2
VER1
VER0
D4
D3
CCRDO CCRDE
D2
D1
D0
FSQ2
FSQ1
FSQ0
Table 34 No subaddress
DATA BYTE
DESCRIPTION
VER
Version identification of the device. It will be changed with all versions of the IC that have different
programming models. Current Version is 000 binary.
CCRDE
Closed caption bytes of the even field have been encoded.
The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately
after the data have been encoded.
CCRDO
Closed caption bytes of the odd field have been encoded.
The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately
after the data have been encoded.
FSQ
State of the internal field sequence counter.
Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH.
1995 Sep 21
21
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
MBG257
handbook, full
6 pagewidth
Gv
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
(1) SCBW = 1; 444 input.
(2) SCBW = 0; 444 input.
Fig.3 Chrominance transfer characteristic 1 (60 Hz).
MBG255
handbook, halfpage
2
Gv
(dB)
0
(1)
(3)
(2)
(4)
−2
−4
−6
(1)
(2)
(3)
(4)
0
0.4
0.8
1.2
f (MHz)
1.6
SCBW = 1.
SCBW = 0.
SCBW = 1; 444 input.
SCBW = 0; 444 input.
Fig.4 Chrominance transfer characteristic 2 (60 Hz).
1995 Sep 21
22
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
MBG258
6
Gv full pagewidth
handbook,
(dB)
(1)
0
(2)
−6
(4)
(3)
−12
−18
−24
−30
−36
−42
−48
−54
0
(1)
(2)
(3)
(4)
2
4
6
8
10
CCRS1 = 0; CCRS0 = 0.
CCRS1 = 0; CCRS0 = 1.
CCRS1 = 1; CCRS0 = 0.
CCRS1 = 1; CCRS0 = 1.
Fig.5 Luminance transfer characteristic 1 (60 Hz).
MBG256
handbook, halfpage
1
Gv
(dB)
0
−1
−2
−3
−4
−5
0
2
4
f (MHz)
6
CCRS1 = 0; CCRS0 = 0.
Fig.6 Luminance transfer characteristic 2 (60 Hz).
1995 Sep 21
23
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
MBG261
handbook, full
6 pagewidth
Gv
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
(1) SCBW = 1; 444 input.
(2) SCBW = 0; 444 input.
Fig.7 Chrominance transfer characteristic 1 (50 Hz).
MBG262
2
handbook, halfpage
Gv
(dB)
0
(1)
(3)
(2)
(4)
−2
−4
−6
(1)
(2)
(3)
(4)
0
0.4
0.8
1.2 f (MHz) 1.6
SCBW = 1.
SCBW = 0.
SCBW = 1; 444 input.
SCBW = 0; 444 input.
Fig.8 Chrominance transfer characteristic 2 (50 Hz).
1995 Sep 21
24
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
MBG263
6
Gv full pagewidth
handbook,
(dB)
(1)
0
(2)
−6
(3)
(4)
−12
−18
−24
−30
−36
−42
−48
−54
0
(1)
(2)
(3)
(4)
2
4
6
8
10
CCRS1 = 0; CCRS0 = 0.
CCRS1 = 0; CCRS0 = 1.
CCRS1 = 1; CCRS0 = 0.
CCRS1 = 1; CCRS0 = 1.
Fig.9 Luminance transfer characteristic 1 (50 Hz).
MBG264
handbook, halfpage
1
Gv
(dB)
0
−1
−2
−3
−4
−5
0
2
4
f (MHz)
6
CCRS1 = 0; CCRS0 = 0.
Fig.10 Luminance transfer characteristic 2 (50 Hz).
1995 Sep 21
25
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
CHARACTERISTICS
VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supply
VDDD
digital supply voltage
4.5
5.5
V
VDDA
analog supply voltage
4.75
5.25
V
IDDD
digital supply current
note 1
−
210
mA
IDDA
analog supply current
note 1
−
55
mA
V
Inputs
VIL
LOW level input voltage
(except SDA, SCL, AP, SP and XTALI)
−0.5
+0.8
VIH
HIGH level input voltage
(except SDA, SCL, AP, SP and XTALI)
2.0
VDDD + 0.5 V
HIGH level input voltage (LLC)
2.4
VDDD + 0.5 V
ILI
input leakage current
−
1
µA
Ci
input capacitance
clocks operating
−
10
pF
data available
−
8
pF
I/Os at high impedance
−
8
pF
V
Outputs
VOL
LOW level output voltage
(except SDA and XTALO)
note 2
0
0.6
VOH
HIGH level output voltage
(except SDA, DTACK and XTALO)
note 2
2.4
VDDD + 0.5 V
HIGH level output voltage (LLC)
note 2
2.6
VDDD + 0.5 V
I2C-bus;
SDA and SCL
VIL
LOW level input voltage
−0.5
+1.5
VIH
HIGH level input voltage
3.0
VDDD + 0.5 V
V
II
input current
VI = LOW or HIGH
−
±10
µA
VOL
LOW level output voltage (SDA)
IOL = 3 mA
−
0.4
V
IO
output current
during acknowledge
3
−
mA
Clock timing (LLC)
TLLC
cycle time
note 3
31
44
ns
δ
duty factor tHIGH/TLLC
note 4
40
60
%
tr
rise time
note 3
−
5
ns
tf
fall time
note 3
−
6
ns
1995 Sep 21
26
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SYMBOL
SAA7187
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Input timing
tSU;CREF
input data set-up time (CREF)
6
−
ns
tHD;CREF
input data hold time (CREF)
3
−
ns
tSU
input data set-up time (any other except
SEL_MPU, CDIR, RW/SCL, A0/SDA,
CS/SA, RESET, AP and SP)
6
−
ns
tHD
input data hold time (any other except
SEL_MPU, CDIR, RW/SCL, A0/SDA,
CS/SA, RESET, AP and SP)
3
−
ns
Crystal oscillator
fn
nominal frequency
(usually 24.545454 or 29.5 MHz)
3rd harmonic
−
30
MHz
∆f/fn
permissible deviation of nominal frequency
note 5
−50
+50
10−6
CRYSTAL SPECIFICATION
Tamb
operating ambient temperature
0
70
°C
CL
load capacitance
8
−
pF
RS
series resonance resistance
−
80
Ω
C1
motional capacitance (typical)
1.5 −20%
1.5 +20%
fF
C0
parallel capacitance (typical)
3.5 −20%
3.5 +20%
pF
MPU interface timing
9
−
ns
0
−
ns
9
−
ns
0
−
ns
−
440
ns
notes 7 and 8; n = 5
−
275
ns
note 6
9
−
ns
tAS
address set-up time
tAH
address hold time
tRWS
read/write set-up time
tRWH
read/write hold time
tDD
data valid from CS (read)
notes 7, 8 and 9; n = 9
tDF
data bus floating from CS (read)
tDS
data bus set-up time (write)
tDH
data bus hold time (write)
note 6
9
−
ns
tACS
acknowledge delay from CS
notes 7 and 8; n = 11
−
520
ns
tCSD
CS HIGH from acknowledge
0
−
ns
tDAT
DTACK floating from CS HIGH
−
360
ns
7.5
40
pF
4
−
ns
−
25
ns
note 6
note 6
notes 7 and 8; n = 7
Data and reference signal output timing
CL
output load capacitance
tOH
output hold time
tOD
output delay time
1995 Sep 21
CREF in output mode
27
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SYMBOL
SAA7187
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
CHROMA, Y and CVBS outputs
Vo(p-p)
output signal voltage (peak-to-peak value)
1.9
2.1
V
RI
internal serial resistance
note 10
18
35
Ω
RL
output load resistance
80
−
Ω
B
output signal bandwidth of DACs
10
−
MHz
ILE
LF integral linearity error of DACs
−3 dB
−
±2
LSB
DLE
LF differential linearity error of DACs
−
±1
LSB
Notes
1. At maximum supply voltage with highly active input signals.
2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF.
3. The data is for both input and output direction.
4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.
5. If an internal oscillator is used, crystal deviation of nominal frequency (fn) is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
6. The value is calculated via equation t = t SU + t HD
7. The value depends on the clock frequency. The numbers given are calculated with fLLC = 24.54 MHz.
8. The values given are calculated via equation t dmax = t OD + n × t LLC + t LLC + t SU
9. The falling edge of DTACK will always occur1 × LLC after data is valid.
10. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output
voltage (digital zero at DAC) is 0.2 V.
1995 Sep 21
28
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
handbook, full pagewidth
SAA7187
TLLC
tHIGH
2.6 V
1.5 V
0.6 V
LLC clock output
tHD; DAT
tf
tr
TLLC
tHIGH
2.4 V
1.5 V
0.8 V
LLC clock input
tSU; DAT
tHD; DAT
tf
tr
2.0 V
input data
valid
valid
not valid
0.8 V
td
tHD; DAT
2.4 V
output data
valid
valid
not valid
0.6 V
MBE742
Fig.11 Clock data timing.
handbook, full pagewidth
LLC
CREF
VP1(n)
Y(0)
Y(1)
Y(2)
Y(3)
Y(4)
VP3(n)
Cb(0)
Cr(0)
Cb(2)
Cr(2)
Cb(4)
RCV2
MBG259
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 lines digital TV format, because these signals are only valid in 12.27 or 14.75 MHz.
The phase of the RCV2 signal is programmed to 0E1H (130H for 50 Hz) in this example in output mode (BRCV2).
Fig.12 Digital TV timing.
1995 Sep 21
29
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
handbook, full pagewidth
H/L transition
count start
128
HPLL
increment
13
SAA7187
4 bits
reserved
3 bits
reserved
sequence
bit (1)
reserved (2)
FSCPLL increment
0
22
0
RTCI
not used in DENC2-SQ
valid
invalid
sample sample
(1) Sequence bit:
PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 276 with 50 Hz systems; 188 with 60 Hz systems.
Fig.13 RTCI timing.
1995 Sep 21
30
8/LLC
MBG260
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
handbook, full pagewidth
A0
tAS
tAH
tRWS
tRWH
CSN
RWN
D(7 to 0)
tDF
tDD
DTACK
tACS
tCSD
tDAT
MBE740
Fig.14 MPU interface timing (read cycle).
handbook, full pagewidth
A0
tAS
tAH
tRWS
tRWH
CSN
RWN
D(7 to 0)
tDF
tDS
DTACK
tACS
tCSD
Fig.15 MPU interface timing (write cycle).
1995 Sep 21
31
tDAT
MBE741
1995 Sep 21
X1
(3)
VDDD1
17
XTAL0
40
41
10
pF
XTAL1
3rd
harmonic
10
pF
37
32
67
SAA7187
42
VDDD3 VDDD4
VSSD
VSSD
VSSD
56
55
47
(1)
51
35 Ω (1) 49
VSSA
46
VrefL
VSSA
52
DAC1
48
VDDA1
35 Ω (1) 53
50
VDDA2
VSSA
VSSA
35 Ω
54
VDDA3
0.1 µF
0.1 µF
0.1 µF
DAC2
DAC3
II
VrefH
VSSD1 to VSSD6
0.1 µF
0.1 µF
15 kΩ
1, 8, 19, 28,
35, 62
VDDA1
VSSA
VSSA
+ 5 V analog
VSSD
Fig.16 Application environment of the DENC2-SQ.
VDDD2
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VSSA
Y
CVBS
1.23 V (p-p)(2)
VSSA
1.0 V (p-p) (2)
VSSA
CHROMA
0.62 V (p-p) (2)
MBG254
75 Ω
12 Ω
75 Ω
20 Ω
75 Ω
20 Ω
Digital video encoder (DENC2-SQ)
(1) Typical value.
(2) For 100⁄100 colour bar.
(3) 24.545454 or 29.5 MHz.
digital
inputs and
outputs
1
nF
10
µH
+ 5 V digital
handbook, full pagewidth
VSSD
Philips Semiconductors
Preliminary specification
SAA7187
APPLICATION INFORMATION
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
PACKAGE OUTLINE
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
eD
eE
y
X
60
A
44
43 Z E
61
bp
b1
w M
68
1
HE
E
pin 1 index
A
e
A4 A1
(A 3)
β
9
k1
27
Lp
k
detail X
10
26
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
A1
min.
A3
A4
max.
bp
b1
mm
4.57
4.19
0.51
0.25
3.30
0.53
0.33
0.81
0.66
0.180
inches
0.020 0.01
0.165
D (1)
E (1)
e
eD
eE
HD
HE
k
24.33 24.33
23.62 23.62 25.27 25.27 1.22
1.27
24.13 24.13
22.61 22.61 25.02 25.02 1.07
k1
max.
Lp
v
w
y
0.51
1.44
1.02
0.18
0.18
0.10
Z D(1) Z E (1)
max. max.
2.16
β
2.16
45 o
0.930 0.930 0.995 0.995 0.048
0.057
0.021 0.032 0.958 0.958
0.020
0.05
0.007 0.007 0.004 0.085 0.085
0.13
0.890 0.890 0.985 0.985 0.042
0.040
0.013 0.026 0.950 0.950
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT188-2
112E10
MO-047AC
1995 Sep 21
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-03-11
33
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
SOLDERING
Wave soldering
Introduction
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering
Reflow soldering techniques are suitable for all PLCC
packages.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
The choice of heating method may be influenced by larger
PLCC packages (44 leads, or more). If infrared or vapour
phase heating is used and the large packages are not
absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1995 Sep 21
34
Philips Semiconductors
Preliminary specification
Digital video encoder (DENC2-SQ)
SAA7187
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1995 Sep 21
35
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SCD43
© Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation
or contract, is believed to be accurate and reliable and may be changed without
notice. No liability will be accepted by the publisher for any consequence of its
use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Printed in The Netherlands
483061/1500/01/pp36
Document order number:
Date of release: 1995 Sep 21
9397 750 00325