Hardware Development Guide for i.MX 6SoloX Applications Processors

Hardware Development Guide for
i.MX 6SoloX Application Processors
Document Number: IMX6SXHDG
Rev. 1, 03/2016
Hardware Development Guide for i.MX 6SoloX Application Processors, Rev. 1, 03/2016
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Freescale Semiconductor, Inc.
Contents
Section number
Title
Page
Chapter 1
About this Book
1.1 Overview...........................................................................................................................................................................7
1.2 Essential reference............................................................................................................................................................ 7
1.3 Suggested reading............................................................................................................................................................. 8
1.4 Related documentation......................................................................................................................................................9
1.5 Conventions...................................................................................................................................................................... 9
1.6 Signal conventions............................................................................................................................................................ 10
1.7 Acronyms and abbreviations.............................................................................................................................................10
Chapter 2
i.MX 6SoloX Design Checklist
2.1 Overview...........................................................................................................................................................................13
2.2 Design Checklist Tables................................................................................................................................................... 13
2.3 Bus isolation circuit.......................................................................................................................................................... 22
2.4 DDR reference circuit....................................................................................................................................................... 23
2.5 JTAG signal termination...................................................................................................................................................23
2.6 Oscillator tolerance........................................................................................................................................................... 24
2.7 Unused analog interfaces.................................................................................................................................................. 24
Chapter 3
i.MX 6 Series Layout Recommendations
3.1 Introduction.......................................................................................................................................................................27
3.2 Basic design recommendations.........................................................................................................................................27
3.3 Stackup recommendations................................................................................................................................................ 28
3.4 DDR connection information............................................................................................................................................29
3.5 Routing considerations..................................................................................................................................................... 33
3.6 DDR power recommendations..........................................................................................................................................46
3.7 PCI Express interface recommendations.......................................................................................................................... 48
Chapter 4
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Section number
Title
Page
Avoiding Board Bring-up Problems
4.1 Introduction.......................................................................................................................................................................55
4.2 Using a current monitor to avoid power pitfalls............................................................................................................... 55
4.3 Using a voltage report to avoid power pitfalls..................................................................................................................55
4.4 Checking for clock pitfalls................................................................................................................................................56
4.5 Avoiding reset pitfalls.......................................................................................................................................................57
4.6 Sample board bring-up checklist...................................................................................................................................... 57
Chapter 5
Understanding the IBIS Model
5.1 Overview...........................................................................................................................................................................61
5.2 IBIS structure and content................................................................................................................................................ 61
5.3 Header Information...........................................................................................................................................................62
5.4 Component and pin information....................................................................................................................................... 62
5.5 Model information............................................................................................................................................................ 64
5.6 Freescale naming conventions for model names and usage in i.MX6 IBIS file...............................................................69
5.7 Quality assurance for the IBIS models............................................................................................................................. 73
5.8 IBIS usage.........................................................................................................................................................................73
5.9 References.........................................................................................................................................................................74
Chapter 6
Using the Manufacturing Tool
6.1 Overview...........................................................................................................................................................................75
6.2 Feature summary...............................................................................................................................................................75
6.3 Version support.................................................................................................................................................................76
6.4 Connecting the manufacturing tool to your device...........................................................................................................76
6.5 Installing the manufacturing tool...................................................................................................................................... 77
6.6 Using the manufacturing tool............................................................................................................................................81
6.7 Customizing the manufacturing tool.................................................................................................................................83
6.8 Other references................................................................................................................................................................ 83
Chapter 7
Using BSDL for Board-level Testing
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Section number
Title
Page
7.1 BSDL overview................................................................................................................................................................ 85
7.2 How BSDL functions........................................................................................................................................................85
7.3 Downloading the BSDL file............................................................................................................................................. 85
7.4 Pin coverage of BSDL...................................................................................................................................................... 86
7.5 Boundary scan operation...................................................................................................................................................86
7.6 I/O pin power considerations............................................................................................................................................ 87
Chapter 8
Appendix A Revision History
Chapter 9
Appendix B Development Platforms
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Chapter 1
About this Book
1.1 Overview
This document’s purpose is to help hardware engineers design and test their i.MX 6
series processor based designs. It provides information on board layout
recommendations, design checklists to ensure first-pass success and ways to avoid board
bring-up problems. It also provides information on board-level testing and simulation
such as using BSDL for board-level testing, using the IBIS model for electrical integrity
simulation and more.
Engineers are expected to have a working understanding of board layouts and
terminology, IBIS modeling, BSDL testing and common board hardware terminology.
This guide is released along with relevant device-specific hardware documentation such
as datasheets, reference manuals and application notes available on www.freescale.com.
1.1.1 Devices supported
This Hardware Developer’s Guide currently supports the i.MX 6SoloX.
1.2 Essential reference
This guide is intended as a companion to the i.MX 6 series chip reference manuals and
data sheets. For reflow profile and thermal limits during soldering, see application note
AN3298. These documents are available on www.freescale.com.
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Suggested reading
1.3 Suggested reading
This section lists additional reading that provides background for the information in this
manual as well as general information about the architecture.
1.3.1 General Information
The following documentation provides useful information about the ARM processor
architecture and computer architecture in general:
For information about the ARM Cortex-A9 processor see: http://www.arm.com/products/
processors/cortex-a/cortex-a9.php
• Computer Architecture: A Quantitative Approach (Fourth Edition) - by John L.
Hennessy and David A. Patterson
• Computer Organization and Design: The Hardware/Software Interface (Second
Edition), by David A. Patterson and John L. Hennessy
The following documentation provides useful information about high-speed board
design:
• Right the First Time- A Practical Handbook on High Speed PCB and System
Design - Volumes I & II - Lee W. Ritchey (Speeding Edge) - ISBN 0-97419360-72
• Signal and Power Integrity Simplified (2nd Edition) - Eric Bogatin (Prentice Hall)ISBN 0-13-703502-0
• High Speed Digital Design- A Handbook of Black Magic - Howard W. Johnson &
Martin Graham (Prentice Hall) - ISBN 0-13-395724-1
• High Speed Signal Propagation- Advanced Black Magic - Howard W. Johnson &
Martin Graham - (Prentice Hall) - ISBN 0-13-084408-X
• High Speed Digital System Design- A handbook of Interconnect Theory and
Practice - Hall, Hall and McCall (Wiley Interscience 2000) - ISBN 0-36090-2
• Signal Integrity Issues and Printed Circuit Design - Doug Brooks (Prentice Hall)
ISBN 0-13-141884-X
• PCB Design for Real-World EMI Control - Bruce R. Archambeault (Kluwer
Academic Publishers Group) - ISBN 1-4020-7130-2
• Digital Design for Interference Specifications - A Practical Handbook for EMI
Suppression - David L. Terrell & R. Kenneth Keenan (Newnes Publishing) - ISBN
0-7506-7282-X
• Electromagnetic Compatibility Engineering - Henry Ott (1st Edition - John Wiley
and Sons) - ISBN 0-471-85068-3
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Chapter 1 About this Book
• Introduction to Electromagnetic Compatibility - Clayton R. Paul (John Wiley and
Sons) - ISBN 978-0-470-18930-6
• Grounding & Shielding Techniques - Ralph Morrison (5th Edition - John Wiley &
Sons) - ISBN 0-471-24518-6
• EMC for Product Engineers - Tim Williams (Newnes Publishing) - ISBN 0-75062466-3
1.4 Related documentation
Freescale documentation is available from the sources listed on the back page of this
guide.
Additional literature is published as new Freescale products become available. For a
current list of documentation, see www.freescale.com.
1.5 Conventions
This document uses the following notational conventions:
Courier
Used to indicate commands, command parameters, code examples, and file and directory
names.
Italics
Italics indicates command or function parameters.
Bold
Function names are written in bold.
cleared/set
When a bit takes the value zero, it is said to be cleared; when it takes a value of one, it is said
to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold.
sig_name
Internal signals are written in all lowercase.
nnnn nnnnh
Denotes hexadecimal number.
0b
Denotes binary number.
rA, rB
Instruction syntax used to identify a source GPR.
rD
Instruction syntax used to identify a destination GPR.
REG[FIELD]
Abbreviations for registers are shown in uppercase text. Specific bits, fields, or ranges appear
in brackets. For example, MSR[LE] refers to the little-endian mode enable bit in the machine
state register.
x
In some contexts, such as signal encodings, an unitalicized x indicates a don’t care.
x
An italicized x indicates an alphanumeric variable.
n, m
An italicized n or m indicates a numeric variable.
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Signal conventions
NOTE
In this guide, notation for all logical, bit-wise, arithmetic,
comparison, and assignment operations follow C Language
conventions.
1.6 Signal conventions
_b, _B
Notation indicates that a signal is active when low.
signal_name
Lowercase italics is used to indicate internal signals.
1.7 Acronyms and abbreviations
The following table defines the acronyms and abbreviations used in this document.
Table 1-1. Definitions and acronyms
Term
Definition
ARM ®
Advanced RISC machines processor architecture
BGA
Ball grid array package
BOM
Bill of materials
BSDL
Boundary scan description language
CAN
Flexible Controller Area Network peripheral
CCM
Clock Controller Module
CSI
MIPI camera serial interface
DDR
Dual data rate DRAM
DDR3
DDR3 DRAM
DDR3L
Low voltage DDR3 DRAM
DDR3U
Ultra low voltage DDR3 DRAM
DRAM
Dynamic random access memory
ECSPI
Enhanced Configurable SPI peripheral
EIM
External Interface Module
ENET
10/100/1000-Mbps Ethernet MAC peripheral
EPIT
Enhanced Periodic Interrupt Timer peripheral
ESR
Equivalent series resistance (of a crystal)
FSL
Freescale Semiconductor
GND
Ground
GPC
General Power Controller
GPIO
General-purpose input/output
HDCP
High-bandwidth Digital Content Protection
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Chapter 1 About this Book
Table 1-1. Definitions and acronyms (continued)
I2C
Inter-integrated circuit interface
IBIS
Input output buffer information specification
IOMUX
i.MX6 chip-level I/O multiplexing
JTAG
Joint Test Action Group
KPP
Keypad Port peripheral
LDB
LVDS Display bridge
LDO
Low drop-out regulator
LPCG
Low power clock gating
LPDDR2
Low-power DDR2 DRAM
LVDS
Low-voltage differential signaling
MLB
MediaLB 150 peripheral
MMDC
Multi Mode DDR Controller
ODT
On-die termination
OTP
One-time programmable
PCB
Printed circuit board
PCIe
PCI Express
PCISig
Peripheral Component Interconnect Special Interest Group
PMIC
Power management integrated circuit
POR
Power-on reset
RAM
Random access memory
RGMII
Reduced Gigabit Media Independent Interface (Ethernet)
RMII
Reduced Media Independent Interface (Ethernet)
ROM
Read-only memory
SDMA
Smart Direct Memory Access Controller
UART
Universal asynchronous receiver/transmitter
USB
Universal Serial Bus
USB OTG
USB On-the-go
USB2.0
USB version 2.0 peripheral
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Acronyms and abbreviations
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Chapter 2
i.MX 6SoloX Design Checklist
2.1 Overview
This document provides a design checklist for the i.MX 6SoloX processor.
The design checklist tables contain recommendations for optimal design. Where
appropriate, the checklist tables also provide an explanation of the recommendation so
that users have a greater understanding of why certain techniques are recommended. All
supplemental tables referenced by the checklist appear in sections following the design
checklist tables.
2.2 Design Checklist Tables
Table 2-1. DDR recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. Connect ZQPAD to an external 240 Ω 1% resistor to This is a reference used during DRAM output buffer
driver calibration.
GND.
2. Connect DRAM_VREF to a source that is 50% of the
voltage value of NVCC_DRAM.
• The user may tie DDR_VREF to a precision
external resistor divider. Shunt DDR_VREF to
GND with a closely-mounted 0.1 μF capacitor.
See Table 2-14 for resistor values. Using
resistors with recommended tolerances ensures
the ±2% DDR_VREF tolerance per the DDR3
specification.
• The user can use a PMIC’s tracking regulator as
used on Freescale reference designs.
3. Connect DRAM_RESET to a 10 kΩ 5% pulldown
resistor to GND.
• DDR3: DRAM_RESET should be pulled down to
meet the JEDEC sequence until the controller is
configured and starts driving. DRAM_RESET
should be kept high when DDR3 enters selfrefresh mode.
• LPDDR2: DRAM_RESET should be left
unconnected.
Some Freescale reference designs use a 1% resistor
simply to consolidate the BOM.
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Design Checklist Tables
Table 2-1. DDR recommendations (continued)
DRAM_RESET is an active-low signal.
4 . DRAM_SDCKE0 and DRAM_SDCKE1 require
external pull-down resistors to GND for JEDEC
compliance when using LPDDR2.
5 . DRAM_SDCKE0 and DRAM_SDCKE1 require
external resistors (such as 10 kΩ) to GND to minimize
current drain during deep sleep mode (DSM).
• For LPDDR2: SDCKE[1:0] must be pulled down
to meet the JEDEC sequence until the controller
is configured and starts driving. Freescale
designs use 10 kΩ.
• For DDR3: SDCKE[1:0] pull-down is not required
to meet JEDEC.
The BSP (Board Support Package) uses a common
DDR routine for both fly-by and T-topology designs.
Fly-by designs have parallel resistor termination on
address lines, while T-topology does not.
During low-power self-refresh, the BSP programs pad
control register GRP_CTLDS to 0x00000000.
Therefore, DRAM_SDCKE0, DRAM_SDCKE1, and
other associated GRP_CTLDS I/O are forced to the
high-impedance state.
Because DRAM_SDCKE0 and DRAM_SDCKE1 are
forced to high-Z, external pull-down resistors are
required to avoid floating outputs during standby. In
Freescale designs, 10 kohm resistors are utilized for
this purpose. Any other termination on the
DRAM_SDCKE0 and DRAM_SDCKE1 lines (such as
50 ohms) should not be present; simulation should be
performed to ensure CKE signal integrity.
6. Make sure that the correct LPDDR2 function is
connected to the correct I/O. Note that this does not
necessarily correspond to the I/O name.
MMDC IO names are for the DDR3 default. When
LPDDR2 is selected, the I/O name (DDR3 MMDC PAD)
does not match with the LPDDR2 functionality. See the
“LPDDR2 and DDR3 pin mux mapping” table in the
“Multi Mode DDR Controller (MMDC)” chapter in your
chip reference manual.
Table 2-2. LCD1 recommendations for developer’s boot modes
Checkbox Recommendation
Explanation/supplemental recommendation
1. When LCD1 boot signals are used as the system’s
LCD1 signals, other functions, or GPIO outputs after
boot, use a passive resistor network to select the
desired boot mode for development boards.
Because only resistors are used, LCD1 bus loads can
cause current drain, leading to higher (false) supply
current measurements. Each LCD1 boot signal should
connect to a series resistor to isolate the bus from the
resistors and/or switchers; see Figure 2-1. Each
configured LCD1 boot signal sees either a 14.7 kΩ
pulldown or a 4.7 kΩ pullup. For each switch-enabled
pulled-up signal, the supply is presented with a 10 kΩ
current load.
An alternate approach using buffers is implemented in
the SABRE-SD development board design. Either of
these implementations is acceptable.
2. To reduce incorrect boot-up mode selections, do one Using LCD1 boot interface lines as inputs may result in
a wrong boot up due to the source overcoming the pull
of the following:
resistor value. A peripheral device may require the
• Use LCD1 boot interface lines only as processor
LCD1 signal to have an external or on-chip resistor to
outputs. Ensure LCD1 boot interface lines are not
minimize signal floating.
loaded down such that the level is interpreted as
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Chapter 2 i.MX 6SoloX Design Checklist
Table 2-2. LCD1 recommendations for developer’s boot modes (continued)
low during power-up, when the intent is to be a
high level, or vice versa.
• If an LCD1 boot signal must be configured as an
input, isolate the LCD1 signal from the target
driving source with one analog switch and apply
the logic value with a second analog switch.
Alternately, peripheral devices with three-state
outputs may be used; ensure the output is highimpedance during the boot up interval.
3. The BOOT_CFG signals are required for proper
functionality and operation and should not be left
floating
If the usage of the LCD1 boot signal affects the
peripheral device, then an analog switch, open collector
buffer, or equivalent should isolate the path. A pullup or
pulldown resistor at the peripheral device may be
required to maintain the desired logic level. Review the
switch or device data sheet for operating specifications.
See the “System Boot” chapter in your chip reference
manual for the correct boot configuration. Note that an
incorrect setting may result from an improper booting
sequence.
Table 2-3. Boot mode input recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. For BOOT_MODE1 and BOOT_MODE0, use one of Boot inputs BOOT_MODE1 and BOOT_MODE0 each
have on-chip pulldown devices with a nominal value of
the following options to achieve logic 0:
100 kΩ, a projected minimum of 60 kΩ, and a projected
• Tie to GND through any size external resistor
maximum of 140 kΩ.
• Tie directly to GND
Be aware that when these are logic high, current is
• Float
drawn from the VDD_SNVS supply. In production,
For logic 1, use one of the following:
when on-chip fuses determine the boot configuration,
both boot mode inputs can be no connects
• Tie directly to the VDD_SNVS_IN rail
• Tie to the VDD_SNVS_IN rail through an external
resistor 10 kΩ. A value of 4.7 kΩ is preferred in
high-noise environments.
If switch control is desired, no external pulldown
resistors are necessary. Simply connect SPST switches
directly to the VDD_SNVS_IN rail. If desired, a 4.7 kΩ
to 10 kΩ series resistor can be used when current drain
is critical.
Table 2-4. I2C recommendations
Checkbox Recommendation
1. Verify the target
Explanation/supplemental recommendation
I2C
interface clock rates.
The bus can only operate as fast as the slowest
peripheral on the bus. If faster operation is required,
move the slow devices to another I2C port.
2. Verify that the target I2C address range is supported These chips support up to four I2C ports.
and does no conflict with other peripherals. If there is
If it is undesirable to move a conflicting device to
another I2C port, review the peripheral operation to see
an unavoidable address conflict, move the offending
2
if it supports remapping the address.
device to another I C port.
3. Do not place more than one set of pullup resistors on This can result in excessive loading. Good design
practice is to place one pair of pullups only.
the I2C lines.
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Design Checklist Tables
Table 2-5. JTAG recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. Do not use external pullup or pulldown resistors on
JTAG_TDO.
JTAG_TDO is configured with an on-chip keeper circuit
such that the floating condition is actively eliminated if
an external pull resistor is not present. An external pull
resistor on JTAG_TDO is detrimental.
See Table 2-15 for a summary of the JTAG interface.
2. Ensure that the on-chip pullup/pulldown configuration External resistors can be used with all JTAG signals
except JTAG_TDO, but they are not required. See
is followed if external resistors are used with JTAG
Table 2-15 for a summary of the JTAG interface.
signals (with the exception of JTAG_TDO).
For example, do not use an external pulldown on an
input that has an on-chip pullup.
3. JTAG_MOD may be referred to as SJC_MOD in
When JTAG_MOD is low, the JTAG interface is
some documents. Both names refer to the same signal. configured for common software debug, adding all the
system TAPs to the chain.
JTAG_MOD should be externally connected to GND for
When JTAG_MOD is high, the JTAG interface is
normal operation in a system. Termination to GND
configured to a mode compliant with the IEEE 1149.1
through an external pulldown resistor is allowed. Use
standard.
£ 4.7 kΩ.
Table 2-6. Power supply decoupling recommendations1
Checkbox
Supply
VDD_ARM_IN
0.22 uF
(min qty)2
2
22 uF 3
4.7 uF
1
Notes
19x19 package: Place 22 μF cap and one of the
0.22uF caps next to the ball J21. Place "+" within 50
mils of via.
17x17WP package: Place 22 μF cap and one of the
0.22uF caps next to the ball H18. Place "+" within 50
mils of via.
17x17NP package: Place 22 μF cap and one of the
0.22uF caps next to the ball H18. Place "+" within 50
mils of via.
14x14 package: Place 22 μF cap and one of the
0.22uF caps next to the ball H18. Place "+" within 50
mils of via.
VDD_ARM_CAP
4
1
19x19 package: Place 22 μF cap and one of the
0.22uF caps next to the ball C18. Place "+" within 50
mils of via.
17x17WP package: Place 22 μF cap and one of the
0.22uF caps next to the ball C16. Place "+" within 50
mils of via.
17x17NP package: Place 22 μF cap and one of the
0.22uF caps next to the ball C16. Place "+" within 50
mils of via.
14x14 package: Place 22 μF cap and one of the
0.22uF caps next to the ball C16. Place "+" within 50
mils of via.
Do not connect any loads to VDDARM_CAP.
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Chapter 2 i.MX 6SoloX Design Checklist
Table 2-6. Power supply decoupling recommendations1 (continued)
Checkbox
Supply
VDD_SOC_IN
0.22 uF
(min qty)2
22 uF 3
4.7 uF
3
1
Notes
19x19 package: Place 22 μF cap and one of the
0.22uF caps next to the ball C9. Place "+" within 50
mils of via.
17x17WP package: Place 22 μF cap and one of the
0.22uF caps next to the ball C8. Place "+" within 50
mils of via.
17x17NP package: Place 22 μF cap and one of the
0.22uF caps next to the ball C8. Place "+" within 50
mils of via.
14x14 package: Place 22 μF cap and one of the
0.22uF caps next to the ball D8. Place "+" within 50
mils of via.
VDD_SOC_CAP
5
1
19x19 package: Place 22 μF cap and one of the
0.22uF caps next to the ball AA10. Place "+" within 50
mils of via.
17x17WP package: Place 22 μF cap and one of the
0.22uF caps next to the ball V8. Place "+" within 50
mils of via.
17x17NP package: Place 22 μF cap and one of the
0.22uF caps next to the ball V8. Place "+" within 50
mils of via.
14x14 package: Place 22 μFcap and one of the 0.22uF
caps next to the ball V8. Place "+" within 50 mils of via.
VDDSOC_CAP is restricted to MX6 loads.
VDD_HIGH_IN
1
1
VDD_HIGH_CAP
1
1
VDDHIGH_CAP is restricted to MX6 loads.
VDD_SNVS_IN
VDD_SNVS_CAP
1
If the nominal value is larger than recommended,
power-up/down ramp time is excessive and suspend/
resume operation cannot be guaranteed. Select a
small capacitor with low ESR.
Do not connect any loads to VDD_SNVS_CAP.
PCIE_VP or
PCIE_VPTX (19x19
package)
1
Place capacitors as close to the ball as possible.
PCIE_VP or
PCIE_VPTX (17x17
WP package)
1
Place capacitors as close to the ball as possible.
PCIE_VP_CAP
(17x17 NP
package)
1
Place capacitors as close to the ball as possible.
PCIE_VP_CAP
(14x14 package)
1
Place capacitors as close to the ball as possible.
NVCC_DRAM
4
1
Can be separated into four 4.7uF caps instead of
single 22 μF
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Design Checklist Tables
Table 2-6. Power supply decoupling recommendations1 (continued)
Checkbox
Supply
0.22 uF
(min qty)2
NVCC_PLL
1
NVCC_xxxx
1 per via
VDD_USB_CAP
1
4.7 uF
22 uF 3
1
Notes
Do not connect any loads to this LDO output.
One capacitor per via. Grouped NVCC balls can share
a capacitor.
2
May use a single 10 μF capacitor instead of 2 4.7 uF
capacitors.
Do not connect any loads to this LDO output.
USB_OTG1_VBUS 1
1
16V rated
USB_OTG2_VBUS 1
1
16V rated
NVCC_USB_H
(1.2V)
1
—
1
1. Use the smallest capacitor package size allowed with your design rules.
2. For 0.22 μF capacitors, use 0402 package.
3. For 22 μF capacitors, 0603 package preferred; 0805 and 1206 are acceptable.
Table 2-7. Power and decoupling recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1.Comply with the power-up sequence guidelines as
described in the data sheet to guarantee reliable
operation of the device.
Any deviation from these sequences may result in the
following situations:
2. Do not overload coin cell backup power rail
VDD_SNVS_IN. Note that the following I/Os are
associated with VDD_SNVS_IN; most inputs have onchip pull resistors and do not require external resistors:
Freescale PMIC PMPF0100 VSNVS regulator is rated
to supply 400 μA output current under worst-case
operating conditions. The VDD_SNVS_IN regulator can
supply larger current in transient situations without
damaging the regulator.
•
•
•
•
•
•
•
•
POR_B – on-chip pullup
ONOFF – on-chip pullup
BOOT_MODE0 – on-chip pulldown
BOOT_MODE1 – on-chip pulldown
TAMPER – on-chip pulldown
PMIC_STBY_REQ – push-pull output
PMIC_ON_REQ – push-pull output
TEST_MODE – on-chip pulldown
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case
scenario)
Concerning i.MX6:
• When VDD_SNVS_IN = VDD_HIGH_IN, SNVS
domain current is drawn from both equally.
• When VDD_HIGH_IN > VDD_SNVS_IN,
VDD_HIGH_IN supplies all SNVS domain current
and current flows into VDD_SNVS_IN to charge a
coin cell battery.
• When VDD_SNVS_IN > VDD_HIGH_IN,
VDD_SNVS_IN supplies current to SNVS, and
some current flows into VDD_HIGH_IN.
Note: VDD_HIGH_IN must be valid (above the internal
detector threshold, 2.4 V typ) for the current flow to
occur. Thus, current flow only happens when
VDD_HIGH_IN is powered to a level below
VDD_SNVS_IN. If VDD_HIGH_IN is off or low, no extra
current is drawn from VDD_SNVS_IN. The whole circuit
assumes it is charging a coin cell and starts charging
when VDD_HIGH_IN is valid. If you are driving
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Table 2-7. Power and decoupling recommendations (continued)
VDD_SNVS_IN with a non-battery power source, it
must be at the same level as VDD_HIGH_IN or current
will flow between them.
• When VDD_SNVS_IN is not powered by a
battery, it is recommended that VDD_SNVS_IN =
VDD_HIGH_IN. If VDD_SNVS_IN is tied to a
battery, the battery eventually discharges to a
value equal to that of VDD_HIGH_IN and never
subsequently charges above VDD_HIGH_IN.
The battery chemistry may add restrictions to
VDD_HIGH_IN’s voltage range. External charging
components should be based on the battery
manufacturer's specifications.
3. Maximum ripple voltage requirements.
Common requirement for ripple noise should be less
than 5% Vp-p of supply voltage average value.
Related power rails affected: all VDD_xxx_IN and
VDD_xxx_CAP.
4. NVCC_LVDS must be powered-on even when not
using the LVDS interface.
The DDR pre-drivers share the NVCC_LVDS power rail
with the LVDS interface. VDDHIGH_CAP can be
utilized as the power source; tie NVCC_LVDS to
VDDHIGH_CAP.
5. If VDD_SNVS_IN is directly supplied by a coin cell, a
schottky diode is required between VDD_HIGH_IN and
VDD_SNVS_IN. The cathode is connected to
VDD_SNVS_IN.
When no power is supplied to VDD_VSNVS_IN, the
diode limits the voltage difference between the two onchip SNVS power domains to approximately 0.3 V. The
processor is designed to allow current flow between the
two SNVS power domains proportional to the voltage
Alternately, VDD_HIGH_IN and VDD_SNVS_IN can be
difference.
tied together if the real-time clock function is not
needed during system power-down.
6 . If boundary scan test (BSDL) will be used, the
following supplies must be powered:
PCIE_VP, PCIE_VPH, PCIE_VPTX
The boundary scan test scan chain runs through the
PCIe PHY. If the PCIe PHY supplies are not powered,
the scan chain will not function.
The PCIE supply connections present depend on the
package.
PCIE_VP, PCIE_VPTX and PCIE_VP_CAP are
internally connected to the output of the LDO_PCIE.
LDO_PCIE must be enabled for boundary scan to
function. LDO_PCIE is enabled at reset.
PCIE_VPH is a supply input and must be powered for
boundary scan to function. On the 17x17 NP package,
PCIE_VPH is connected to VDD_HIGH_CAP inside the
package so it does not need to be supplied externally.
Table 2-8. Oscillator and clock recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. Precision 32.768 kHz oscillator
The capacitors implemented on either side of the
crystal are about twice the crystal load capacitance. To
hit the target oscillation frequency, board capacitors
need to be reduced to compensate for board and chip
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Design Checklist Tables
Table 2-8. Oscillator and clock recommendations (continued)
Connect a crystal between RTC_XTALI and
RTC_XTALO. Choose a crystal with a maximum of 100
kΩ ESR (equivalent series resistance) and follow the
manufacturer’s recommendation for loading
capacitance.
Do not use an external biasing resistor because the
bias circuit is on-chip.
parasitic capacitance; typically 15–16 pF is employed.
The integrated oscillation amplifier has an on-chip selfbiasing scheme, but is high-impedance (relatively
weak) to minimize power consumption. Care must be
taken to limit parasitic leakage from RTC_XTALI and
RTC_XTALO to either power or ground (> 100 MΩ) as
this negatively affects the amplifier bias and causes a
reduction of startup margin.
Use short traces between the crystal and the
processor, with a ground plane under the crystal, load
capacitors, and associated traces.
2. External kilohertz source
The voltage level of this driving clock should not exceed
the voltage of VDD_SNVS_CAP and the frequency
If feeding an external clock into the device, RTC_XTALI
should be <100 kHz under typical conditions. Do not
can be driven DC-coupled with RTC_XTALO floated or
exceed VDD_SNVS_CAP or damage/malfunction may
driven with a complimentary signal.
occur. The RTC_XTALI signal should not be driven if
the VDD_SNVS_CAP supply is off. This can lead to
damage or malfunction. For RTC_XTALI VIL and VIH
voltage levels, see the latest i.MX 6 series datasheet
available at www.freescale.com.
Note that if this external clock is stopped, the internal
ring oscillator starts automatically.
3. Loose-tolerance 40 kHz oscillator
When a high-accuracy real-time clock is not required,
the system may use the on-chip 40 kHz oscillator. The
An on-chip loose-tolerance ring oscillator is available of
tolerance is ± 50%.
approximately 40 kHz. If RTC_XTALI is tied to GND
The ring oscillator starts faster than an external crystal
and RTC_XTALO is floating, the on-chip oscillator is
and is used until the external crystal reaches stable
automatically engaged.
oscillation. The ring oscillator also starts automatically if
no clock is detected at RTC_XTALI at any time.
4. Precision 24 MHz oscillator
Connect a fundamental-mode crystal between XTALI
and XTALO. An 80 Ω typical ESR crystal rated for a
maximum drive level of 250 μW is acceptable.
Alternately, a 50 Ω typical ESR crystal rated for a
maximum drive level of 200 μW may be used. See the
engineering bulletin EB830 on www.freescale.com for
additional options.
5. External megahertz source
If feeding an external clock into the device, XTALI can
be driven DC-coupled with XTALO floated.
Freescale BSP software requires 24 MHz on this clock.
This clock is used as a reference for USB and PCIe, so
there are strict frequency tolerance and jitter
requirements. See Table 2-16 for guidelines. See the
crystal oscillator (XTALOSC) reference manual chapter
and relevant interface specification chapters for details.
To access a calculator for the 24 MHz crystal drive
level, see EB830 on the i.MX Community.
For XTALI VIL and VIH voltage levels, see the latest
i.MX 6 series datasheet. This clock is used as a
reference for USB and PCIe, so there are strict
frequency tolerance and jitter requirements. See Table
2-16 for guidelines. See the crystal oscillator
(XTALOSC) reference manual chapter and relevant
interface specification chapters for details.
6. CCM_LK1_P/ CCM_CLK1_N are LVDS input/output The clock inputs/outputs are general-purpose
differential pairs compatible with TIA/EIA-644 standard. differential high-speed clock Input/outputs.
The frequency range is 0 to 600 MHz.
Any or both of them can be configured:
Alternatively, a single-ended signal can be used to
• As inputs to feed external reference clocks to the
drive a CCM_CLKx_P input. In this case, the
corresponding CCM_CLKx_N input should be tied to a on-chip PLLs and/or modules, for example as alternate
reference clock for PCIe video/audio interfaces.
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Table 2-8. Oscillator and clock recommendations (continued)
constant voltage level equal to 50% of
VDD_HIGH_CAP. Termination should be provided with
high-frequency signals.
See the LVDS pad electrical specification in the data
sheet for further details.
• As outputs to be used as either a reference clock
or as a functional clock for peripherals, for
example an output of the PCIe master clock (root
complex use). See the chip reference manual for
details on the respective clock trees.
After initialization, the CCM_CLKx inputs/outputs can
be disabled (if not used) by the PMU_MISC1 register. If
unused, any or both of the CCM_CLKx_N/P pairs may
be left floating.
7. Bias XTALI with a 2.2 MΩ resistor to GND. Mount the The XTALI bias must be adjusted externally to ensure
reasonable start-up time.
resistor close to the XTALI ball.
Table 2-9. Reset and ONOFF recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. If the external SRC_POR_B signal is used to control
the processor POR, then SRC_POR_B must be
immediately asserted at power-up and remain asserted
until the VDD_ARM_CAP and VDD_SOC_CAP
supplies are stable. VDD_ARM_IN and VDD_SOC_IN
may be applied in either order with no restrictions. In
the absence of an external reset feeding the
SRC_POR_B input, the internal POR module takes
control.
A reset switch may be wired to the chip’s POR_B,
which is a cold-reset negative-logic input that resets all
modules and logic in the IC. POR_B may be used in
addition to internally generated power-on reset signal
(logical AND, both internal and external signals are
considered active low).
2. For portable applications, the ONOFF input may be
connected to an ON/OFF SPST push-button switch.
On-chip debouncing is provided, and this input has an
on-chip pullup. If not used, ONOFF should be a no
connect.
A brief connection to GND in OFF mode causes the
internal power management state machine to change
state to ON.
In ON mode, a brief connection to GND generates an
interrupt (intended to be a software-controllable powerdown).
An approximate 5 second or more connection to GND
causes a forced OFF.
Table 2-10. PCIe recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. Termination is required on the differential clock lines.
Connect two 49.9 Ω resistors, one between REFCLKand GND, the other between REFCLK+ and GND.
Alternately, Connect a 100 Ω resistor between
REFCLK- and REFCLK+.
These termination resistors should be placed as close
as possible to the receiver device inputs in case the
chip LVDS clock outputs are used as the REFCLK
source for the PCIe endpoint device.
2. The differential transmitter must be ac coupled. Use
a 0.1 μF-series capacitor on PCIE_TXP and a second
0.1 μF on PCIE_TXM.
To ensure PCIe specification compliance, ac coupling
is required at each transmitter. The receiver must be dc
coupled.
3. PCIe Jitter compliance
On previous i.MX6 SoCs, the on-chip PCIe clock
generation did not meet the jitter requirements of the
PCIe specification. This has not yet been evaluated on
the i.MX 6SoloX.
Freescale recommends including an external clock
source that meets the PCIe jitter specification until the
i.MX 6SoloX PCIe jitter compliance can be assessed.
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Bus isolation circuit
Table 2-11. USB recommendations
Checkbox Recommendation
1. USB OTG
Explanation/supplemental recommendation
The processor should turn VBUS on as required.
To comply with the USB OTG specification, the VBUS
supply on the OTG connector should default to off
when the boards power up.
2. USB Host
USB_H1_VBUS should be directly connected to a 5 V
supply.
Tie USB_H1_VBUS to an unswitched 5 V supply for the
typical use case. However, if the system is a USB
device, then USB_H1_VBUS may be a no connect.
3. USB HSIC supply
If USB_H_DATA and USB_H_STROBE are used as
GPIOs, they can be configured for voltages up to 2.5V
For USB, HSIC operation, the NVCC_USB_H supply
nominal (see the datasheet Operating Ranges table
should be configured for a nominal operating voltage of
details).
1.2V (see the datasheet Operating Ranges table
details).
Table 2-12. Reference resistor recommendations
Checkbox Recommendation
1. PCIE_REXT – Connect an external 200 Ω 1%
resistor to GND.
Explanation/supplemental recommendation
The impedance calibration process requires connection of this reference resistor. If PCIe is unused, the
reference resistor may be populated if desired for
manufacturability purposes, or left no-connect for cost
savings.
Table 2-13. Miscellaneous recommendations
Checkbox Recommendation
Explanation/supplemental recommendation
1. The TEST_MODE input is internally connected to an This input is reserved for Freescale manufacturing use.
on-chip pulldown device. The user can either float this
signal or tie it to GND.
2. For termination of unused analog interfaces, see
Table 2-17
—
3. GPANAIO must be a no connect.
This output is reserved for Freescale manufacturing
use.
4. NC contacts are no connect and should be floated.
Depending on the feature set, some versions of the IC
may have NC contacts connected inside the BGA.
2.3 Bus isolation circuit
The following figure provides supporting information for Table 2-2, recommendation #1.
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Chapter 2 i.MX 6SoloX Design Checklist
Figure 2-1. Boot configuration for development mode
2.4 DDR reference circuit
The following table is a resistor chart (see Table 2-1, recommendation #2). The
recommendations are appropriate for designs with DDR memory chips with a maximum
Vref input current of 2 μA each.
Table 2-14. DDR Vref resistor sizing guideline
Number of DRAM with 2 μA Vref input current
Resistor divider value (2 resistors)
2
≤ 1.21 kΩ 1%
2
≤ 1.54 kΩ 0.5%
2
≤ 2.32 kΩ 0.1%
2.5 JTAG signal termination
The following table is a JTAG termination chart (see recommendations in Table 2-5).
Table 2-15. JTAG interface summary
JTAG signal
I/O type
On-chip termination
External termination
JTAG_TCK
Input
47 kΩ pullup
Not required;
can use 10 kΩ pullup
JTAG_TMS
Input
47 kΩ pullup
Not required;
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Oscillator tolerance
Table 2-15. JTAG interface summary (continued)
can use 10 kΩ pullup
JTAG_TDI
Input
47 kΩ pullup
Not required;
can use 10 kΩ pullup
JTAG_TDO
3-state output
Keeper
Do not use pullup or pulldown
JTAG_TRSTB
Input
47 kΩ pullup
Not required;
can use 10 kΩ pullup
JTAG_MOD
Input
100 kΩ pullup
Use 1 kΩ pulldown or tie to
GND
2.6 Oscillator tolerance
The following table provides 24 MHz oscillator tolerance guidelines (see Table 2-8,
recommendations #4 and #5). Because these are guidelines, the designer must verify all
tolerances per the official specifications.
Table 2-16. 24 MHz crystal tolerance guidelines
Interface
Tolerance (± ppm)
Ethernet
50
USB2.0
150
PCIe
300
2.7 Unused analog interfaces
Table 2-17 shows the recommended connections for unused analog interfaces (see Table
2-13, recommendation #2).
Table 2-17. Recommended connections for unused analog interfaces
Module
Contact name
Recommendations if unused
ADC
ADC1_IN[3:0], ADC2_IN[3:0]
Float
ADC_VREFL
Ground
ADC_VREFH
Tie to VDDA_ADC_3P3
VDDA_ADC_3P3
VDDA_ADC_3P3 must be powered
even if the ADC is not used.
CCM
CCM_CLK1_P, CCM_CLK1_N,
CCM_CLK2
Float
LDB
LVDS_CLK_P, LVDS_CLK_N
LVDS_DATA0_P, LVDS0_DATA_N
Float
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Table 2-17. Recommended connections for unused analog interfaces (continued)
LVDS_DATA1_P, LVDS1_DATA_N
LVDS_DATA0_P, LVDS2_DATA_N
LVDS_DATA0_P, LVDS3_DATA_N
PCIe
PCIE_REXT, PCIE_RXM,
PCIE_RXP,PCIE_TXM, PCIE_TXP
Float
PCIE_VP, PCIE_VPTX, PCIE_VP_CAP 4.7 μF capacitor to ground1
RTC
USB OTG
PCIE_VPH
Float or ground 1
RTC_XTALI
Ground
RTC_XTALO
Float
USB_OTG1_CHD_B, USB_OTG1_DN,
USB_OTG1_DP, USB1_OTG_VBUS
Float
USB_OTG2_CHD_B, USB_OTG2_DN,
USB_OTG2_DP, USB2_OTG_VBUS
VADC
VADC_IN[3:0]
Ground
VDD_AFE_1P2
10 kΩ resistor to ground
VDDA_AFE_3P3
10 kΩ resistor to ground
VADC_AFE_BANDGAP
Float
1. These supplies must remain powered if boundary scan test needs to be done. Since the internal LDO_PCIE is enabled
after reset, the application may disable the LDO by setting the register field PMU_REG_CORE[REG1_TARG] = “0000”
(power gated off).
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Unused analog interfaces
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Chapter 3
i.MX 6 Series Layout Recommendations
3.1 Introduction
This chapter provides recommendations to assist design engineers with the layout of an
i.MX 6 series-based system.
3.2 Basic design recommendations
The i.MX 6SoloX processor comes in multiple packages. For detailed information, see
the i.MX 6.
When using the Allegro tool, optimal practice is to use the footprint as created by
Freescale. When not using the Allegro tool, use the Allegro footprint export feature
(supported by many tools). If export is not possible, create the footprint per the package
mechanical dimensions outlined in the product data sheet.
Native Allegro layout and gerber files are available on www.freescale.com.
3.2.1 Placing decoupling capacitors
Place small decoupling and larger bulk capacitors on the bottom side of the PCB.
The 0201 decoupling and 0603 bulk capacitors should be mounted as close as possible to
the power vias. The distance should be less than 50 mils. Additional bulk capacitors can
be placed near the edge of the BGA via array. Placing the decoupling capacitors close to
the power balls is critical to minimize inductance and ensure high-speed transient current
demand by the processor.
A correct via size is critical for preserving adequate routing space. The recommended
geometry for the via pads is: pad size 18 mils and drill 8 mils.
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Stackup recommendations
The following list provides the main recommendations for choosing the correct
decoupling scheme:
• Place the largest capacitance in the smallest package that budget and manufacturing
can support.
• For high speed bypassing, select the required capacitance with the smallest package
(for example, 0.22 μF and package 0201).
• Minimize trace length (inductance) to small caps.
• Series inductance cancels out capacitance.
• Tie caps to GND plane directly with a via.
• Place capacitors close to the power contact of the associate package designed from
the schematic.
A preferred BGA power decoupling design is the layout is available through
www.freescale.com. Customers should use the Freescale design strategy for power and
decoupling.
3.3 Stackup recommendations
High-speed design requires a good stackup in order have the right impedance for the
critical traces. The constraints for the trace width may depend on a number of factors,
such as the board stackup and associated dielectric and copper thickness, required
impedance, and required current (for power traces). The Freescale reference design uses a
minimum trace width of 3 mils for the DDR routing. The stackup also determines the
constraints for routing and spacing.
Consider the following when designing the stackup and selecting the material for your
board.
• Board stack-up is critical for high-speed signal quality.
• You must preplan impedance of critical traces
• High-speed signals must have reference planes on adjacent layers to minimize crosstalk.
• FSL reference design equals Isola 370HR.
• FSL validation boards equals Isola FR408.
The recommended stackup is 8-layers, with the layer stack as shown in the following
figure. The lefthand image shows the detail provided by Freescale inside the fabrication
detail as a part of the Gerber files. The righthand side shows the solution suggested by the
PCB fabrication company for our requirements.
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Chapter 3 i.MX 6 Series Layout Recommendations
Figure 3-1. Layer stack SABRE SD board
The following table shows a working stack-up implementation:
Table 3-1. Stackup implementation
Layers
Single ended
Trace
width
(Mils)
Differential
Impedance
(Ωs)
Trace
width
(Mils)
Trace
spacing
‘Airgap’
(Mils)
Impedance
(Ωs)
Trace
width
(Mils)
Trace
spacing
‘Airgap’
(Mils)
TOP
4.7
50
4.3
5.7
90
3.7
5.3
INT1
4.5
50
4.2
5.8
90
3.8
5.2
INT2
4.5
50
4.2
5.8
90
3.8
5.2
BOT
4.7
50
4.3
5.7
90
3.7
5.3
Impedance
(Ωs)
100
100
Figure 3-2. Example top layer impedance solution from PCB fabricator
3.4 DDR connection information
The following figures show the block diagrams from the reference design boards for the
DDR3 interface and the LPDDR2 interface (respectively) with the i.MX 6SX.
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DDR connection information
Figure 3-3. Connection between i.MX 6SX and LPDDR2
Figure 3-4. Connection between i.MX 6SX and DDR3
The DDR3 interface is one of the most critical interfaces for chip routing. It must have
the controlled impedance for the single ended traces be equal to 50 Ω and for the
differential pairs be equal to 100 Ω .
The following figure shows the physical connection scheme for both top and bottom
placement of the DDR chips, showing the final placement of the DDR3 memory and the
decoupling capacitors. The blue figure shows the top layer and the red figure shows the
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Chapter 3 i.MX 6 Series Layout Recommendations
bottom layer. It is very important to place the memory as close to the processor as
possible to reduce trace capacitance and keep the propagation delay to the minimum.
Follow the reference board layout as a guideline for memory placement and routing.
Figure 3-5. Final placement of memories and decoupling capacitors
3.4.1 DDR routing rules
DDR3 routing can be accomplished in two different ways: routing all signals at the same
length or routing by byte group.
Routing all signals at the same length can be more difficult at first because of the tight
space between the DDR and the processor and the large number of required
interconnects. However, it is the better way because it makes signal timing analysis
straightforward. Ideally, we could route all the signals at the same length. Nevertheless, it
could be difficult because of the large number of connections in the tight space between
the DDR and the processor. The following table explains the rules for routing the signals
by the same length.
Table 3-2. DDR3 routing by the same length Signals Total length Recommendations
Signals
Total length
Recommendations
Address and Bank
Clock length
Match the signals ±25 mils of the value
specified in the length column
Data and Buffer
Clock length
Match the signals ±25 mils of the value
specified in the length column
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DDR connection information
Table 3-2. DDR3 routing by the same length Signals Total length Recommendations
(continued)
Control signals
Clock length
Match the signals ±25 mils of the value
specified in the length column
Clock DRAM_SDCLK[1:0]
Longest trace ≤ 3 inches
Match the signals of clocks signals ±5
mils. Each differential clock pair
DRAM_SDQS[4:0] and
DRAM_SDQS[4:0]_B
Clock length
Match the signals of DQS signals
±10 mils of the value specified in the
length column.
Routing by byte group requires better control of the signals of each group. It is also more
difficult for analysis and constraint settings. However, its advantage is that the constraint
to match lengths can be applied to a smaller group of signals. This is often more
achievable once the constraints are properly set. The following table explains the rules for
routing the signals by byte group.
Table 3-3. DDR3 routing by byte group
Chip signals
DRAM_SDCLK[1:0]
DRAM_SDCLK_B[1:0]
Group
Clock
Length (mils)
Recommendations
Min
Max
Short as possible
2.25 inches
Match the signals ± 5
mils.
2.25 inches is
recommended.
DRAM_A[15:0]
DRAM_SDBA[2:0]
DRAM_RAS
DRAM_CAS
DRAM_SDWE
Address and Command Clock (min) – 200
Clock (min)1
Match the signals ± 25
mils.
DRAM_D[7:0]
DRAM_DQM0
DRAM_SDQS0
DRAM_SDQS0_B
Byte Group 1
—
Clock (min)
Match the signals of
each byte group ± 25
mils.
DRAM_D[15:8]
DRAM_DQM1
DRAM_SDQS1
DRAM_SDQS1_B
Byte Group 2
—
Clock (min)
DRAM_D[23:16]
DRAM_DQM2
DRAM_SDQS2
DRAM_SDQS2_B
Byte Group 3
—
Clock (min)
DRAM_D[31:24]
DRAM_DQM3
DRAM_SDQS3
DRAM_SDQS3_B
Byte Group 4
—
Clock (min)
DRAM_CS[1:0]
DRAM_SDCKE[1:0]
DRAM_SDODT[1:0]
Control signals
Clock (min) – 200
Clock (min)
Match the differential
signals of DQS ± 10
mils.
Match the signals ± 50
mils.
1. Clock (min) — The shortest length of the clock group signals because this group has a ± 5 mil matching tolerance.
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Chapter 3 i.MX 6 Series Layout Recommendations
Finally, the impedance for the signals should be 50 Ω for single ended and 100 Ω for
differential pairs.
3.5 Routing considerations
The chip can support up to 4 Gbytes of DRAM memory. i.MX 6SoloX DDR routing
needs to be separated into three groups: data, address, and control. Each group has its
own method of routing from an i.MX 6 series chip to DDR memory. The DDR layout has
2 Gbyte and 4 Gbyte options.
3.5.1 Swapping data lines
The DDR3 pin swapping technique for the data bus lines within bytes makes it easier to:
• Route direct lines
• Avoid changes between layers
The rules are as follows:
• Hardware write leveling – lowest order bit within byte lane must remain on lowest
order bit of lane by JEDEC compliance (see the ìWrite Levelingî section in
JESD79-3E)
• D0, D8, D16, and D24 are fixed
• Other data lines free to swap within byte lane
• JEDEC DDR3 memory restrictions are:
• No restrictions for complete byte lane swapping
• DQS and DQM must follow lanes
NOTE
If byte lane swapping was done, target DDR IC register read
value must be transposed according to the data line swapping.
3.5.2 DDR3 (32 bits) T topology considerations
Take into account the following when designing a T-topology system.
• Follow the routing rules described in Table 3-2.
• Termination resistors not required.
• Short routing lengths and on-chip drive strength control.
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Routing considerations
• Your design is limited to 4 DDR chips.
• DDR3, 2 GBytes using latest memories (4 GBytes coming).
3.5.3 DDR3 (32 bits) Fly-by topology considerations
Take in to account the following recommendations when designing a Fly-by topology
system
• DDR controller provides address mirroring when using two chip selects, which aids
address line routing for memories on both sides of board.
• Bus termination resistors are required.
3.5.4 2-Gigabyte recommendations: T topology
The 2 Gbyte option has two memories. You should follow these recommendations for
best practice:
• Have a balanced routing for the T connection.
• Avoid having many layer transitions.
• Do not cross split reference planes during the routing.
The following figure shows the topology for the ADDR/CMD/CTRL signals. It has a tree
topology. Note the balanced T routing.
Figure 3-6. ADDR/CMD/CTRL signal topology
The following figure shows the point-to-point data bus connection, with routing by byte
group.
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Figure 3-7. Point-to-point data bus connection (routing by byte group)
3.5.5 2-Gigabyte recommendations: Fly-by topology
The following diagrams show the 2 Gbyte recommendations using both chip selects
(CS[1:0]) and loading 1 GBytes to each one. This option has four memories and requires
the addition of a termination resistor.
NOTE
The fly-by examples in this guide can be used for either a one-chip select solution using
16 address traces or a two-chip select solution using only 15 address traces. The
unnecessary trace may simply be deleted from the design.
Route the ADDR/CMD signals as shown in the following figure:
Figure 3-8. ADDR/CMD/CTRL signal topology
Route the Byte lane signals as shown in the following figure:
Figure 3-9. Data bus routing topology
Route the Clock differential signals as shown in the following figure:
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Routing considerations
Figure 3-10. Clock routing topology
3.5.6 Two chip T topology routing examples
The figures in this section show examples for the routing of the 2GByte DDR3
memories. The following figures are a guideline of the T configuration routing with eight
layers PCB. The following table shows the color coding used in the figures.
Table 3-4. Color code
Color
Meaning
Green
ADD & CMD Signals
Yellow
Clocks
Pink
Data Byte Group 0
Purple
Data Byte Group 1
Blue
Data Byte Group 2
Brown
Data Byte Group 3
Gray
DDR_1V35 & DDR_VREF
Red
Control Signals
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Figure 3-11. Top layer T-topology DDR3 routing
Figure 3-12. Internal L3 T-topology DDR3 routing
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Routing considerations
Figure 3-13. Internal L5 T-topology DDR3 routing
Figure 3-14. Internal L10 T-topology DDR3 routing
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Chapter 3 i.MX 6 Series Layout Recommendations
Figure 3-15. Bottom layer T-topology DDR3 routing
The following table shows the total etch of the signals for the byte 0 and byte 1 groups.
The layout is an example, using 1790 mils for the clock.
Table 3-5. Total signal etch (DDR3)
Signals
Length (Mils)
DRAM_D0
668.879
DRAM_D1
669.081
DRAM_D2
668.418
DRAM_D3
669.224
DRAM_D4
667.319
DRAM_D5
669.851
DRAM_D6
667.602
DRAM_D7
668.021
DRAM_DQM0
669.672
DRAM_SDQS0
671.056
DRAM_SDQS0_B
671.493
DRAM_D8
677.254
DRAM_D9
675.478
DRAM_D10
675.902
DRAM_D11
677.141
DRAM_D12
677.912
DRAM_D13
679.458
DRAM_D14
677.199
Table continues on the next page...
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Routing considerations
Table 3-5. Total signal etch (DDR3) (continued)
DRAM_D15
679.199
DRAM_DQM1
678.342
DRAM_SDQS1
680.463
DRAM_SDQS1_B
680.649
DRAM_SDCLK0
1789.627
DRAM_SDCLK0_B
1789.648
3.5.7 Four chips fly-by topology routing examples
The figures in this section show examples for the routing of 2-Gbyte DDR memories.
These figures are a guideline of the routing by layer using the fly by configuration
topology. They use the same color code shown in Table 3-4.
Figure 3-16. Top fly-by DDR3 routing
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Figure 3-17. Internal L3 fly-by DDR3 routing
Figure 3-18. Internal L5 fly-by DDR3 routing
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Routing considerations
Figure 3-19. Internal L10 fly-by DDR3 routing
Figure 3-20. Internal L12 fly-by DDR3 routing
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Figure 3-21. Internal Bottom fly-by DDR3 routing
Table 3-6. Total signal etch fly-by DDR3
Signals
Length (Mils)
DRAM_D0
787.572
DRAM_D1
790.338
DRAM_D2
790.323
DRAM_D3
790.007
DRAM_D4
786.924
DRAM_D5
790.014
DRAM_D6
788.058
DRAM_D7
790.905
DRAM_DQM0
790.300
DRAM_SDQS0
786.391
DRAM_SDQS0_B
785.699
DRAM_D8
801.213
DRAM_D9
802.533
DRAM_D10
808.059
DRAM_D11
803.854
DRAM_D12
805.219
DRAM_D13
801.782
DRAM_D14
802.879
Table continues on the next page...
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Routing considerations
Table 3-6. Total signal etch fly-by DDR3 (continued)
DRAM_D15
801.067
DRAM_DQM1
804.210
DRAM_SDQS1
804.016
DRAM_SDQS1_B
803.209
DRAM_SDCLK0 (Byte0)
2779.48
DRAM_SDCLK0_B (Byte 0)
2759.761
DRAM_SDCLK0 (Byte1)
2105.156
DRAM_SDCLK0_B (Byte 1)
2083.168
3.5.8 High speed signal routing recommendations
The following list provides recommendations for routing traces for high speed signals.
Note that the propagation delay and the impedance control should match in order to have
the correct communication with the devices.
• High-speed signals (DDR, RGMII, display) must not cross gaps in the reference
plane.
• Avoid creating slots, voids, and splits in reference planes. Review via voids to ensure
they do not create splits (space out vias).
• Provide ground return vias within 100 mils distance from signal layer-transition vias
when transitioning between different reference ground planes.
• A solid GND plane must be directly under crystal, associated components, and
traces.
• Clocks or strobes that are on the same layer need at least 2.5× spacing from an
adjacent trace (2.5× height from reference plane) to reduce cross-talk.
• All synchronous modules should have bus length matching and relative clock length
control. For SD module interfaces:
• Match data and CMD trace lengths (length delta depends on bus rates)
• CLK should be longer than the longest signal in the Data/CMD group (+5 mils)
• Similar DDR rules must be followed for data, address and control as for SD
module interfaces.
3.5.9 Ground plane recommendations
This section provides examples of good practices and how to avoid common user
mistakes when flowing the ground planes layers.
The following two figures show common examples of poor GND planes.
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Figure 3-22. Poor GND plane 1
Figure 3-23. Poor GND plane 2
Spacing the vias some mils apart facilitates the GND copper flowing in the plane. The
following figures show good practices of ground planes.
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DDR power recommendations
Figure 3-24. Good layout GND plane detail
Figure 3-25. Good layout GND plane detail
3.6 DDR power recommendations
The following recommendations apply to the VREF (P0V675_REFDDR) voltage
reference plane.
• Use 30 mils trace between decoupling cap and destination.
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• Maintain a 25 mils clearance from other nets.
• Isolate VREF and/or shield with ground.
Decouple using distributed 0.22 μF capacitors by the regulator, controller, and
devices.
• Place one 1.0 μF near the source of VREF: one near the VREF pin on the controller
and two between the controller and the devices.
The following recommendations apply to the VTT (DDR_VTT) voltage reference
plane. The figures are examples from the evaluation board for the VTT reference
schematic.
• Place the VTT island on the component side layer at the end of the bus behind the
DRAM devices.
• Use a wide-island trace for current capacity.
• Place the VTT generator as close to termination resistors as possible to minimize
impedance (inductance).
• Place one or two 0.1 μF decoupling capacitors by each termination RPACK on the
VTT island to minimize the noise on VTT. Other bulk (10–22 pF) decoupling is also
recommended to be placed on the VTT island.
Figure 3-26. DDR_VTT validation board example
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PCI Express interface recommendations
Figure 3-27. DDR_VTT validation board examples
3.7 PCI Express interface recommendations
This chip provides a ×1 PCIe lane. The PCIe module supports PCI Express Gen 2.0
interfaces at 5 Gb/s. It is also backwards compatible to Gen 1.1 interfaces at 2.5 Gb/s.
NOTE
Lane ×1 is composed of two differential signals pairs: one TXD signal pair and one RXD
signal pair.
Table 3-7. PCI Express signal descriptions
Signal name
Signal group
Description
PCIE_TXP, PCIE_TXM
Data
PCI Express transmit differential pair
PCIE_RXP, PCIE_RXM
Data
PCI Express receive differential pair
3.7.1 PCI Express general routing guidelines
Use the following recommendations for PCI Express general routing:
• The trace width and spacing of the lanes ×1 signals should be such that the
differential impedance is 85 Ω ± 10%.
• The PCIE_REXT contacts should be connected to a 200 Ω 1% resistor to ground.
The trace length between the pin and the resistor should be minimized. The resistor
value is defined within the data sheet and should determine the exact resistor value.
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• Route traces over continuous planes (power and ground).
• They should not pass over any power/GND plane slots or anti-etch.
• When placing connectors, make sure the ground plane clear-outs around each pin
have ground continuity between all pins.
• Maintain the parallelism (skew matched) between DP and DM, and match overall
differential length difference to less than 5 mils.
• Maintain symmetric routing for each differential pair.
• Do not route DP and DM traces under oscillators or parallel to clock traces and/or
data buses.
• Minimize the lengths of high speed signals that run parallel to the DP and DM pair.
• Keep DP and DM traces as short as possible.
• Route DP and DM signals with a minimum amount of corners. Use 45-degree turns
instead of 90-degree turns.
• Avoid layer changes (vias) on DP and DM signals. Do not create stubs or branches.
• Provide ground return vias within 50 mils distance from signal layer-transition vias
when transitioning between different reference ground planes.
3.7.1.1 PCI Express coupling lane
Based on our development design, we have the following coupling signal schema.
Consult the PCISig documentation for detailed information.
• DC-coupled Rx signals with 0 Ω resistors
• AC-coupled Tx signals with 0.1µF capacitors
3.7.1.2 Additional resources for PCI Express signal routing
recommendations
For more information about, PCI Express signal routing recommendations, see the
following.
• Freescale Hardware Design Considerations for PCI Express® and SGMII (http://
www.freescale.com/files/training_presentation/
TP_HARDWARE_DESIGN_PCI_SMGIII.pdf)
• PCISig, PCI Express Base Specification.
• PCISig, PCI Express Card Electromechanical Specification.
• PCISig, PCSIG Board Design Guidelines for PCI Express™ Architecture.
• PCI Express Basics: Developing Physical Design Rules for PCIe (http://
www.mentor.com/products/pcb-system-design/multimedia/pcie-basics-webinar )
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PCI Express interface recommendations
3.7.2 LVDS recommendations
Use the following recommendations for the LVDS.
• Follow standard high-speed differential routing rules for signal integrity.
• Each differential pair should be length matched to ± 5 mils.
• LVDS differential pairs should have a differential impedance of 100 Ω.
3.7.3 USB recommendations
Use the following recommendations for the USB.
• Route the high speed clocks and the DP and DM differential pair first.
• Route DP and DM signals on the top or bottom layer of the board
• The trace width and spacing of the DP and DM signals should meet the differential
impedance requirement of 90 Ω .
• Route traces over continuous planes (power and ground).
• They should not pass over any power/GND plane slots or anti-etch.
• When placing connectors, make sure the ground plane clearouts around each pin
have ground continuity between all pins.
• Maintain the parallelism (skew matched) between DP and DM, and match overall
differential length difference to less than 5 mils.
• Maintain symmetric routing for each differential pair.
• Do not route DP and DM traces under oscillators or parallel to clock traces and/or
data buses.
• Minimize the lengths of high speed signals that run parallel to the DP and DM pair.
• Keep DP and DM traces as short as possible.
• Route DP and DM signals with a minimum amount of corners. Use 45-degree turns
instead of 90-degree turns.
• Avoid layer changes (vias) on DP and DM signals. Do not create stubs or branches.
• Provide ground return vias within 50 mils distance from signal layer-transition vias
when transitioning between different reference ground planes.
3.7.4 Impedance signal recommendations
Use the following table as a reference when you are updating or creating constraints in
your software PCB tool to set up the impedance and the correct trace width.
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Table 3-8. Impedance signal recommendations
Signal Group
Impedance
Layout Tolerance (±)
All signals, unless specified
50 Ω SE
10%
PCIe Diff signals
85 Ω Diff
10%
USB Diff signals
90 Ω Diff
10%
Diff signals:
100 Ω Diff
10%
LVDS, DDR, Phy IC to Ethernet
Connector
The following figure shows the dimensions of a stripline and microstrip pair. Figure 3-29
shows the differential pair routing.
Figure 3-28. Microstrip and stripline differential pair dimensions
Figure 3-29. Differential pair routing
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PCI Express interface recommendations
• The space between two adjacent differential pairs should be greater than or equal to
twice the space between the two individual conductors.
• The skew between LVDS pairs should be within the minimum recommendation (±
100 mil).
3.7.5 Reference resistors
NOTE
The reference resistor and the connection should be placed
away from noisy regions. Noise induced on it may impact the
internal circuit and degrade the interface signals.
3.7.6 ESD and radiated emissions recommendations
The PCB design should use six or more layers, with solid power and ground planes. The
recommendations for ESD immunity and radiated emissions performance are as follows:
• All components with ground chassis shields (USB jack, buttons, and so forth) should
connect the shield to the PCB chassis ground ring.
• Ferrite beads should be placed on each signal line connecting to an external cable.
These ferrite beads must be placed as close to the PCB jack as possible.
NOTE
Ferrite beads should have a minimum impedance of 500 Ω
at 100 MHz with the exception of the ferrite on USB_5V.
• Ferrite beads should NOT be placed on the USB D+/D– signal lines as this can cause
USB signal integrity problems. For radiated emissions problems due to USB, a
common mode choke may be placed on the D+/D– signal lines. However, in most
cases, it should not be required if the PCB layout is satisfactory. Ideally, the common
mode choke should be approved for high speed USB use or tested thoroughly to
verify there are no signal integrity issues created.
• It is highly recommended that ESD protection devices be used on ports connecting to
external connectors. See the reference schematic (available at www.freescale.com)
for detailed information about ESD protection implementation on the USB
interfaces.
• If possible, stitch all around the board with vias with 100 mils spacing between them
connected to GND planes with exposed solder mask to improve EMI.
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3.7.7 Component placement recommendations
Adhere to the following recommendations when placing components.
• Place components such that short and/or critical routes can be easily laid out.
• Critical routes determine component location.
• Orient devices to facilitate routes (minimize length and crossovers).
• Consider placing the following pairings adjacent.
• i.MX and DDR
• PHY and associated jack
• Jack and CODEC input
• Bluetooth® (or other RF) and antenna
3.7.8 Reducing skew and phase problems in deferential pairs
traces
Differential pair technology has evolved to require more stringent checking in the area of
phase control. This is evident on the higher data rates associated with parallel buses such
as PCI Gen 2, DDR, LVDS, or Ethernet. In the simplest of terms, Diff Pair technology
sends opposite and equal signals down a pair of traces. Keeping these opposite signals in
phase is essential to assuring that they function as intended.
Figure 3-30 and Figure 3-31 show two examples of static routing where a match is
achieved without needing to tune one element of the differential pair.
Figure 3-30. Yellow traces diff pairs 1
The following figure shows the addition of a delay trace to one element of the differential
pair to avoid length mismatch (which reduces skew and phase problems). The green box
marks the detail.
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Figure 3-31. Small bumps added to the shorter differential pair
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Chapter 4
Avoiding Board Bring-up Problems
4.1 Introduction
This chapter provides recommendations for avoiding typical mistakes when bringing up a
board for the first time. These recommendations consist of basic techniques that have
proven useful in the past for detecting board issues and addressing the three most typical
bring-up pitfalls: power, clocks, and reset. A sample bring-up checklist is provided at the
end of the chapter.
4.2 Using a current monitor to avoid power pitfalls
Excessive current can cause damage to the board. Avoid this problem by using a currentlimiting laboratory supply set to the expected typical main current draw (at most).
Monitor the main supply current with an ammeter when powering up the board for the
first time. You can use the supply's internal ammeter if it has one. By monitoring the
main supply current and controlling the current limit, any excessive current can usually
be detected before permanent damage occurs.
4.3 Using a voltage report to avoid power pitfalls
Using incorrect voltage rails is a common power pitfall. To help avoid this mistake,
create a basic table called a voltage report prior to bringing up your board. This table
helps validate that all the supplies are reaching the expected levels.
To create a voltage report, list the following:
• Your board voltage sources
• Default power-up values for the board voltage sources
• Best location on the board to measure the voltage level of each supply
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Checking for clock pitfalls
Carefully determine the best measurement location for each power supply to avoid a
large voltage drop (IR drop) on the board, which causes inaccurate current values to be
measured. The following guidelines help produce the best current measurements:
• Measure closest to the load (in this case the i.MX6 processor).
• Make two measurements: the first after initial board power-up and the second while
running a heavy use-case that stresses the i.MX6 processor.
Ensure that the supplies that are powering the i.MX6 meet the DC electrical
specifications as listed in your chip-specific data sheet.
The shaded cells in the PMIC LDO2 row call your attention to the difference in the
expected value and measured value, which indicates a potential problem with that power
rail.
Table 4-1. Sample voltage report
Source
Net name
Expected (V)
Measured (V)
Measured point
Comment
Main
5V0
5.0
5.103
C5.1
—
3.3 V discrete reg
3V3_DELAYED
3.35
3.334
SH1
Requires LDO3 to
enable
PMIC Switcher 1
VDDARM
1.375
1.377
SH2
—
PMIC Switcher 2
VDDSOC
1.375
1.376
SH3
—
PMIC Switcher 3
1V5_DDR
1.5
1.501
SH4
—
PMIC LDO1
1V8
1.8
1.802
TP9
—
PMIC LDO2
2V5
2.5
0.3
TP5
—
VREFDDR
0V75_REFDDR
0.75
0.751
C8.1
50% of 1V5_DDR
Coin Cell
3V0_STBY
3.0
3.006
TP1
—
i.MX6
VDDARM_CAP
1.1
1.114
C6.1
—
i.MX6
VDDHIGH_CAP
2.5
2.515
SH5
—
i.MX6
VDDSNVS_CAP
1.0
1.016
TP2
—
4.4 Checking for clock pitfalls
Problems with the external clocks are another common source of board bring-up issues.
Ensure that all of your clock sources are running as expected.
The XTALI/XTALO and the RTC_XTALI/RTC_XTALO clocks are the main clock
sources for 24 MHz and 32 kHz reference clocks respectively on the i.MX6. Although
not required, the use of low jitter external oscillators to feed CLK1_P/N or CLK2 on the
i.MX6 can be an advantage if low jitter or special frequency clock sources are required
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Chapter 4 Avoiding Board Bring-up Problems
by modules driven by CLK1_P/N or CLK2. See the CCM chapter in your i.MX6 chip
reference manual for details. If a 32.768 kHz crystal is not connected to the i.MX6, an
on-chip ring oscillator is automatically used for the low-frequency clock source.
When checking crystal frequencies, use an active probe to avoid excessive loading. A
parasitic probe typically inhibits the 32.768 kHz and 24 MHz oscillators from starting up.
Use the following guidelines:
• RTC_XTALI clock is running at 32.768 kHz (can be generated internally or applied
externally).
• XTALI/XTALO is running at 24 MHz (used for the PLL reference).
• CLK1_P/N/CLK2 can be used as oscillator inputs for low jitter special frequency
sources.
• CLK1_P/N and CLK2 are optional.
In addition to probing the external input clocks, you can check internal clocks by
outputting them at the debug signals CLKO1 and CLKO2 (iomuxed signals). See the
CCM chapter in the chip reference manual for more details about which clock sources
can be output to those debug signals.
4.5 Avoiding reset pitfalls
Follow these guidelines to ensure that you are booting using the correct boot mode.
• During initial power on while asserting the POR_B reset signal, ensure that 24 MHz
clock is active before releasing POR_B.
• Follow the recommended power-up sequence specified in the i.MX6 data sheet.
• Ensure the POR_B signal remains asserted (low) until all voltage rails associated
with bootup are on.
The GPIOs and internal fuses control how the i.MX6 boots. For a more detailed
description about the different boot modes, see the system boot chapter of the chip
reference manual.
4.6 Sample board bring-up checklist
Note that the checklist incorporates the recommendations described in the previous
sections. Blank cells should be filled in during bring-up as appropriate.
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Sample board bring-up checklist
Table 4-2. Board bring-up checklist
Checklist Item
Details
Owner
Findings
& status
Note: The following items must be completed serially.
1. Perform a visual inspection.
Check major components to make sure nothing has been
misplaced or rotated before applying power.
2. Verify all i.MX6 voltage rails.
Confirm that the voltages match the data sheet’s
requirements. Be sure to check voltages not only at the
voltage source, but also as close to the i.MX6 as possible
(like on a bypass capacitor). This reveals any IR drops on the
board that will cause issues later.
Ideally all of the i.MX6 voltage rails should be checked, but
VDD_ARM_IN and VDD_SOC_IN are particularly important
voltages. These are the core logic voltages and must fall
within the parameters provided in the i.MX6 data sheet.
VDD_SNVS_IN, NVCC_JTAG, and NVCC_DRAM are also
critical to the i.MX6 boot up.
Note: NVCC_LVDS2V5 must be powered when using the
chip DDR interface. This power input is used as the PreDriver power source for the DDR I/O pads.
3. Verify power-up sequence.
Verify that power on reset (POR_B) is de-asserted (high) after
all power rails have come up and are stable. See the i.MX6
data sheet for details about power-up sequencing.
4. Measure/probe input clocks (32
kHz, 24MHz, others).
Without a properly running clock, the i.MX6 will not function
properly.
5. Check JTAG connectivity
This is one of the most fundamental and basic access points
to the i.MX6 to allow the debug and execution of low level
code.
Note: The following items may be worked on in parallel with other bring up tasks.
Access internal RAM.
Verify basic operation of the i.MX6 in system. Perform a basic
test by performing a write-read-verify to the internal RAM. No
software initialization is necessary to access internal RAM.
Verify CLKO outputs (measure and
verify default clock frequencies for
desired clock output options) if the
board design supports probing of the
CLKO pin.
This ensures that the corresponding clock is working and that
the PLLs are working.
Measure boot mode frequencies.
Set the boot mode switch for each
boot mode and measure the
following (depending on system
availability):
This verifies the specified signals’ connectivity between the
i.MX6 and boot device and that the boot mode signals are
properly set.
Note that this step requires chip initialization, for example via
the JTAG debugger, to properly set up the IOMUX to output
CLKO and to set up the clock control module to output the
desired clock. See the reference manual for more details.
See the “System Boot” chapter in the reference manual for
details about configuring the various boot modes.
• NAND (probe CE to verify
boot, measure RE frequency)
• SPI-NOR (probe slave select
and measure clock frequency)
• MMC/SD (measure clock
frequency)
Table continues on the next page...
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Chapter 4 Avoiding Board Bring-up Problems
Table 4-2. Board bring-up checklist (continued)
Run basic DDR initialization and test
memory.
1. Assuming the use of a JTAG debugger, run the DDR
initialization and open a debugger memory window
pointing to the DDR memory map starting address.
2. Try writing a few words and verify if they can be read
correctly.
3. If not, recheck the DDR initialization sequence and
whether the DDR has been correctly soldered onto the
board.
It is also recommended that users recheck the schematic to
ensure that the DDR memory has been connected to the
i.MX6 correctly.
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Sample board bring-up checklist
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Chapter 5
Understanding the IBIS Model
5.1 Overview
This chapter explains how to use the IBIS (input output buffer information specification)
model, which is an Electronic Industries Alliance standard for the electronic behavioral
specifications of integrated circuit input/output analog characteristics. The model is
generated in ASCII text format and consists of multiple tables that capture current vs.
voltage (IV) and voltage vs. time (VT) characteristics of each buffer. IBIS models are
generally used to perform PCB-board-level signal integrity (SI) simulations and timing
analyses.
The IBIS model’s features are as follows:
• Supports fast chip-package-board simulation, with SPICE-level accuracy and faster
than any transistor-level model
• Provides the following for portable model data
• I/O buffers, series elements, terminators
• Package RLC parasitics
• Electrical board description
5.2 IBIS structure and content
An IBIS file contains the data required to model a component’s input, output, and I/O
buffers behaviorally in ASCII format. The basic IBIS file contains the following data:
• Header information regarding the model file
• Information about the component, the package’s electrical characteristics, and the
pin-to-buffer model mapping (in other words, which pins are connected to which
buffer models)
• The data required to model each unique input, output, and I/O buffer design on the
component
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Header Information
IBIS models are component-centric, meaning they allow users to model an entire
component rather than only a particular buffer. Therefore, in addition to the electrical
characteristics of a component’s buffers, an IBIS file includes the component’s pin-tobuffer mapping and the electrical parameters of the component’s package.
5.3 Header Information
The first section of an IBIS file provides the basic information about the file and its data.
The following table explains the header information notation.
Table 5-1. Header Information
Keyword
Required
Description
[IBIS Ver]
Yes
Version of IBIS Specification this file
uses.
[Comment char]
No
Change the comment character.
Defaults to the pipe (|) character
[File Name]
Yes
Name of this file. All file names must be
lower case. The file name extension for
an IBIS file is .ibs
[File Rev]
Yes
The revision level of this file. The
specification contains guidelines for
assigning revision levels.
[Date]
No
Date this file was created
[Source]
No
The source of the data in this file. Data is
taken from a simulation and validated on
the board.
[Notes]
No
Component or file-specific notes.
[Disclaimer]
No
May be legally required
[Copyright]
No
The file’s copyright notice
Header Information
[IBIS Ver] 4.2
[Comment Char] |_char
[File Name] mx6sx_bga19x19_consmr.ibs [File Rev] 20140807
[Date] Fri Aug 8 09:44:31 2014
[Source] FSL Viper 2014.01.29 [Notes]
5.4 Component and pin information
The second section of an IBIS file is where the data book information regarding the
component’s pinout, pin-to-buffer mapping, and the package and pin electrical
parameters is placed.
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Chapter 5 Understanding the IBIS Model
Table 5-2. Component and Pin Information
Keyword
Required
Comment
[Component]
Yes
The name of the component being
modeled. Standard practice has been to
use the industry standard part
designation. Note that IBIS files may
contain multiple [Component]
descriptions.
[Manufacturer]
Yes
The name of the component
manufacturer
[Package]
Yes
This keyword contains the range
(minimum, typical and maximum values)
over which the packages’ lead
resistance, inductance, and capacitance
vary (the R_pkg, L_pkg, and C_pkg
parameters).
[Pin]
Yes
This keyword contains the pin-to-buffer
mapping information. In addition, the
model creator can use this keyword to
list the package information: R, L, and C
data for each individual pin (R_pin,
L_pin, and C_pin parameters).
[Package Model]
No
If the component model includes an
external package model (or uses the
[Define Package Model] keyword within
the IBIS file itself), this keyword indicates
the name of that package model.
[Pin Mapping]
No
This keyword is used if the model
creator wishes to include information on
buffer power and ground connections.
This information may be used for
simulations involving multiple outputs
switching.
[Diff Pin]
No
This keyword is used to associate
buffers that should be driven in a
complementary fashion as a differential
pair.
[Model Selector]
This keyword provides a simple means
by which several buffers can be made
optionally available for simulation at the
same physical pin of the component.
Component and pin information
[Component]
mx6sx_bga19x19
[Manufacturer]
FREESCALE
[Package]
| variable
typ
min
max
R_pkg
0.2839146
0.0091798
0.575946
L_pkg
3.33311nH
0.16746nH
7.75079nH
C_pkg
24.5630pF
1.13795pF
356.1pF
|
[Pin] signal_name
model_name
R_pin
L_pin
C_pin
A1
VSS
GND
NA
NA
NA
A2
DRAM_SDQS3_N
ddr
0.473559
5.48846nH 1.36964pF
A3
DRAM_SDQS3_P
ddr
0.478764
5.40998nH 1.61263pF
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Model information
|
[Pin Mapping]
pulldown_ref
pullup_ref
A1
VSS
NC
A2
NC
NC
…
|
[Diff Pin]
inv_pin
vdiff
tdelay_typ tdelay_min tdelay_max
A3
A2
NA
NA
NA
NA
H1
H2
NA
NA
NA
NA
M2
M1
NA
NA
NA
NA
T1
U1
NA
NA
NA
NA
AB2
AC2
NA
NA
NA
NA
|
|****************************************************************
|*
Model Selector
*
|****************************************************************
|
[Model Selector] ddr
ddr3_sel11_ds111_mio
DDR, 1.5V, ddr3 mode, 34 Ohm driver impedance
ddr3_sel11_ds110_mio
DDR, 1.5V, ddr3 mode, 40 Ohm driver impedance
5.5 Model information
The [Model] keyword starts the description of the data for a particular buffer.
Table 5-3. Model information
Keyword
Comment
[Model Spec]
General set of parameters for the model simulation.
[Receiver Thresholds]
Threshold information for the different simulation cases.
[Temperature Range]
The temperature range over which the min, typ and max IV
and switching data have been gathered.
[Voltage Range]
The range over which Vcc is varied to obtain the min, typ and
max pullup and power clamp data.
[Pulldown] [Pullup] [GND_clamp] [POWER_clamp]
IV information. For more details, see “IV information”.
[Ramp] [Rising Waveform] [Falling Waveform]
VT information. For more details, see “VT information”.
[Test Data] [Rising Waveform Near] [Rising Waveform Far]
[Falling Waveform Near] [Falling Waveform Far]
VT golden model information. For more details, see “Golden
Model VT information”.
[Test Load]
5.5.1 IV information
IV information is composed of four Current-over-Voltage tables: [Pullup], [Pulldown],
[GND_clamp], and [Power_clamp]. Each look-up table describes a different part of the
IO cell model.
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Chapter 5 Understanding the IBIS Model
Figure 5-1. Model IV parameters’ structure
5.5.2 VT information
Table 5-4. Ramp and waveform keywords
Keyword
Required
Comment
[Ramp]
Yes
Basic ramp rate information, given as a
dV/dt_r for rising edges and dV/dt_f for
falling edges, see the following equation.
20% to 80% voltage swing
dV
=
time taken to swing above voltage
dt
Note: The dV value is the 20% to 80%
voltage swing of the buffer when driving
into the specified load, R_load (for
[Ramp], this load defaults to 50). For
CMOS drivers or I/O buffers, this load is
assumed to be connected to the
voltages defined by the [Voltage Range]
keyword for falling edges and to ground
for rising edges.
[Rising Waveform]
No
The actual rising (low to high transition)
waveform, provided as a VT table.
[Falling Waveform]
No
The actual falling (high to low transition)
waveform, provided as a VT table.
Table 5-5. Ramp and waveform keywords example
[Ramp]
| variable typ
min
max
dV/dt_r 0.4627/0.3456n
0.4326/0.4568n
0.4962/0.3030n
dV/dt_f 0.4546/0.3481n
0.4272/0.3918n
0.4774/0.3569n
Table continues on the next page...
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Model information
Table 5-5. Ramp and waveform keywords example (continued)
R_load = 0.2400k
|
[Rising Waveform]
R_fixture= 0.2400k
V_fixture= 0.0
V_fixture_min= 0.0
V_fixture_max= 0.0
|time V(typ)
V(min)
V(max)
|0.0S 0.3369uV
12.4052uV
41.7335nV
|19.7866fS 0.6730uV
12.7375uV
0.3823uV
|20.8863fS 0.6917uV
12.7519uV
0.4013uV
|21.9489fS 0.7058uV
12.7657uV
0.4196uV
V(min)
V(max)
|0.0S 0.7711V
0.7211V
0.8270V
|0.3334nS 0.7711V
0.7211V
0.8270V
|0.3445nS 0.7711V
0.7211V
0.8269V
|
...
|
[Falling Waveform]
R_fixture= 0.2400k
V_fixture= 0.0
V_fixture_min= 0.0
V_fixture_max= 0.0
|time V(typ)
|
...
The [Ramp] keyword is always required, even if the [Rising Waveform] and [Falling
Waveform] keywords are used. However, the VT tables under [Rising Waveform] and
[Falling Waveform] are generally preferred to [Ramp] for the following reasons:
• VT data may be provided under a variety of loads and termination voltages
• VT tables may be used to describe transition data for devices as they turn on and turn
off.
• [Ramp] effectively averages the transitions of the device, without providing any
details on the shapes of the transitions themselves. All detail of the transition ledges
would be lost.
The VT data should be included under two [Rising Waveform] and two [Falling
Waveform] sections, each containing data tables for a Vcc-connected load and a Groundconnected load (although other loading combinations are permitted).
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Chapter 5 Understanding the IBIS Model
The most appropriate load is a resistive value corresponding to the impedance of the
system transmission lines the buffer will drive (own impedance). For example, a buffer
intended for use in a 60 Ω system is best modeled using a 60 Ω load (R_fixture).
Figure 5-2. Model data interpretation
5.5.3 Golden Model VT information
Golden waveforms are a set of waveforms simulated using known ideal test loads. They
are useful for verifying the accuracy of behavioral simulation results against the transistor
level circuit model from which the IBIS model parameters originated.
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Model information
Figure 5-3. Generic test load network
Table 5-6. Golden waveform keywords
Keyword
Required
[Test Data]
No
[Rising Waveform Near] [Rising
Yes
Waveform Far] [Falling Waveform Near]
[Falling Waveform Far]
[Test Load]
Yes
Comment
• Provides a set of golden
waveforms and references the
conditions under which they were
derived.
• Useful for verifying the accuracy of
behavioral simulation results
against the transistor level circuit
model from which the IBIS model
parameters originated.
Current-Over-Voltage tables, for far and
near portions of the golden model as
described by Figure 5-3.
• Defines a test load network and its
associated electrical parameters
for reference by golden waveforms
under the [Test Data] keyword.
• If Test_load_type is Differential,
the test load is a pair of the circuits
shown in . If the R_diff_near or
R_diff_far subparameter is used, a
resistor is connected between the
near or far nodes of the two
circuits.
• If Test_load_type is Single_ended,
R_diff_near and R_diff_far are
ignored.
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Chapter 5 Understanding the IBIS Model
5.6 Freescale naming conventions for model names and
usage in i.MX6 IBIS file
The model names are defined per each [Model selector]. The models may differ from
each other by having different parameters—such as voltage, drive strength, mode of
operation, and slew rate. The mode of operation, drive strength, and slew rate parameters
are programmable by software.
5.6.1 [Model Selector] ddr
The “ddr” model type supports the DDR signals.
5.6.2 DDR [Model Selector]
“ddr” models exist for DDR3, DDR3L, DDR3U and LPDDR2 protocols.
This model has the following parameters:
•
•
•
•
DDR protocol
DDR IO type
Drive strength
ODT enable/disable
The IBIS model name is composed from the parameters’ values in two ways, as follows:
• Without active ODT circuit: <ddr protocol>_sel<ddr_type>_ds<drive_strength>_mio
• With active ODT circuit: <ddr protocol>odt_t<ODT_value>_sel<ddr_type>_mi
DDR write models ("_mio" suffix) have no simulated ODT, as ODT is disabled during
write. Write models' DS parameter is meaningful and changes to describe the different
levels of drive strength.
DDR read models ("_mi" suffix) have no meaningful DS parameter, as no driving
happens during read. Read models’ ODT parameter is meaningful and changes to
describe different levels of ODT impedance.
DDR Protocol Selected according to the used DDR. DDR IO voltage level is selected
accordingly.
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Freescale naming conventions for model names and usage in i.MX6 IBIS file
DDR IO Type Controlled by the IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE[19:18]
register in IOMUXC (IOMUX controller) DDR_SEL bits, to select between DDR3 &
LPDDR2.
Drive strength Controlled by bits [5:3] (DSE) of the following registers in IOMUXC
(IOMUX controller):
IOMUXC_SW_PAD_CTL_GRP_BxDS (4 registers)
IOMUXC_SW_PAD_CTL_GRP_CTLDS
IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDRxx (16 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_DQMx (4 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_CSx_B (2 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B
IOMUXC_SW_PAD_CTL_PAD_DRAM_ODTx (2 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBAx (3 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 (2 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P (4 registers)
IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
ODT value Controlled by bits [18:16], [14:12], [10:8], and [6:4] in MPODTCTRL
register of MMDC.
[Model Selector] DDR in IBIS file
ddr3_sel11_ds111_mio
…
lpddr2_sel10_ds111_mio
…
DDR, 1.5V, ddr3 mode, 34 Ohm driver impedance
LPDDR, 1.2V, lpddr2 mode, 34 Ohm driver impedance
See the register description in the IOMUXC chapter in the chip reference manual for
further details about this model.
5.6.3 RGMII
This model has the following parameters:
• RGMII voltage
• Drive strength
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The IBIS model name is composed from the parameters’ values as follows:
rgmii1p8_sel11_ds<drive_strength>_mio
rgmii2p5_sel11_ds<drive_strength>_mio
Voltage Level IBIS currently supports 2.5 V and 1.8 V options. 2.5 V or 1.8V is applied
to NVCC_RGMIIx..
Drive strength Controlled by bits [5:3] (DSE) of the following registers in IOMUXC
(IOMUX controller):
IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC
IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL
IOMUXC_SW_PAD_CTL_PAD_RGMII_TDx (4 registers)
IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC
IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL
IOMUXC_SW_PAD_CTL_PAD_RGMII_RDx (4 registers)
[Model Selector] RGMII in IBIS file
rgmii1p8_sel11_ds111_mio
rgmii1p8_sel11_ds110_mio
rgmii1p8_sel11_ds101_mio
DDR, 1.8V, ddr3 mode, 32/29 Ohm pd/pu driver impedance
DDR, 1.8V, ddr3 mode, 37/34 Ohm pd/pu driver impedance
DDR, 1.8V, ddr3 mode, 45/41 Ohm pd/pu driver impedance
5.6.4 [Model Selector] GPIO
This model has the following parameters:
•
•
•
•
Voltage level
Drive strength
Slew rate
Speed
The IBIS model name is composed from parameters’ values as follows:
gpio<voltage_level>_ds<drive_strength>_sr<slew_rate(1 bit)><speed(2 bits)>_mio
Voltage level For i.MX6 chips, there are no user configurations for the voltage level
because the GPIO cell senses the NVCC and auto-configures itself accordingly. The IBIS
user can choose between high and low voltage by selecting a different model at [Model
Selector].
Drive strength Controlled by the DSE bits (bits [5:3]) in the
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Freescale naming conventions for model names and usage in i.MX6 IBIS file
IOMUXC_SW_PAD_CTL_PAD_<pad name>.
Slew rate Controlled by the SRE bit (bit 0) in the IOMUXC_SW_PAD_CTL_PAD_<pad
name>.
Speed Controlled by the SPEED bits (bits [7:6]) in the
IOMUXC_SW_PAD_CTL_PAD_<pad name>.
[Model Selector] gpio in IBIS file
gpio1p2_ds111_sr111_mio
gpio1p2_ds111_sr110_mio
gpio1p2_ds111_sr101_mio
…
gpio1p5_ds111_sr111_mio
gpio1p5_ds111_sr110_mio
gpio1p5_ds111_sr101_mio
…
gpio1p8_ds111_sr111_mio
gpio1p8_ds111_sr110_mio
gpio1p8_ds111_sr101_mio
gpio1p8_ds111_sr100_mio
…
gpio2p5_ds111_sr111_mio
gpio2p5_ds111_sr110_mio
gpio2p5_ds111_sr101_mio
…
gpio3p3_ds111_sr111_mio
gpio3p3_ds111_sr110_mio
gpio3p3_ds111_sr101_mio
…
GPIO, 1.2 V,extra drive,fast sr,max fsel
GPIO, 1.2 V,extra drive,fast sr,fast fsel
GPIO, 1.2 V,extra drive,fast sr,medium fsel
GPIO, 1.5V,extra drive,fast sr,max fsel
GPIO, 1.5V,extra drive,fast sr,fast fsel
GPIO, 1.5V,extra drive,fast sr,medium fsel
GPIO,
GPIO,
GPIO,
GPIO,
1.8V,extra
1.8V,extra
1.8V,extra
1.8V,extra
drive,fast
drive,fast
drive,fast
drive,fast
sr,max fsel
sr,fast fsel
sr,medium fsel
sr,slow fsel
GPIO, 2.5V,extra drive,fast sr,max fsel
GPIO, 2.5V,extra drive,fast sr,fast fsel
GPIO, 2.5V,extra drive,fast sr,medium fsel
GPIO, 3.3V,extra drive,fast sr,max fsel
GPIO, 3.3V,extra drive,fast sr,fast fsel
GPIO, 3.3V,extra drive,fast sr,medium fsel
See the register description in the IOMUXC chapter in the chip reference manual for
further details about this model.
5.6.5 [Model Selector] LVDS
At the time of publication, i.MX 6SoloX IBIS does not contain the LVDS model. It is
expected to be published in a future revision.
5.6.6 [Model Selector] USB
At the time of publication, i.MX6 IBIS does not contain the USB model. It is expected to
be published in a future revision.
5.6.7 List of pins not modeled in the i.MX6 IBIS file
The following table provides a list of analog or special interface pins that are not modeled
in the i.MX 6SoloX IBIS file.
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Table 5-7. i.MX 6SoloX pins not supported by IBIS
ANALOG
LVDS
PCIe
USB
GPANAIO
LVDS_CLK_N
PCIE_RX_N
USB_OTG1_CHD_B
CCM_CLK2
LVDS_CLK_P
PCIE_RX_P
USB_OTG1_VBUS
CCM_CLK1_N
LVDS_DATA3_N
PCIE_TX_N
USB_OTG2_VBUS
CCM_CLK1_P
LVDS_DATA3_P
PCIE_TX_P
USB_OTG1_DN
RTC_XTALI
LVDS_DATA2_N
—
USB_OTG2_DN
RTC_XTALO
LVDS_DATA2_P
—
USB_OTG1_DP
XTALI
LVDS_DATA1_N
—
USB_OTG2_DP
XTALO
LVDS_DATA1_P
—
—
—
LVDS_DATA0_N
—
—
—
LVDS_DATA0_P
—
—
5.7 Quality assurance for the IBIS models
The IBIS models are validated against the IBIS specification, which provides a way to
objectively measure the correlation of model simulation results with reference transistorlevel spice simulation or measurements.
Correlation The process of making a quantitative comparison between two sets of I/O
buffer characterization data, such as lab measurement vs. structural simulation or
behavioral simulation vs. structural simulation.
Correlation Level A means for categorizing I/O buffer characterization data based on
how much the modeling engineer knows about the processing conditions of a sample
component and which correlation metric he or she used.
All models have passed the following checks:
•
•
•
•
•
IBISCHK without errors or unexplained warnings
Data for basic simulation checked
Data for timing analysis checked
Data for power analysis checked
Correlated against Spice simulations
5.8 IBIS usage
Freescale board designers used the i.MX6Q IBIS model with the Hyperlynx tool by
Mentor Graphics. The HyperLynx version used was HyperLynx v8.1.1 + Update 2.
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References
Effective board design results achieved after loading:
• i.MX6Q IBIS model.
• Companion IC IBIS models.
• Board model in HyperLynx format.
Board simulations for various GPIO, LVDS, and DDR signals were then run.
5.9 References
Consult the following references for more information about the IBIS model.
• IBIS Open Forum (http://ibis.org/)
The IBIS Open Forum consists of EDA vendors, computer manufacturers,
semiconductor vendors, universities, and end-users. It proposes updates and reviews,
revises standards, and organizes summits. It promotes IBIS models and provides
useful documentation and tools.
• IBIS specification
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Chapter 6
Using the Manufacturing Tool
6.1 Overview
The i.MX manufacturing tool is designed to program firmware onto storage devices such
as NAND or eSDe through the EVK and preload the data area with media files in an
efficient and convenient manner. It is intended for Freescale Semiconductor customers or
their OEMs who plan to mass manufacture i.MX-based products.
The application is not designed to test the devices or to diagnose manufacturing
problems. Devices initialized with this application still need to be functionally verified.
6.2 Feature summary
The tool includes the following features:
• Continuous operation—operations automatically begin with the connection of a new
device, and multiple operations such as update and copy can be linked together
seamlessly.
• Enumeration—static-ID firmware loaded into RAM in recovery-mode prevents
Windows® from enumerating every device.
• AutoPlay—various Windows® ‘pop-up’ application and status messages, such as
Explorer in Windows® XP and Windows 7.
In addition, the following characteristics improve the tool’s ease of use:
• An independent process bar is set up for each physical USB port.
• The tool begins processing with the connection of the first device detected and
allows users to replace each device after completion instead of needing to wait for all
devices to complete.
• The tool uses color-based indicators to indicate the work status on each of the ports.
• Blue indicates the device is being processed.
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Version support
• Green indicates the device was successfully processed and that the programmed
device can be replaced with a new one independent of the of the device’s
progress.
• Red indicates the device failed to process.
6.3 Version support
Table 6-1. Version support
Tool
Version requirement
i.MX 6SoloX Manufacturing Tool for WinCE
Version 2.3.2 or later
6.4 Connecting the manufacturing tool to your device
The manufacturing tool can be connected using a USB hub-based physical setup or a
direct connection, as described in “Connecting with a USB hub,” and “Connecting
directly”.
6.4.1 Connecting with a USB hub
The following figure shows how to connect the manufacturing tool, using the USB hubbased physical setup.
Figure 6-1. Physical connection with a USB hub
Connect an external USB 2.0 powered hub to the PC’s USB connection. The hub must
meet the following criteria:
• USB 2.0 compliant
• Externally powered and not bus powered.
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Chapter 6 Using the Manufacturing Tool
NOTE
The hub should be able to supply at least 500 mA per USB port.
The PC should recognize the external USB hub. The manufacturing tool will configure
the USB ports (up to 16) on the external hub(s) for use.
6.4.2 Connecting directly
The following figure shows the direct connect setup configuration. Each device connects
to a single port on an internal PCI USB controller. This configuration is limited to the
number of PCI slots available.
Figure 6-2. Physical connection without a USB hub
6.5 Installing the manufacturing tool
The following subsections explain how to install the manufacturing tool. These
subsections are in chronological order.
6.5.1 Running the .exe
The following steps explain where to install the .exe. This executable can be run directly
and requires no special installation.
1. Unzip the tool package to your local directory (for example, D:\mfgtools-rel\ ).
2. Find MfgTool.exe in the list of files.
3. Run MfgTool.exe in your local directory.
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Installing the manufacturing tool
You should see a user interface similar to the one shown in the following figure.
Figure 6-3. Example user interface
6.5.2 Choosing your player profile
The manufacturing tool requires player profiles, which is a directory that contains all the
information about a particular product. The player profile includes a configuration file
named player.ini that specifies the name of the product, USB IDs, SCSI IDs, device
firmware files, and media files. The profile also contains a list of one or more player
operations to be performed on devices matching the profile. For information about
creating and editing profiles, see the Manufacturing Tool User’s Manual
The bottom of the user interface includes a status information panel. This panel includes
a profile line that displays the currently selected profile, which is called out in the Figure
by a red rectangle. Clicking on the arrow opens a dropdown menu that lists the available
profiles. Use this list to select your desired platform.
NOTE
The start/stop button in the status information panel (called out
by a red circle in the following figure) is disabled until a valid
profile is selected.
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Chapter 6 Using the Manufacturing Tool
Figure 6-4. Choosing your platform from the profile dropdown menu
6.5.3 Installing the drivers
To install drivers, use the following procedure.
1. Connect your board to one of your PC’s USB ports. Make sure you have set the
board to bootstrap mode before powering it on. Refer to chip-specific documentation
to learn how to set the board to bootstrap mode.
2. When you connect and power on your board, you should see the following popwindow:
Figure 6-5. Default welcome window
3. Choose Install from a list or specific location and click Next.
4. Input your driver location: YourDiskVolume:\mfgtools-rel\Drivers\iMX_BulkIO_Driver
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Installing the manufacturing tool
Figure 6-6. Setting your driver location
5. Click Next .
6. Click Finish to finish the driver installation.
Figure 6-7. Finishing the installation
6.5.4 Configuring your system
There are two ways to configure your system: auto-scanning or using the options menu.
To auto-scan the devices connected to your PC, click the scan button on the main window
(as shown in Figure 6-3).
To use the options menu, do the following:
1. Open the options menu at top of the main user interface window.
2. Click configuration to open the configuration window.
3. In the configuration window, click the USB Ports tab; this lets you view all of the
USB ports.
4. Select the USB port to which your device is connected (as shown in the following
figure) and click OK to close the window.
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Chapter 6 Using the Manufacturing Tool
Figure 6-8. Selecting your USB port
6.6 Using the manufacturing tool
Once you have completed all steps in “Connecting the manufacturing tool to your
device,” and “Installing the manufacturing tool,” the tool is ready for use.
The status information panel is located near the bottom of the main application window
(see Figure 6-3). Use this panel to select a profile and to see the status of the profile and
or the firmware version of an update operation. When the tool is idle, the interface
appears as in Figure 6-9.
Click the green start button to initiate a process.
Figure 6-9. Idle interface
Once a process is started, a blue status bar indicates the progress of the processing. The
process can be stopped by clicking the red stop button.
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Using the manufacturing tool
Figure 6-10. Process in progress
If the process completes successfully, the status bar turns green. Click the stop button to
finish the process. If the status bar turns red, the processing failed.
Figure 6-11. Successful process
Once the start/stop button is clicked and the operations begin, the status information
panel displays the following information:
Start Time Time the operations began
Elapsed Time How long have operations been running
Average Duration Average time to complete a single device
Successful Operations How many devices successfully updated
Failed Operations How many device updates have failed
Failure Rate Percentage of failures
If you have a terminal tool to monitor the debug serial port of your board, you can open it
to see more process information than what is presented in the GUI.
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Chapter 6 Using the Manufacturing Tool
6.7 Customizing the manufacturing tool
This chapter illustrates the tool’s behavior with screenshots from the reference design
boards provided by Freescale. However, you can customize the tool for other designs. For
detailed information on customizing the manufacturing tool, see the Manufacturing Tool
User’s Manual
6.8 Other references
For more detailed information about the manufacturing tool, see the following documents
included in the manufacturing tool release package. Contact your local Freescale sales
office for assistance obtaining documents if needed:
• For detailed information about how to use the manufacturing tool, see Manufacturing
Tool V2 Quick Start Guide.
• For detailed information about how to script the processing operations of the
manufacturing tool, see the Manufacturing Tool V2 UCL User Manual.
• For information about how to generate the manufacturing tool firmware for Linux
and Android, see Manufacturing Tool V2 Linux or Android Firmware Development
Guide.
• For the change list and known issues, see Manufacturing Tool V2 Release Notes.
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Other references
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Chapter 7
Using BSDL for Board-level Testing
7.1 BSDL overview
Boundary scan description language (BSDL) is used for board-level testing after
components have been assembled. The interface for this test uses the JTAG pins. The
definition is contained within IEEE Std 1149.1.
7.2 How BSDL functions
A BSDL file defines the internal scan chain, which is the serial linkage of the IO cells,
within a particular device. The scan chain looks like a large shift register, which provides
a means to read the logic level applied to a pin or to output a logic state on that pin. Using
JTAG commands, a test tool uses the BSDL file to control the scan chain so that deviceboard connectivity can be tested.
For example, when using an external ROM test interface, the test tool would do the
following:
1. Output a specific set of addresses and controls to pins connected to the ROM
2. Perform a read command and scan out the values of the ROM data pins.
3. Compare the values read with the known golden values.
Based on this procedure, the tool can determine whether the interface between the two
parts is connected properly and does not contain shorts or opens.
7.3 Downloading the BSDL file
The BSDL file for each i.MX processor is stored on the Freescale website upon product
release. Contact your local sales office or fields applications engineer to check the
availability of information prior to product releases.
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Pin coverage of BSDL
7.4 Pin coverage of BSDL
Each pin is defined as a port within the BSDL file. You can open the file with a text
editor (like Wordpad) to review how each pin will function. The BSDL file defines these
functions as shown:
-------
PORT DESCRIPTION TERMS
in = input only
out = three-state output (0, Z, 1)
buffer = two-state output (0, 1)
inout = bidirectional
linkage = OTHER (vdd, vss, analog)
The appearance of ”linkage” in a pin’s file implies that the pin cannot be used with
boundary scan. These are usually power pins or analog pins that cannot be defined with a
digital logic state.
7.5 Boundary scan operation
The boundary scan operation is controlled by:
• TEST_MODE, POR_B, and JTAG_MOD pins
• On-chip Fuse bits
The JTAG_MOD pin state controls the selection of JTAG to the core logic or boundary
scan operation. See the following references for further information:
• The “System JTAG Controller (SJC)” chapter in the chip reference manual for the
definitions of the JTAG interface operations.
• The “JTAG Security Modes” section in the same chapter for an explanation of the
operation of the e-Fuse bit definitions in the following table.
• The “Fusemap” chapter in the chip reference manual the fusemap tables.
Table 7-1. System considerations for BSDL
Pin name
Logic state
Description
JTAG_MOD
1
IEEE 1149.1 JTAG compliant mode
BOOT_MODE[1:0]
[0:0]
Boot From Fuses
[0:1]
Serial Downloader
[1:0]
Internal Boot (Development)
1
Power On Reset for the device
POR_B
e-Fuse bits
Table continues on the next page...
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Chapter 7 Using BSDL for Board-level Testing
Table 7-1. System considerations for BSDL
(continued)
JTAG_SMODE[1:0]
SJC_DISABLE
[0:0]
JTAG enable mode
[0:1]
Secure JTAG mode
0
Secure JTAG Controller is enabled
7.6 I/O pin power considerations
The boundary scan operation uses each of the available device pins to drive or read
values within a given system. Therefore, the power supply pin for each specific module
must be powered in order for the IO buffers to operate. This is straightforward for the
digital pins within the system.
PCIe is not a digital interface, but the module provides built-in support for the IEEE
1149.6 extension for AC testing of their pins. Therefore, this module must also be
powered when utilizing a scan chain that contains the pins from this module, or the scan
chain does not function properly.
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I/O pin power considerations
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Chapter 8
Appendix A Revision History
Table 8-1. Revision History
Rev. Number
Date
Substantive Change(s)
0
05/2015
Initial release
1
03/2016
Corrected the PCIE signals descriptions in
Table 2-6.
Updated PCIE supply requirements for
boundary scan operation in Table 2-6.
Updated PCIe requirements for unused
PCIE signals and the associated note in
Table 2-17.
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Chapter 9
Appendix B Development Platforms
This appendix provides a complete list of the development platforms that are available
from Freescale to support the i.MX 6SoloX.
Table 9-1. SABRE Board for Smart Devices
Version i.MX used
i.MX 6SoloX
Schematic PN and Rev.
170-27962 Rev. C
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 GByte DDR3L
512 Mbit QSPI Flash
eMMC Footprint
1x SD3.0 SD Card Socket
2x SD2.0 SD Card Sockets
LVDS Port
LCD 24-bit Parallel Port
CSI Camera Connector
Audio Codec
2x Gbit Ethernet (RJ45)
Mini PCIe
Sensors
Accelerometer
Digital eCompass
Ambient Light Sensor
2x CAN Ports
8x 12-bit ADC input Port
Quick Start Guide
Available at www.freescale.com/imxsabre on Freescale
website.
Schematic
Available at www.freescale.com/imxsabre on Freescale
website.
Layout
Available at www.freescale.com/imxsabre on Freescale
website.
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How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: www.freescale.com/salestermsandconditions.
Freescale and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. ARM, the ARM powered logo, and Cortex are the
registered trademarks of ARM Limited, in EU and/or elsewhere. All
other product or service names are the property of their respective
owners. All rights reserved.
© 2016 Freescale Semiconductor, Inc.
Document Number IMX6SXHDG
Revision 1, 03/2016

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