74ABT125 Quad buffer; 3-state Rev. 04 — 27 April 2010 Product data sheet 1. General description The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT125 device is a quad buffer that is ideal for driving bus lines. The device features four Output Enables (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state outputs. 2. Features and benefits Quad bus interface 3-state buffers Live insertion and extraction permitted Output capability: HIGH −32 mA; LOW +64 mA Power-up 3-state Inputs are disabled during 3-state mode Latch-up protection exceeds 500 mA per JESD78 class II level A ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT125N −40 °C to +85 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74ABT125D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ABT125DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74ABT125PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74ABT125BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74ABT125 NXP Semiconductors Quad buffer; 3-state 4. Functional diagram 1Y 2 1A 1 1OE 5 2A 4 2OE 9 3A 3 2 1 2Y 1 3 EN1 5 6 6 10 12 3Y 9 8 8 nOE 10 3OE 4A 4Y nY nA 4 mna227 12 11 11 13 13 4OE mna229 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 5. Pinning information 5.1 Pinning terminal 1 index area 1 74ABT125 1Y 3 12 4A 2OE 4 11 4Y 1A 2 13 4OE 1Y 3 12 4A 2OE 4 5 6 2A 5 10 3OE 2A 2Y 6 9 3A 2Y GND 7 8 3Y 001aai027 11 4Y GND(1) 10 3OE 9 8 13 4OE 3Y 14 VCC 2 7 1 1A GND 1OE 14 VCC 1OE 74ABT125 3A 001aai028 Transparent top view Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1OE to 4OE 1, 4, 10, 13 output enable input (active LOW) 1A to 4A 2, 5, 9, 12 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 6. Functional description Table 3. Function selection[1] Inputs Output nOE nA nY L L L L H H H X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values[1] In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +7.0 V VI input voltage VO output voltage output in OFF-state or HIGH-state −1.2 +7.0 V −0.5 +5.5 V IIK input clamping current VI < 0 V −18 - mA IOK output clamping current VO < 0 V −50 - mA IO output current output in LOW-state - 128 mA Tj junction temperature - 150 °C Tstg storage temperature −65 +150 °C - 500 mW [2] Tamb = −40 °C to +85 °C total power dissipation Ptot [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] SO14 packages: above 70 °C Ptot derate linearly with 8 mW/K SSOP14 and TSSOP20 packages: above 60 °C Ptot derate linearly with 5.5 mW/K DHVQFN14 packages: above 60 °C Ptot derate linearly with 4.5 mW/K 8. Recommended operating conditions Table 5. Operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC Conditions Min Max Unit supply voltage 4.5 5.5 V VI input voltage 0 VCC V VIH HIGH-level input voltage 2.0 - V VIL LOW-level Input voltage - 0.8 V IOH HIGH-level output current −32 - mA IOL LOW-level output current - 64 mA Δt/ΔV input transition rise and fall rate - 10 ns/V Tamb ambient temperature −40 +85 °C 74ABT125_4 Product data sheet in free air All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 °C Conditions −40 °C to +85 °C Unit Min Typ Max Min Max - −0.9 −1.2 - −1.2 V VCC = 4.5 V; IOH = −3 mA 2.5 2.9 - 2.5 - V VCC = 5.0 V; IOH = −3 mA 3.0 3.4 - 3.0 - V VCC = 4.5 V; IOH = −32 mA 2.0 2.4 - 2.0 - V VIK input clamping voltage VCC = 4.5 V; IIK = −18 mA VOH HIGH-level output voltage VI = VIL or VIH VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH - 0.35 0.55 - 0.55 V II input leakage current VCC = 5.5 V; VI = GND or 5.5 V - ±0.01 ±1.0 - ±1.0 μA IOFF power-off leakage current VCC = 0.0 V; VI or VO ≤ 4.5 V - ±5.0 ±100 - ±100 μA IO(pu/pd) power-up/power-down VCC = 2.1 V; VO = 0.5 V; output current VI = GND or VCC; OE = don’t care - ±5.0 ±50 - ±50 μA IOZ OFF-state output current [1] VCC = 5.5 V; VI = VIL or VIH VO = 2.7 V - 1.0 50 - 50 μA VO = 0.5 V - −1.0 −50 - −50 μA - 5.0 50 - 50 μA −50 −100 −180 −50 −180 mA outputs HIGH-state - 65 250 - 250 μA outputs LOW-state - 12 15 - 30 mA - 65 250 - 50 μA outputs enabled - 0.5 1.5 - 1.5 mA outputs disabled - 50 250 - 250 mA one enable input at 3.4 V and other inputs at VCC or GND; outputs disabled - 0.5 1.5 - 1.5 mA ILO output leakage current HIGH-state; VO = 5.5 V; VCC = 5.5 V; VI = GND or VCC IO output current VCC = 5.5 V; VO = 2.5 V ICC supply current VCC = 5.5 V; VI = GND or VCC [2] outputs disabled ΔICC additional supply current per control pin; VCC = 5.5 V; one control input at 3.4 V, other inputs at VCC or GND [3] CI input capacitance VI = 0 V or VCC - 4 - - - pF CO output capacitance outputs disabled; VO = 0 V or VCC - 7 - - - pF [1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %, a transition time of up to 100 μs is permitted. [2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second. [3] This is the increase in supply current for each input at 3.4 V. 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. Test circuit is shown in Figure 8. Symbol Parameter 25 °C; VCC = 5.0 V Conditions −40 °C to +85 °C; Unit VCC = 5.0 V ± 0.5 V Min Typ Max Min Max tPLH LOW to HIGH propagation delay nA to nY, see Figure 6 1.0 2.8 4.1 1.0 4.6 ns tPHL HIGH to LOW propagation delay nA to nY; see Figure 6 1.0 3.1 4.6 1.0 4.9 ns tPZH OFF-state to HIGH propagation delay nOE to nY; see Figure 7 1.0 3.2 5.0 1.0 5.9 ns tPZL OFF-state to LOW propagation delay nOE to nY; see Figure 7 1.0 4.2 6.2 1.0 6.8 ns tPHZ HIGH to OFF-state propagation delay nOE to nY; see Figure 7 1.0 4.1 5.4 1.0 6.2 ns tPLZ LOW to OFF-state propagation delay nOE to nY; see Figure 7 1.5 2.8 5.0 1.5 5.5 ns 11. Waveforms VI VM nA input GND tPHL tPLH VOH VM nY output VOL mna230 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Propagation delay input (nA) to output (nY) 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state VI nOE input VM VM GND tPZL tPLZ 3.5 V output LOW-to-OFF OFF-to-LOW VM VOL + 0.3 V VOL tPHZ VOH tPZH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aal294 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Enable and disable times VI tW 90 % 90 % negative pulse VM 0V VCC 10 % tf tr tr tf VI 90 % positive pulse 0V VEXT VM 10 % VI RL VO G DUT RT 90 % CL RL VM VM 10 % mna616 10 % tW 001aai298 a. Input pulse definition b. Test circuit Test data is given in Table 8. Test circuit definitions: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Table 8. Load circuitry for switching times Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT337-1 (SSOP14) 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT402-1 (TSSOP14) 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description BiCMOS BipolarCMOS DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ABT125_4 20100427 Product data sheet - 74ABT125_3 Modifications: 74ABT125_3 Modifications: • Table note 1 from Table 6 Transition time corrected. 20080429 Product data sheet - 74ABT125_2 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. • • • • Figure 3 “Logic diagram (one buffer)” added to Section 4 “Functional diagram”. Pins renamed throughout the data sheet. Package DHVQFN14 added to Section 3 “Ordering information” and Section 12 “Package outline”. Table 8 “Measurement points” and Table 9 “Test data” added. Figure 8 “Test setup for switching times” updated. Section 13 “Abbreviations” added. 74ABT125_2 19980116 Product specification - 74ABT125_1 74ABT125_1 19960305 - - - 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ABT125_4 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74ABT125_4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 27 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 15 74ABT125 NXP Semiconductors Quad buffer; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 April 2010 Document identifier: 74ABT125_4