74ALVCH16501 18-bit universal bus transceiver; 3-state Rev. 03 — 2 April 2010 Product data sheet 1. General description The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW. To ensure the high-impedance state during power-up or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standard JESD8-B CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at VCC = 3.0 V Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode All inputs have bus hold circuitry Output drive capability 50 Ω transmission lines at 85 °C 3-state non-inverting outputs for bus-oriented applications 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVCH16501DGG −40 °C to +85 °C TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVCH16501DL −40 °C to +85 °C SSOP56 plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 4. Functional diagram OEAB CPAB LEAB 1 EN1 55 2 2C3 C3 G2 OEBA 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 CPBA 54 LEBA 2 55 OEAB OEBA LEAB LEBA CPAB CPBA EN4 30 28 52 5C6 C6 G5 51 49 A0 3 48 47 A1 45 A2 44 A3 43 A4 42 A5 41 A6 40 A7 38 A8 37 A9 36 A10 34 A11 33 A12 31 A13 A14 1 27 27 A15 28 A16 30 A17 3D 1 1 4 1 6D 5 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 001aal718 Fig 1. Logic symbol 74ALVCH16501_3 Product data sheet 54 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 001aal717 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state VCC data input to internal circuit 001aal733 Fig 3. Bus hold circuit OEAB CPBA LEBA CPAB LEAB OEBA C1 C1 1D 1D B1 A1 C1 C1 1D 1D 18 IDENTICAL CHANNELS 001aal719 Fig 4. Logic diagram 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 74ALVCH16501 OEAB 1 56 GND LEAB 2 55 CPAB A0 3 54 B0 GND 4 53 GND A1 5 52 B1 A2 6 51 B2 VCC 7 50 VCC A3 8 49 B3 A4 9 48 B4 A5 10 47 B5 GND 11 46 GND A6 12 45 B6 A7 13 44 B7 A8 14 43 B8 A9 15 42 B9 A10 16 41 B10 A11 17 40 B11 GND 18 39 GND A12 19 38 B12 A13 20 37 B13 A14 21 36 B14 VCC 22 35 VCC A15 23 34 B15 A16 24 33 B16 GND 25 32 GND A17 26 31 B17 OEBA 27 30 CPBA LEBA 28 29 GND 001aal716 Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description OEAB 1 output enable A-to-B input LEAB 2 latch enable A-to-B input A0 to A17 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 data inputs or outputs GND 4, 11, 18, 25, 29, 32, 39, 46, 53, 56 ground (0 V) VCC 7, 22, 35, 50 positive supply voltage OEBA 27 output enable B-to-A LEBA 28 latch enable B-to-A 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state Table 2. Pin description …continued Symbol Pin Description CPBA 30 clock input B-to-A B0 to B17 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs or outputs CPAB 55 clock input A-to-B 6. Functional description 6.1 Function table Table 3. Function table[1] Inputs Output Operating mode OEAB LEAB CPAB An Bn L X X X Z disabled H H X H H transparent H H X L L H ↓ X h H H ↓ X l L H L ↑ h H H L ↑ l L H L H or L X H H L H or L X L [1] latch data and display clock data and display hold data and display A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the enable or clock transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the enable or clock transition; X = don’t care; Z = high-impedance OFF-state; ↓ = HIGH-to-LOW clock transition; ↑ = LOW-to-HIGH clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current ICC supply current 74ALVCH16501_3 Product data sheet Conditions Min Max Unit −0.5 +4.6 V −50 - mA control inputs [1] −0.5 +4.6 V data inputs [1] −0.5 VCC + 0.5 V - ±50 mA −0.5 VCC + 0.5 V - ±50 mA - 100 mA VI < 0 V VO > VCC or VO < 0 V [1] VO = 0 V to VCC All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter IGND Conditions Min Max Unit ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C SSOP package [2] - 850 mW TSSOP package [3] - 600 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Above 55 °C the value of Ptot derates linearly with 11.3 mW/K. [3] Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage maximum speed performance CL = 30 pF 2.3 - 2.7 V CL = 50 pF 3.0 - 3.6 V low-voltage applications 1.2 - 3.6 V 0 - VCC V VI input voltage VO output voltage 0 - VCC V Tamb ambient temperature in free air −40 - +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V VCC = 3.0 V to 3.6 V 0 - 10 ns/V 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V IO = −100 μA; VCC = 2.3 V to 3.6 V VCC − 0.2 VCC - V IO = −6 mA; VCC = 2.3 V VCC − 0.3 VCC − 0.08 - V IO = −12 mA; VCC = 2.3 V VCC − 0.6 VCC − 0.26 - V IO = −12 mA; VCC = 2.7 V VCC − 0.5 VCC − 0.14 - V IO = −12 mA; VCC = 3.0 V VCC − 0.6 VCC − 0.09 - V IO = −24 mA; VCC = 3.0 V VCC − 1.0 VCC − 0.28 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V Unit Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V - 0.1 5 μA IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 2.7 V to 3.6 V - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current per data I/O pin; VCC = 2.3 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V [2] 45 - - μA VCC = 3.0 V; VI = 0.8 V [2] 75 150 - μA VCC = 2.3 V; VI = 1.7 V [2] −45 - - μA VCC = 3.0 V; VI = 2.0 V [2] −75 −175 - μA VCC = 3.6 V [2] 500 - - μA VCC = 3.6 V [2] −500 - - μA IBHH IBHLO bus hold HIGH current bus hold LOW overdrive current IBHHO bus hold HIGH overdrive current CI input capacitance - 4.0 - pF CI/O input/output capacitance - 8.0 - pF [1] All typical values are measured at Tamb = 25 °C. [2] Valid for data inputs of bus hold parts only. 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10. Symbol Parameter Conditions Min Typ[1] Max Unit Tamb = −40 °C to +85 °C fmax maximum frequency see Figure 8 VCC = 2.3 V to 2.7 V [2] 150 333 - MHz VCC = 3.0 V to 3.6 V [3] 150 340 - MHz 150 333 - MHz VCC = 2.7 V tpd propagation delay An to Bn; Bn to An; see Figure 6 [4] VCC = 2.3 V to 2.7 V [2] 1.0 2.8 5.1 ns VCC = 3.0 V to 3.6 V [3] 1.0 3.0 4.2 ns - 3.0 4.6 ns VCC = 2.7 V LEAB, LEBA to Bn, An; see Figure 8 VCC = 2.3 V to 2.7 V [2] 1.1 3.5 6.1 ns VCC = 3.0 V to 3.6 V [3] 1.3 3.4 4.8 ns - 3.6 5.3 ns VCC = 2.7 V CPAB, CPBA to Bn, An; see Figure 8 VCC = 2.3 V to 2.7 V [2] 1.0 3.3 6.1 ns VCC = 3.0 V to 3.6 V [3] 1.4 3.3 4.9 ns - 3.4 5.6 ns VCC = 2.7 V ten enable time OEBA to An; see Figure 7 [4] VCC = 2.3 V to 2.7 V [2] 1.3 2.8 6.3 ns VCC = 3.0 V to 3.6 V [3] 1.1 2.5 5.0 ns - 3.3 6.0 ns VCC = 2.7 V OEAB to Bn; see Figure 7 VCC = 2.3 V to 2.7 V [2] 1.0 2.5 5.8 ns VCC = 3.0 V to 3.6 V [3] 1.0 2.4 4.6 ns - 2.7 5.3 ns VCC = 2.7 V tdis disable time OEBA to An; see Figure 7 [4] VCC = 2.3 V to 2.7 V [2] 1.3 2.5 5.3 ns VCC = 3.0 V to 3.6 V [3] 1.3 3.1 4.2 ns - 3.3 4.6 ns VCC = 2.7 V OEAB to Bn; see Figure 7 VCC = 2.3 V to 2.7 V [2] 1.5 2.5 6.2 ns VCC = 3.0 V to 3.6 V [3] 1.4 2.9 5.0 ns - 3.6 5.7 ns VCC = 2.7 V 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state Table 7. Dynamic characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit Figure 10. Symbol Parameter Conditions tW pulse width LEAB, LEBA HIGH; see Figure 8 Min Typ[1] Max Unit VCC = 2.3 V to 2.7 V [2] 3.3 0.8 - ns VCC = 3.0 V to 3.6 V [3] 3.3 0.9 - ns 3.3 0.7 - ns VCC = 2.7 V CPAB, CPBA HIGH or LOW; see Figure 8 VCC = 2.3 V to 2.7 V [2] 3.3 2.0 - ns VCC = 3.0 V to 3.6 V [3] 3.3 1.1 - ns 3.3 1.4 - ns VCC = 2.7 V tsu set-up time An, Bn to CPAB, CPBA; see Figure 9 VCC = 2.3 V to 2.7 V [2] 1.7 0.1 - ns VCC = 3.0 V to 3.6 V [3] 1.3 −0.3 - ns 1.4 −0.1 - ns 0.1 - ns VCC = 2.7 V An, Bn to LEAB, LEBA; see Figure 9 VCC = 2.3 V to 2.7 V [2] 1.1 VCC = 3.0 V to 3.6 V [3] 1.0 0.3 - ns 1.0 −0.2 - ns VCC = 2.7 V th hold time An, Bn to CPAB, CPBA; see Figure 9 VCC = 2.3 V to 2.7 V [2] 1.7 0.3 - ns VCC = 3.0 V to 3.6 V [3] 1.3 0.4 - ns 1.6 0.3 - ns VCC = 2.7 V An, Bn to LEAB, LEBA; see Figure 9 VCC = 2.3 V to 2.7 V [2] 1.6 0.3 - ns VCC = 3.0 V to 3.6 V [3] 1.2 0.1 - ns 1.5 0.1 - ns outputs enabled - 21 - pF outputs disabled - 3 - pF VCC = 2.7 V CPD power dissipation capacitance per buffer; VI = GND to VCC [1] All typical values are measured at Tamb = 25 °C. [2] Typical values are measured at VCC = 2.5 V. [3] Typical values are measured at VCC = 3.3 V. [4] tpd is the same as tPLH and tPHL. [5] ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 11. Waveforms VI An, Bn input VM VM tPHL tPLH GND VOH Bn, An output VM VM VOL 001aal734 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 6. Propagation delay, data input (An, Bn) to data output (Bn, An) VI OEAB, OEBA input VM VM GND tPLZ tPZL VCC An, Bn output LOW-to-OFF OFF-to-LOW VM VX VOL tPZH tPHZ VOH VY An, Bn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aal721 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 7. 3-state output enable and disable times 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 1 / fmax VI LExx input CPxx input GND VM VM tW VM tPLH tPHL VOH An, Bn output VM VOL VM 001aal720 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output, and pulse width VI An, Bn input VM VM GND tsu th VM tsu VM th VI CPxx, LExx input VM VM GND 001aal722 Measurement points are given in Table 8. Fig 9. Table 8. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs) Measurement points Supply voltage Input VCC VI VM VM VX VY 2.3 V to 2.7 V VCC 0.5 0.5 VOL + 0.15 V VOH − 0.15 V 2.7 V 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74ALVCH16501_3 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 12. Test information VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance includes jig and probe capacitance. RT = Termination resistance should be equal to Zo of pulse generator. VEXT = External voltage for measuring switching times. Fig 10. Load circuit for measuring switching times Table 9. Test data Supply voltage Input VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74ALVCH16501_3 Product data sheet Load VEXT All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 13. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT364-1 (TSSOP56) 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1 D E A X c y HE v M A Z 29 56 Q A2 A1 A (A 3) θ pin 1 index Lp L 28 1 bp e 0 detail X w M 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.8 0.4 0.2 2.35 2.20 0.25 0.3 0.2 0.22 0.13 18.55 18.30 7.6 7.4 0.635 10.4 10.1 1.4 1.0 0.6 1.2 1.0 0.25 0.18 0.1 0.85 0.40 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT371-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-118 Fig 12. Package outline SOT371-1 (SSOP56) 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Order number Supersedes 74ALVCH16501_3 20100402 - 74ALVCH16501_2 Modifications: Product data sheet - • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. Section 3 “Ordering information”: Added type 74ALVCH16501DL. Quick reference section removed. 74ALVCH16501_2 19980929 Product specification - - 74ALVCH16501_1 74ALVCH16501_1 19980929 Product specification - - - 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 15 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74ALVCH16501_3 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 16 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74ALVCH16501_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 17 of 18 74ALVCH16501 NXP Semiconductors 18-bit universal bus transceiver; 3-state 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 April 2010 Document identifier: 74ALVCH16501_3