74LVTN16245B 3.3 V 16-bit transceiver; 3-state Rev. 02 — 23 March 2010 Product data sheet 1. General description The 74LVTN16245B is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is a 16-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The control function implementation minimizes external timing requirements. The device features an output enable input (nOE) for easy cascading and a direction input (nDIR) for direction control. 2. Features and benefits 16-bit bus interface 3-state buffers Output capability: +64 mA and −32 mA TTL input and output switching levels Input and output interface capability to systems at 5 V supply Power-up 3-state Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Latch-up protection JESD78B Class II exceeds 500 mA ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVTN16245BDGG −40 °C to +85 °C TSSOP48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 74LVTN16245BBQ −40 °C to +85 °C HXQFN60U plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 × 6 × 0.5 mm SOT1134-1 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 4. Functional diagram 2DIR 1DIR 2OE 1OE 2A0 1A0 1B0 1A1 2B0 2A1 2B1 1B1 1A2 2A2 1B2 1A3 2B2 2A3 1B3 1A4 2B3 2A4 2B4 1B4 1A5 2A5 1B5 1A6 2B5 2A6 1B6 2B6 2A7 1A7 1B7 2B7 001aaa789 Fig 1. Logic symbol 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 2 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 1OE G3 1DIR 3EN1[BA] 3EN2[AB] 2OE G6 2DIR 6EN4[BA] 6EN5[AB] 1A0 1 1B0 2 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 2A0 1B7 4 2B0 5 2A1 2B1 2A2 2B2 2A3 2B3 2A4 2B4 2A5 2B5 2A6 2B6 2A7 2B7 001aak306 Fig 2. IEC logic symbol 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 3 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 5. Pinning information 5.1 Pinning 74LVTN16245B 1DIR 1 48 1OE 1B0 2 47 1A0 1B1 3 46 1A1 GND 4 45 GND 1B2 5 44 1A2 1B3 6 43 1A3 VCC 7 42 VCC 1B4 8 41 1A4 1B5 9 40 1A5 GND 10 39 GND 1B6 11 38 1A6 1B7 12 37 1A7 2B0 13 36 2A0 2B1 14 35 2A1 GND 15 34 GND 2B2 16 33 2A2 2B3 17 32 2A3 VCC 18 31 VCC 2B4 19 30 2A4 2B5 20 29 2A5 GND 21 28 GND 2B6 22 27 2A6 2B7 23 26 2A7 2DIR 24 25 2OE 001aak307 Fig 3. Pin configuration SOT362-1 (TSSOP48) 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 4 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state terminal 1 index area D1 A32 A1 D5 A31 A30 B20 A29 B19 A28 B18 A27 D4 D8 A26 A2 A25 B1 B17 B2 B16 A3 A24 A4 A23 B15 B3 A5 A22 74LVTN16245B B4 B14 A6 A21 B5 B13 B6 B12 A7 A20 A8 A19 B7 B11 A9 A18 GND(1) A10 D6 D2 A11 B9 B8 A12 A13 B10 A14 A15 D7 A17 A16 D3 001aak308 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SOT1134-1 (HXQFN60U) 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 5 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description SOT362-1 SOT1134-1 1DIR, 2DIR 1, 24 A30, A13 direction control input 1B0 to 1B7 2, 3, 5, 6, 8, 9, 11, 12 B20, A31, D5, D1, A2, B2, B3, A5 data input/output 2B0 to 2B7 13, 14, 16, 17, 19, 20, 22, 23 A6, B5, B6, A9, D2, D6, A12, B8 data input/output GND 4, 10, 15, 21, 28, 34, 39, 45 A32, A3, A8, A11, A16, A19, A24, A27 ground (0 V) VCC 7, 18, 31, 42 A1, A10, A17, A26 supply voltage 1OE, 2OE 48, 25 A29, A14 output enable input (active LOW) 2A0 to 2A7 36, 35, 33, 32, 30, 29, 27, 26 A21, B13, B12, A18, D3, D7, A15, B10 data input/output 1A0, to 1A7 47, 46, 44, 43, 41, 40, 38, 37 B18, A28, D8, D4, A25, B16, B15, A22 data input/output n.c. - A4, A7, A20, A23, B1, B4, B7, B9, B11, B14, B17, B19 not connected 6. Functional description Table 3. Function table [1] Control Input/output nOE nDIR nAn nBn L L output nAn = nBn input L H input output nBx = nAx H X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +4.6 V input voltage [1] −0.5 +7.0 V VO output voltage output in OFF-state or HIGH-state [1] −0.5 +7.0 V IIK input clamping current VI < 0 V −50 - mA IOK output clamping current VO < 0 V −50 - mA IO output current output in LOW-state - 128 mA output in HIGH-state −64 - mA −65 +150 °C - 150 °C VI Tstg Tj storage temperature [2] junction temperature 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 6 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Ptot total power dissipation Tamb = −40 °C to +85 °C Min Max Unit TSSOP48 package [3] - 500 mW HXQFN60U package [4] - 1000 mW [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. [3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K. [4] Above 70 °C the value of Ptot derates linearly with 1.8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC supply voltage Conditions 2.7 - 3.6 V VI input voltage 0 - 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IOH HIGH-level output current −32 - - mA IOL LOW-level output current none - - 32 mA current duty cycle ≤ 50 %; fi ≥ 1 kHz - - 64 mA in free-air −40 - +85 °C - - 10 ns/V Tamb ambient temperature Δt/ΔV input transition rise and fall rate outputs enabled 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit VCC = 2.7 V; IIK = −18 mA −1.2 −0.85 - V VCC − 0.2 VCC - V IOH = −8 mA; VCC = 2.7 V 2.4 2.5 - V IOH = −32 mA; VCC = 3.0 V 2.0 2.3 - V IOL = 100 μA - 0.07 0.2 V IOL = 24 mA - 0.3 0.5 V IOL = 16 mA - 0.25 0.4 V IOL = 32 mA - 0.3 0.5 V IOL = 64 mA - 0.4 0.55 V Tamb = −40 °C to +85 °C VIK input clamping voltage VOH HIGH-level output voltage IOH = −100 μA; VCC = 2.7 V to 3.6 V VOL LOW-level output voltage VCC = 2.7 V VCC = 3.0 V 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 7 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Min Typ[1] Max Unit - 0.1 ±1 μA - 0.1 10 μA VI = 5.5 V - 0.1 20 μA VI = VCC - 0.5 10 μA VI = 0 V Symbol Parameter Conditions II control pins input leakage current VCC = 3.6 V; VI = VCC or GND VCC = 0 V or 3.6 V; VI = 5.5 V input/output data pins; VCC = 3.6 V [2] −5 −0.1 - μA IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 μA ILO output leakage current output in HIGH-state when VO > VCC; VO = 5.5 V; VCC = 3.0 V - 75 125 μA IO(pu/pd) power-up/power-down output current VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; nOE = don’t care - 40 ±100 μA ICC supply current VCC = 3.6 V; VI = GND or VCC; IO = 0 A - 0.07 0.12 mA [3] output HIGH output LOW outputs disabled - 4.0 6.0 mA [4] - 0.07 0.12 mA [5] - 0.1 0.2 mA ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input at VCC − 0.6 V other inputs at VCC or GND CI input capacitance pins nDIR and nOE, VO = 0 V or 3.0 V - 3 - pF Cio(off) off-state input/output capacitance pins nAn and nBn, outputs disabled; VO = GND or VCC - 9 - pF [1] Typical values are measured at VCC = 3.3 V and at Tamb = 25 °C. [2] Unused pins at VCC or GND. [3] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only. [4] ICC is measured with outputs pulled to VCC or GND. [5] This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 8 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Min Typ[1] Max Unit VCC = 2.7 V - - 3.5 ns VCC = 3.0 V to 3.6 V 1.0 1.9 3.3 ns VCC = 2.7 V - - 3.5 ns VCC = 3.0 V to 3.6 V 1.0 1.7 3.3 ns VCC = 2.7 V - - 5.3 ns VCC = 3.0 V to 3.6 V 1.0 2.8 4.5 ns VCC = 2.7 V - - 5.1 ns VCC = 3.0 V to 3.6 V 1.0 2.8 4.1 ns VCC = 2.7 V - - 5.7 ns VCC = 3.0 V to 3.6 V 1.5 3.2 5.1 ns VCC = 2.7 V - - 4.6 ns VCC = 3.0 V to 3.6 V 1.5 3.0 4.6 ns Conditions Tamb = −40 °C to +85 °C LOW to HIGH propagation delay tPLH HIGH to LOW propagation delay tPHL OFF-state to HIGH propagation delay tPZH OFF-state to LOW propagation delay tPZL HIGH to OFF-state propagation delay tPHZ LOW to OFF-state propagation delay tPLZ [1] nAn to nBn or nBn to nAn; see Figure 5 nAn to nBn or nBn to nAn; see Figure 5 nOE to nAn or nBn; see Figure 6 nOE to nAn or nBn; see Figure 6 nOE to nAn or nBn; see Figure 6 nOE to nAn or nBn; see Figure 6 Typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 9 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 11. Waveforms VI nAn, nBn input VM GND t PHL t PLH VOH nBn, nAn output VM VOL mna477 Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Propagation delay input (nAn, nBn) to output (nBn, nAn) VI nOE input VM 0V tPLZ tPZL 3.0 V nAn or nBn output VM VX VOL tPHZ tPZH VOH nBn or nAn output VY VM 0V 001aaj658 Measurements points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Enable and disable times Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 10 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state VI tW 90 % negative pulse VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI PULSE GENERATOR RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Table 9. Load circuit for measuring switching times Test data Input Load VEXT VI fi tW tr, tf CL RL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6V open 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 11 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 12. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 8. Package outline SOT362-1 (TSSOP48) 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 12 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 4 x 6 x 0.5 mm B D SOT1134-1 A terminal 1 index area E A A1 detail X e2 e1 1/2 e e C A B C v w L1 D2 D6 A11 eR y D7 B10 A10 L y1 C D3 A16 B8 C C A B C v w b A17 e B11 B7 e3 Eh e4 1/2 e B1 B17 A1 terminal 1 index area A26 D5 D1 B20 B18 A32 D8 A27 X D4 Dh k 0 2.5 Dimensions Unit mm 5 mm scale A A1 b max 0.50 0.05 0.35 nom 0.48 0.02 0.30 min 0.46 0.00 0.25 D Dh E Eh e e1 e2 e3 e4 eR 4.1 4.0 3.9 1.90 1.85 1.80 6.1 6.0 5.9 3.90 3.85 3.80 0.5 1 2.5 3 4.5 0.5 k L 0.25 0.35 0.20 0.30 0.15 0.25 L1 0.125 0.075 0.025 v w y 0.07 0.05 0.08 y1 0.1 sot1134-1_po Fig 9. References Outline version IEC JEDEC JEITA SOT1134-1 --- --- --- European projection Issue date 08-12-17 09-01-22 Package outline SOT1134-1 (HXQFN60U) 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 13 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 13. Abbreviations Table 10. Abbreviations Acronym Description BiCMOS Bipolar Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVTN16245B_2 20100323 Product data sheet - 74LVTN16245B_1 Modifications: 74LVTN16245B_1 74LVTN16245B_2 Product data sheet • 74LVTN16245BBQ changed from HUQFN60U (SOT1025-1) to HXQFN60U (SOT1134-1) package. 20090729 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 - © NXP B.V. 2010. All rights reserved. 14 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74LVTN16245B_2 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 15 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVTN16245B_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 23 March 2010 © NXP B.V. 2010. All rights reserved. 16 of 17 74LVTN16245B NXP Semiconductors 3.3 V 16-bit transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 23 March 2010 Document identifier: 74LVTN16245B_2