DSP56720 Chip Errata

Freescale Semiconductor
Chip Errata
Document Number: DSP56720CE
Rev. 1.0, 12/2007
DSP56720
Silicon Revision: 0M78E
Table 1 defines Severity values for errata described in this document.
Table 1. Definitions of Errata Severity
Severity
Errata
Type
1
Critical
2
High
Failure mode that might restrict or limit the use of the device for all or a majority Generally available
of intended applications
3
Moderate
Unexpected behavior that does not cause significant problems for the intended Generally available
applications of the device
Meaning
Failure mode that severely inhibits the use of the device for all or a majority of
intended applications
Workaround
Unavailable
Table 3 lists known chip errata affecting the versions of DSP56720 identified in the final column. Table 2
summarizes the errata described in more detail in Table 3.
Table 2. Chip Errata Summary for DSP56720
Severity
Erratum ID
Title
3
ES153
Clearing Individual ESAI Interrupt Enable Bits
0M78E
3
ES154
Port A Data Register When Configured For External Memory Controller
0M78E
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Silicon Revision
Table 3. Chip Errata for DSP56720
Severity
Erratum ID
3
ES153
Summary
Module Affected:
ESAI/ESAI_1/ESAI_2/
ESAI_3
Title:
Clearing Individual ESAI
Interrupt Enable Bits
Release Date:
September 2007
Silicon
Revision
Details
Description: If an ESAI transmit interrupt enable bit
(TEIE, TEDIE, TIE, TLIE) or an ESAI receive interrupt
enable bit (REIE, REDIE, RIE, RLIE) is cleared by
software while that same interrupt is asserted then the
interrupt vector received by the DSP56300 core may
be for the ESAI Receive Data interrupt if no other ESAI
interrupts are pending.
0M78E
This only occurs if the interrupt is disabled before the
interrupt vector is calculated but after the DSP56300
core has accepted that interrupt as the highest priority
pending interrupt. The ESAI Receive Data interrupt
does not need to be enabled for this to happen.
This errata also applies to ESAI_1, ESAI_2 and
ESAI_3.
Workaround: Mask the ESAI interrupt in the IPRP
register while clearing an individual ESAI interrupt
enable bit. It is also valid to globally mask all interrupts
while the individual ESAI interrupt is disabled, but this
is not required.
Fix Plan/Status: Not fixed.
3
ES154
Module Affected:
GPIO
Title:
Port A Data Register
When Configured For
External Memory
Controller
Release Date:
September 2007
Description: If Port A Control and Direction Register
bits are configured to enable the External Memory
Controller (PCRA[x] = PRRA[x] = 1) then the
corresponding Port A Data Register bit must be kept
clear (PCDA[x] = 0) otherwise the LAD[x] pin may be
driven with an incorrect value.
0M78E
Workaround: For each bit in the Port A Data Register,
ensure PCDA[x] = 0 whenever PCRA[x] = PRRA[x] = 1.
Fix Plan/Status: Not fixed.
DSP56720 Chip Errata, Rev. 1.0
2
Freescale Semiconductor
NOTES
DSP56720 Chip Errata, Rev. 1.0
Freescale Semiconductor
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Document Number: DSP56720CE
Rev. 1.0
12/2007
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