FREESCALE DSP56720

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: DSP56720
Rev.1, 12/2007
DSP56720 / DSP56721
DSP56720
144-Pin LQFP
20 mm x 20 mm
0.5 mm pitch
SymphonyTM DSP56720 /
DSP56721 Multi-Core Audio
Processors
144-Pin LQFP
20 mm x 20 mm
0.5 mm pitch
The Symphony DSP56720/DSP56721 Multi-Core Audio
Processors are part of the DSP5672x family of programmable
CMOS DSPs, designed using multiple DSP56300 24-bit
cores.
Ordering Information
The DSP56720/DSP56721 devices are intended for
automotive, consumer, and professional audio applications
that require high performance for audio processing. In
addition, the DSP56720 is ideally suited for applications that
need the capability to expand memory off-chip or to interface
to external parallel peripherals. Potential applications include
A/V receivers, HD-DVD and Blu-Ray players, car
audio/amplifiers, and professional recording equipment.
The DSP56720/DSP56721 devices excel at audio processing
for automotive and consumer audio applications requiring
high MIPs. Higher MIPs and memory requirements are driven
by the new high-definition audio standards (Dolby Digital+,
Dolby TrueHD, DTS-HD, for example) and the desire to
process multiple audio streams.
In addition, DSP56720/DSP56721 devices are optimal for the
professional audio market requiring audio recording, signal
processing, and digital audio synthesis.
The DSP56720/DSP56721 processors provide a wealth of
on-chip audio processing functions, via a plug and play
software architecture system that supports audio decoding
algorithms, various equalization algorithms, compression,
signal generator, tone control, fade/balance, level
meter/spectrum analyzer, among others. The
DSP56720/DSP56721 devices also support various matrix
decoders and sound field processing algorithms.
DSP56721
80-Pin LQFP
14 mm x 14 mm
0.65 mm pitch
Device
DSP56720
DSP56720
Device Marking or
Operating Temperature
Range
LQFP Package
DSPA56720AG
20 mm x 20 mm
DSPB56720AG
20 mm x 20 mm
DSPA56721AG
20 mm x 20 mm
DSPB56721AG
20 mm x 20 mm
DSPA56721AF
14 mm x 14 mm
DSPB56721AF
14 mm x 14 mm
Communication (ICC), an External Memory Controller
(EMC) to support SDRAM, and a Sony/Philips Digital
Interface (S/PDIF).
The DSP56720/DSP56721 offer 200 million instructions per
second (MIPs) per core using an internal 200 MHz clock.
The DSP56720/DSP56721 are high density CMOS devices
with 3.3 V inputs and outputs.
The DSP56720 device is slightly different than the DSP56721
device—the DSP56720 includes an external memory
interface while the DSP56721 device does not. The
DSP56720 block diagram is shown in Figure 1; the
DSP56721 block diagram is shown in Figure 2.
With two DSP56300 cores, a single DSP56720 or DSP56721
device can replace dual-DSP designs, saving costs while
meeting high MIPs requirements. Legacy peripherals from
the previous DSP5636x/7x families are included, as well as a
variety of new modules. Included among the new modules are
an Asynchronous Sample Rate Converter (ASRC), Inter-Core
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2006, 2007. All rights reserved.
Table of Contents
1
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Pinout for DSP56720 144-Pin Plastic LQFP Package . .4
1.2 Pinout for DSP56721 80-Pin Plastic LQFP Package . . .6
1.3 Pinout for DSP56721 144-Pin Plastic LQFP Package . .7
1.4 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .8
2.1.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . .10
2.1.3 Power Requirements . . . . . . . . . . . . . . . . . . . . .10
2.1.4 DC Electrical Characteristics . . . . . . . . . . . . . . .11
2.1.5 AC Electrical Characteristics . . . . . . . . . . . . . . .12
2.1.6 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . .12
2.1.7 External Clock Operation. . . . . . . . . . . . . . . . . .13
2.1.8 Reset, Stop, Mode Select, and Interrupt Timing 14
2.2 Module-Level Specifications . . . . . . . . . . . . . . . . . . . . .17
2.2.1 Serial Host Interface (SHI) SPI Protocol Timing 18
2.2.2 Serial Host Interface (SHI) I2C Protocol Timing.24
3
4
5
6
7
8
2.2.3 Programming the SHI I2C Serial Clock . . . . . . 26
2.2.4 Enhanced Serial Audio Interface (ESAI) Timing 27
2.2.5 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.6 GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.7 JTAG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2.8 Watchdog Timer Timing . . . . . . . . . . . . . . . . . . 35
2.2.9 Host Data Interface (HDI24) Timing . . . . . . . . . 35
2.2.10 S/PDIF Timing . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2.11 EMC Timing (DSP56720 only) . . . . . . . . . . . . . 43
Functional Description and Application Information . . . . . . . 48
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1 80-Pin Package Outline Drawing . . . . . . . . . . . . . . . . . 48
6.2 144-Pin Package Outline Drawing . . . . . . . . . . . . . . . . 51
Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
2
Freescale Semiconductor
DSP
Core-0
On-Chip
Memory
P
GPIO
WDT_1
ESAI_3
DSP
Core-1
ASRC
On-Chip
Memory
Arbiter 8
Shared Bus 0
Y
ESAI_2
TEC_1
SHI_1
Chip Config
GPIO
CGM
Arbiter 9
X
S/PDIF
EMC
GPIO
WDT
ESAI_1
ESAI
TEC
SHI
EXTAL/XTAL
P
X
Y
Shared Bus 1
Arbiters 0–7
PCU
/ AGU
/ ALU
DMA
OnCE
PCU
/ AGU
/ ALU
OnCE
Shared Memory 8K
Blocks 0–7 (64K total)
MODA0, MODB0,
MODC0, MODD0
DMA
MODA1, MODB1,
MODC1, MODD1
2 JTAGs
JTAG
Figure 1. DSP56720 Block Diagram
DSP
Core-0
On-Chip
Memory
ASRC
X
GPIO
WDT_1
ESAI_3
ESAI_2
TIMER_1
SHI_1
DSP
Core-1
On-Chip
Memory
Arbiter 8
Shared Bus 0
P
HDI24_1
GPIO
SPDIF
CGM
Chip Config
EXTAL/XTAL
HDI24
GPIO
WDT
ESAI_1
ESAI
TIMER
SHI
HDI24
Shared Bus 1
Y
P
X
Y
Arbiters 0–7
PCU
/ AGU
/ ALU
DMA
OnCE
OnCE
Shared Memory 8K
Blocks 0–7 (64K total)
MODA0, MODB0,
MODC0, MODD0
2 JTAGs
JTAG
PCU
/ AGU
/ ALU
DMA
MODA1, MODB1,
MODC1, MODD1
Figure 2. DSP56721 Block Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
3
1
Pin Assignments
DSP56720 devices are available in one package type; DSP56721 devices are available in two package types. For the pin
assignments of a specific device in a specific package, please see sections 1.2–1.1.
Table 1. Pin Assignments by Package
Device
Package
See
DSP56720
144-pin plastic LQFP
Figure 3 on page 5
DSP56721
80-pin plastic LQFP
Figure 4 on page 6
144-pin plastic LQFP
Figure 5 on page 7
For more detailed information about signals, refer to the DSP56720/DSP56721 Reference Manual (DSP56720RM).
1.1
Pinout for DSP56720 144-Pin Plastic LQFP Package
For the pinout of the DSP56720 144-pin plastic LQFP package, see Figure 3.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
4
Freescale Semiconductor
SCAN
MODA0/IRQA
MODB0/IRQB
MODC0/PLOCK
MODD0/PG1
FSR_3
SCKR_3
HCKR_3
SCKT_3
FST_3
HCKT_3
IO_GND
IO_VDD
CORE_GND
CORE_VDD
MODA1/IRQC
MODB1/IRQD
MODC1/NMI_1
MODD1/PG2
SDO2_2/SDI3_2
SDO3_2/SDI2_2
SDO4_2/SDI1_2
SDO5_2/SDI0_2
SDO2_3/SDI3_3
SDO3_3/SDI2_3
SDO4_3/SDI1_3
SDO5_3/SDI0_3
SS/HA2
HREQ/PH4
SCK/SCL
MOSI/HA0
MISO/SDA
SS_1/HA2_1
RESET
CORE_GND
CORE_VDD
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DSP56720
144-Pin
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
IO_GND
IO_VDD
WDT
PINIT/NMI
TDO
TDI
TCK
TMS
SDO2_1/SDI3_1
SDO3_1/SDI2_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
CORE_GND
CORE_VDD
FSR
SCKR
HCKR
SCKT
FST
HCKT
SDO2/SDI3
SDO3/SDI2
SDO4/SDI1
SDO5/SDI0
SPDIFOUT1
SPDIFIN1
IO_GND
IO_VDD
EXTAL
XTAL
PLLP_GND
PLLD_GND
PLLD_VDD
PLLA_GND
PLLA_VDD
PLLP_VDD
LSYNC_IN
LSYNC_OUT
LAD23
LAD22
LAD21
LAD20
LAD19
LAD18
LAD17
CORE_VDD
CORE_GND
IO_VDD
IO_GND
LAD16
LAD15
LAD14
LAD13
LAD12
LAD11
LAD10
LAD9
IO_VDD
IO_GND
CORE_VDD
CORE_GND
LAD8
LAD7
LAD6
LAD5
LAD4
LAD3
LAD2
LAD1
LAD0
IO_GND
IO_VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
CORE_VDD
CORE_GND
LALE
LCS0
LCS1
LCS2
LCS3
LCS4
LCS5
LCS6
LCS7
IO_VDD
IO_GND
CORE_VDD
CORE_GND
LWE
LOE
LGPL5
LSDA10
LCKE
LCLK
LBCTL
LSDWE
LSDCAS
LGTA
LA0
LA1
LA2
IO_VDD
IO_GND
PLLP1_GND
PLLP1_VDD
PLLD1_GND
PLLD1_VDD
PLLA1_GND
PLLA1_VDD
Figure 3. DSP56720 144-Pin Package Pinout
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
5
1.2
Pinout for DSP56721 80-Pin Plastic LQFP Package
SCK/SCL
MOSI/HA0
MISO/SDA
67
66
65
CORE_VDD
HREQ/PH4
68
CORE_GND
SS/HA2
69
61
MODC1/NMI_1
70
62
MODB1/IRQD
71
SS_1/HA2_1
MODA1/IRQC
72
RESET
CORE_VDD
73
63
CORE_GND
74
64
IO_GND
MODC0/PLOCK
77
IO_VDD
MODB0/IRQB
78
75
MODA0/IRQA
79
76
SCAN
80
For the pinout of the DSP56721 80-pin plastic LQFP package, see Figure 4.
SDO2_3/SDI3_3
1
60
WDT
SDO3_3/SDI2_3
2
59
PINIT/NMI
SDO4_3/SDI1_3
3
58
TDO
SDO5_3/SDI0_3
4
57
TDI
IO_VDD
5
56
TCK
IO_GND
6
55
TMS
CORE_VDD
7
54
CORE_GND
CORE_GND
8
53
CORE_VDD
52
SDO4/SDI1
51
SDO5/SDI0
SPDIFIN1/SDO2_2/SDI3_2
DSP56721
9
SPDIFOUT1/SDO3_2/SDI2_2
10
80-Pin
38
39
40
HCKT
SDO2/SDI3
SDO3/SDI2
36
CORE_GND
37
35
CORE_VDD
FST
34
PLLP_VDD
IO_GND
41
33
PLLA_VDD
20
IO_VDD
42
GND
32
19
SCKT
PLLA_GND
GND
31
43
HCKR
18
30
PLLD_VDD
GND
SCKR
PLLD_GND
44
29
45
17
FSR
16
GND
28
GND
27
PLLP_GND
SDO5_1/SDI0_1
46
SDO4_1/SDI1_1
15
26
XTAL
SCKT_3
CORE_GND
47
25
14
CORE_VDD
EXTAL
SCKR_3
24
48
SDO3_1/SDI2_1
IO_VDD
13
23
49
FSR_3
SDO2_1/SDI3_1
12
22
IO_GND
SDO5_2/SDI0_2
21
50
FST_3
11
HCKT_3
SDO4_2/SDI1_2
Figure 4. DSP56721 80-Pin Package
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
6
Freescale Semiconductor
1.3
Pinout for DSP56721 144-Pin Plastic LQFP Package
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
SCAN
MODA0/IRQA
MODB0/IRQB
MODC0/PLOCK
MODD0/PG1
IO_GND
IO_VDD
CORE_GND
CORE_VDD
MODA1/IRQC
MODB1/IRQD
MODC1/NMI_1
MODD1/PG2
FSR_2
SCKR_2
SCKT_2
FST_2
SDO0_2
SDO1_2
IO_GND
IO_VDD
SDO0_3
SDO1_3
SS/HA2
HREQ/PH4
SCK/SCL
MOSI/HA0
MISO/SDA
SS_1/HA2_1
HREQ_1/PH4_1
SCK_1/SCL_1
MOSI_1/HA0_1
MISO_1/SDA_1
RESET
CORE_GND
CORE_VDD
For the pinout of the DSP56721 144-pin plastic LQFP package, see Figure 5.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DSP56721
144-Pin
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
IO_GND
IO_VDD
WDT
PIINT/NMI
TDO
TDI
TCK
TMS
SCKR_1
FSR_1
SCKT_1
FST_1
SDO0_1
SDO1_1
IO_GND
IO_VDD
CORE_GND
CORE_VDD
SDO0
SDO1
SDO4/SDI1
SDO5/SDI0
SPDIFOUT1/H12/HAD12
SPDIFIN1/H8/HAD8
HACK/HRRQ
HOREQ/HTRQ
IO_GND
IO_VDD
EXTAL
XTAL
PLLP_GND
PLLD_GND
PLLD_VDD
PLLA_GND
PLLA_VDD
PLLP_VDD
HAS/HA0
HA1/HA8
HA2/HA9
HRW/HRD
HDS/HWR
HCS/HA10
IO_VDD
IO_GND
FST_3
HCKT_3
SDO2_1/SDI3_1
SDO3_1/SDI2_1
CORE_VDD
CORE_GND
SDO4_1/SDI1_1
SDO5_1/SDI0_1
FSR
SCKR
HCKR
SCKT
IO_VDD
IO_GND
CORE_VDD
CORE_GND
FST
HCKT
SDO2/SDI3
SDO3/SDI2
IO_GND
IO_VDD
H0/HAD0
H1/HAD1
H2/HAD2
H3/HAD3
H4/HAD4
H5/HAD5
37
38
38
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TIO0/H15/HAD15
PG18/HDI_SEL
IO_GND
TIO0_1/H18/HAD18
CORE_VDD
CORE_GND
SDO2_3/SDI3_3
SDO3_3/SDI2_3
SDO4_3/SDI1_3
SDO5_3/SDI0_3
IO_VDD
IO_GND
CORE_VDD
CORE_GND
SDO2_2/SDI3_2
SDO3_2/SDI2_2
SDO4_2/SDI1_2
SDO5_2/SDI0_2
HCKR_3
FSR_3
SCKR_3
SCKT_3
IO_VDD
IO_GND
H6/HAD6
H7/HAD7
SPDIFIN2/H9/HAD9
SPDIFIN3/H10/HAD10
SPDIFIN4/H11/HAD11
SPDIFOUT2/H13/HAD13
SPLOCK/H14/HAD14
GND
GND
GND
GND
GND
Figure 5. DSP56721 144-Pin Package Pinout
1.4
Pin Multiplexing
Many pins are multiplexed. For more about pin multiplexing, refer to the DSP56720/DSP56721 Reference Manual
(DSP56720RM).
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
7
2
Electrical Characteristics
For electrical characteristics, see Table 2.
Table 2. Electrical Characteristics
For
See
Section 2.1, “Chip-Level Conditions”
Section 2.2, “Module-Level Specifications”
2.1
on page 8
on page 17
Chip-Level Conditions
For a summary of chip-level conditions in this section, see Table 3.
Table 3. Chip-Level Conditions
For
See
Section 2.1.1, “Maximum Ratings”
2.1.1
on page 8
Section 2.1.2, “Thermal Characteristics”
on page 10
Section 2.1.3, “Power Requirements”
on page 10
Section 2.1.4, “DC Electrical Characteristics”
on page 11
Section 2.1.5, “AC Electrical Characteristics”
on page 12
Section 2.1.6, “Internal Clocks”
on page 12
Section 2.1.7, “External Clock Operation”
on page 13
Section 2.1.8, “Reset, Stop, Mode Select, and Interrupt Timing”
on page 14
Maximum Ratings
For maximum ratings, see Table 4.
CAUTION
This device contains circuitry protecting against damage due to high static voltage or
electrical fields. However, normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled
to an appropriate logic voltage level (for example, either GND or VDD). The suggested
value for a pull-up or pull-down resistor is 4.7 kΩ.
NOTE
In the calculation of timing requirements, adding a maximum value of one specification to
a minimum value of another specification does not yield a reasonable sum. A maximum
specification is calculated using a worst case variation of process parameter values in one
direction. The minimum specification is calculated using the worst case for the same
parameters in the opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another specification;
adding a maximum to a minimum represents a condition that can never exist.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
8
Freescale Semiconductor
Table 4. Maximum Ratings
Rating1
Symbol
Value1, 2
Unit
VCORE_VDD,
VPLLD_VDD
-0.3 to + 1.26
V
VPLLP_VDD,
VIO_VDD,
VPLLA_VDD,
-0.3 to + 4.0
V
Tr
10
ms
Input Voltage per pin excluding VDD and GND
VIN
GND -0.3 to 5.5V
V
Current drain per pin excluding VDD and GND
(Except for pads listed below)
I
12
mA
Ilsync_out
16
mA
LCLK
Ilclk
16
mA
LALE
Iale
16
mA
TDO
IJTAG
24
mA
TJ
-40 to +125
TSTG
-65 to +150
°C
°C
ESD protected voltage (Human Body Model)
–
2000
V
ESD protected voltage (Charged Device)
• All pins
• Corner pins
–
Supply Voltage
Maximum CORE_VDD power supply ramp time4
LSYNC_OUT
Operating temperature range3
Storage temperature
V
500
750
Notes:
1.
2.
3.
4.
GND = 0 V, TJ = -40°C to 125°C, CL = 50pF
Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the
maximum rating may affect device reliability or cause permanent damage to the device.
Operating temperature qualified for consumer applications. TJ = TA + qJA x Power. Variables used were
Core Current = 900mA, I/O Current = 200mA, Core Voltage = 1.1 V, I/O Voltage = 3.6 V, TA = 105°C.
If the power supply ramp to full supply time is longer than 10 ms, the POR circuitry will not operate correctly, causing erroneous
operation.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
9
2.1.2
Thermal Characteristics
For thermal characteristics, see Table 5.
Table 5. Thermal Characteristics
Characteristic
Board Type
Natural Convection, Junction-to-ambient thermal resistance1,2
Single layer board
(1s)
Four layer board
(2s2p)
Junction-to-case thermal resistance3
Symbol
RθJA or θJA
LQFP Values
Unit
57 for 80 QFP
49 for 144 QFP
°C/W
44 for 80 QFP
40 for 144 QFP
°C/W
RθJC or θJC 10 for 80 QFP
9 for 144 QFP
–
°C/W
Notes:
1.
2.
3.
2.1.3
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
Thermal resistance between the die and the case top surface as measured by the cold plate method
(MIL SPEC-883 Method 1012.1).
Power Requirements
To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode
as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins.
IO_VDD
Core_VDD
External
Schottky
Diode
Figure 6. Prevent High Current Conditions by Using External Schottky Diode
If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead
of Core_VDD, as shown in Figure 7.
Core_VDD
IO_VDD
Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD
For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,
as shown in Figure 8.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
10
Freescale Semiconductor
Tr
1.0V
Core_VDD 0 V
Tr must be < 10 ms
Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD
2.1.4
DC Electrical Characteristics
For DC electrical characteristics, see Table 6.
Table 6. DC Electrical Characteristics
Characteristics
Symbol
Min
Typ
Max
Unit
Supply voltages
• Core (Core_VDD)
• PLL (PLLD_VDD, PLLD1_VDD)
VDD
0.9
1.0
1.1
V
Supply voltages
• I/O (IO_VDD)
• PLL (PLLP_VDD, PLLP1_VDD)
• PLL (PLLA_VDD, PLLA1_VDD)
VDDIO
3.14
3.3
3.46
V
VIH
2.0
–
VIO_VDD+2V
V
Input high voltage
Note: To avoid a high current condition and possible system damage, all 3.3 volt supplies must rise before the 1.0 volt
supplies rise.
Input low voltage
VIL
-0.3
–
0.8
V
Input leakage current
IIN
–
–
± 84
μA
Clock pin Input Capacitance (EXTAL)
CIN
High impedance (off-state) input current (@ 3.3 V or
0 V)
ITSI
-10
–
10
μA
Output high voltage
IOH = -12 mA
LSYNC_OUT, LALE, LCLK Pins IOH = -16 mA, TDO
Pin IOH = -24 mA
VOH
2.4
–
–
V
Output low voltage
IOL = 12 mA
LSYNC_OUT, LALE, LCLK Pins IOL = 16 mA, TDO
Pins IOL = 24 mA
VOL
–
–
0.4
V
18
pF
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
11
Table 6. DC Electrical Characteristics (Continued)
Characteristics
Symbol
Min
Typ
Max
Unit
Internal supply current1 (core only) at internal clock of
200 MHz
• In Normal mode
ICCI
–
190
780
mA
• In Wait mode
ICCW
–
90
680
mA
mode2
ICCS
–
50
640
mA
Input capacitance
CIN
–
–
10
pF
• In Stop
Notes:
1.
2.
2.1.5
The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In order
to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive
DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This
reflects typical DSP applications. Typical internal supply current is measured with VCORE_VDD = 1.0V, VDD_IO = 3.3V at TJ = 25°C.
Maximum internal supply current is measured with VCORE_VDD = 1.10V, VIO_VDD) = 3.6V at TJ = 125°C.
In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float).
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8 V and a VIH
minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50% point of the respective input signal’s transition. DSP56720/DSP56721 output levels are
measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively.
2.1.6
Internal Clocks
Internal clock characteristics are listed in Table 7.
Table 7. Internal Clocks
No.
Characteristics
Symbol
Min
Typ
Max
Unit
2
–
8
MHz
Fref = Fin/NR
400
MHz
Fvco = (Fin * NF)/NR
1
Comparison Frequency
Fref
2
Input Clock Frequency
Fin
3
PLL VCO Frequency
4
5
Output Clock Frequency
• with PLL enabled
• with PLL disabled
Duty Cycle
Fvco
[1]
Max = 200 MHz
200
Fout
–
MHz
–
25
–
–
Condition
40
200
200
50
60
Fout= Fvco/NO
Fout = Fin
%
Fvco=
200 MHz – 400 MHz
Notes:
Fin = External frequency, NF = Multiplication Factor, NR = Predivision Factor, NO = Output Divider
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
12
Freescale Semiconductor
2.1.7
External Clock Operation
The DSP56720/DSP56721 system clock is derived from the on-chip oscillator or is externally supplied. To use the on-chip
oscillator, connect a crystal and associated resistor/capacitor components to EXTAL and XTAL; see the example in Figure 9.
EXTAL
Suggested component values:
XTAL
Fosc = 24.576 MHz
R = 1 M ±10%
C (EXTAL)= 18 pF
C (XTAL) = 18 pF
R
XTAL1
C
Calculations are for a 5 – 30 MHz crystal with the following parameters:
• Shunt capacitance (C0) of 10 pF – 12 pF
• Series resistance 40 Ohm
• Drive level of 10 μW
C
Figure 9. Using the On-Chip Oscillator
If the DSP56720/DSP56721 system clock is an externally supplied square wave voltage source, it is connected to EXTAL
(Figure 10). When the external square wave source is connected to EXTAL, the XTAL pin is not used.
VIH
Midpoint
EXTAL
VIL
ETH
ETL
1
3
Note:
2
ETC
The midpoint is 0.5 (VIH + VIL).
Figure 10. External Clock Timing
Table 8. Clock Operation
No.
1
Characteristics
EXTAL input high 1
(40% to 60% duty cycle)
• Crystal oscillator
• Square wave input
Symbol
Min
Max
Units
Eth
16.67
2.5
100
inf
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
13
Table 8. Clock Operation (Continued)
No.
2
3
4
Characteristics
Symbol
Min
Max
Units
Etl
16.67
2.5
100
inf
ns
EXTAL cycle time
• With PLL disabled
• With PLL enabled
Etc
5
33.3
inf
500
ns
Instruction cycle time
• With PLL disabled
• With PLL enabled
Tc
5.00
5.00
inf
5120
ns
EXTAL input low1
(40% to 60% duty cycle)
• Crystal oscillator
• Square wave input
Notes:
1.
2.
3.
2.1.8
Measured at 50% of the input transition.
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock
high or low time required for correct operation, however, remains the same at lower operating frequencies;
therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle
as long as the minimum high time and low time requirements are met.
A valid clock signal must be applied to the EXTAL pin within 3 ms of the DSP56720/DSP56721 being
powered up.
Reset, Stop, Mode Select, and Interrupt Timing
For reset, stop, mode select, and interrupt timing, see Table 9.
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
No.
Characteristics
Expression
Min
Max
Unit
–
–
11
ns
10
Delay from RESET assertion to all pins at reset value3
11
Required RESET duration4
• Power on, external clock generator, PLL disabled
• Power on, external clock generator, PLL enabled
2 x TC
2 x TC
10
10
–
–
ns
ns
Syn reset deassert delay time
• Minimum
2 × TC
10
–
ns
(2 x TC) + TLOCK
200
–
us
13
• Maximum (PLL enabled)
14
Mode select setup time
–
10.0
–
ns
15
Mode select hold time
–
10.0
–
ns
16
Minimum edge-triggered interrupt request assertion width
–
4
–
ns
17
Minimum edge-triggered interrupt request deassertion width
–
4
–
ns
18
Delay from interrupt trigger to interrupt code execution
10 × TC + 4
54
–
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
14
Freescale Semiconductor
Table 9. Reset, Stop, Mode Select, and Interrupt Timing Parameters
No.
Characteristics
Expression
Min
Max
Unit
19
Duration of level sensitive IRQA assertion to ensure interrupt service
(when exiting Stop)1, 2, 3
• PLL is active during Stop and Stop delay is enabled (OMR Bit 6 = 0)
(128K × TC)
655
–
μs
• PLL is active during Stop and Stop delay is not enabled (OMR Bit 6 =
1)
25 × TC
125
–
ns
• PLL is not active during Stop and Stop delay is enabled (OMR Bit 6 =
0)
(128K x TC) +
TLOCK
855
–
μs
• PLL is not active during Stop and Stop delay is not enabled (OMR Bit
6 = 1)
(25 x TC) + TLOCK
200
–
μs
10 x TC + 3.8
–
53.8
ns
20
• Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to
general-purpose transfer output valid caused by first interrupt
instruction execution1
21
Interrupt Requests Rate1
• ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1, Timer, Timer_1
12 x TC
–
60.0
ns
• DMA
8 x TC
–
40.0
ns
• IRQ, NMI (edge trigger)
8 x TC
–
40.0
ns
• IRQ (level trigger)
12 x TC
–
60.0
ns
DMA Requests Rate
• Data read from ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
6 x TC
–
30.0
ns
• Data write to ESAI, ESAI_1, ESAI_2, ESAI_3, SHI, SHI_1
7 x TC
–
35.0
ns
• Timer, Timer_1
2 x TC
–
10.0
ns
• IRQ, NMI (edge trigger)
3 x TC
–
15.0
ns
22
Notes:
1.
When using fast interrupts and when IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to
prevent multiple interrupt service. To avoid these timing restrictions, the Edge-triggered mode is recommended when using fast
interrupts. Long interrupts are recommended when using Level-sensitive mode.
2.
For PLL disable, if using an external clock (PCTL Bit 13 = 1), no stabilization delay is required and recovery time will be defined by
the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shut down during Stop. Recovering from Stop requires the PLL to get
locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 200 μs.
3.
Periodically sampled and not 100% tested.
4.
RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active and valid. When
VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been yet met, the device circuitry will
be in an uninitialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the
shortest possible duration.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
15
VIH
RESET
11
13
10
All Pins
Reset Value
Figure 11. Reset Timing Diagram
a) First Interrupt Instruction Execution
19
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
18
b) General Purpose I/O
General
Purpose
I/O
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
20
Figure 12. External Fast Interrupt Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
16
Freescale Semiconductor
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
16
IRQA, IRQB,
IRQC, IRQD,
NMI,
NMI_1
17
Figure 13. External Interrupt Timing Diagram (Negative Edge-Triggered)
VIH
RESET
14
15
MODA, MODB,
MODC, MODD,
PINIT
VIH
VIH
VIL
VIL
IRQA, IRQB,
IRQC,IRQD, NMI
Figure 14. MODE Select Set-Up and Hold Timing Diagram
2.2
Module-Level Specifications
For a summary of the module-level specifications in this section, see Table 10.
Table 10. Module-Level Specifications
For
See
Section 2.2.1, “Serial Host Interface (SHI) SPI Protocol Timing”
2C
Section 2.2.2, “Serial Host Interface (SHI) I
2C
Section 2.2.3, “Programming the SHI I
Protocol Timing”
Serial Clock”
on page 18
on page 24
on page 26
Section 2.2.4, “Enhanced Serial Audio Interface (ESAI) Timing”
on page 27
Section 2.2.5, “Timer Timing”
on page 32
Section 2.2.6, “GPIO Timing”
on page 32
Section 2.2.7, “JTAG Timing”
on page 33
Section 2.2.8, “Watchdog Timer Timing”
on page 35
Section 2.2.9, “Host Data Interface (HDI24) Timing”
on page 35
Section 2.2.10, “S/PDIF Timing”
on page 42
Section 2.2.11, “EMC Timing (DSP56720 only)”
on page 43
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
17
2.2.1
Serial Host Interface (SHI) SPI Protocol Timing
See Table 11 for SHI SPI protocol timing parameters and Figure 15, Figure 16, Figure 17, and Figure 18 for timing diagrams.
Table 11. Serial Host Interface SPI Protocol Timing Parameters
No.
23
Characteristics1,3,4
Minimum serial clock cycle = tSPICC(min)
XX Tolerable Spike width on data or clock in
24
Serial clock high period
Mode
Filter Mode
Expression
Min
Max
Unit
Master/Slave
Bypassed
10 x TC + 9
59.0
–
ns
Very Narrow
10 x TC + 9
59.0
–
ns
Narrow
10 x TC + 133
183.0
–
ns
Wide
10 x TC + 333
373.0
–
ns
Bypassed
–
–
0
ns
Very Narrow
–
–
10
ns
Narrow
–
–
50
ns
Wide
–
–
100
ns
Bypassed
0.5 x (tSPICC -10)
33.0
–
ns
Very Narrow
0.5 x (tSPICC -10)
33.0
–
ns
Narrow
0.5 x (tSPICC -10)
86.0
–
ns
Wide
0.5 x (tSPICC -10)
121.5
–
ns
Bypassed
2.5 x TC + 12
22.5
–
ns
Very Narrow
2.5 x TC + 12
22.5
–
ns
Narrow
2.5 x TC + 102
114.5
–
ns
Wide
2.5 x TC + 189
201.5
–
ns
Bypassed
0.5 x (tSPICC -10)
33.0
–
ns
Very Narrow
0.5 x (tSPICC -10)
33.0
–
ns
Narrow
0.5 x (tSPICC -10)
86.0
–
ns
Wide
0.5 x (tSPICC -10)
121.5
–
ns
Bypassed
2.5 x TC + 12
22.5
–
ns
Very Narrow
2.5 x TC + 12
22.5
–
ns
Narrow
2.5 x TC + 102
114.5
–
ns
Wide
2.5 x TC + 189
201.5
–
ns
–
–
–
–
–
–
–
5
ns
ns
–
Master
Slave
25
Serial clock low period
Master
Slave
26
Serial clock rise/fall time
Master
Slave
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
18
Freescale Semiconductor
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
Characteristics1,3,4
No.
27
SS assertion to first SCK edge
Mode
Filter Mode
Expression
Min
Max
Unit
Slave
Bypassed
3.5 x TC+15
32.5
–
ns
Very Narrow
3.5 x TC+5
22.5
–
ns
Narrow
–
0
–
ns
Wide
–
0
–
ns
Bypassed
–
10
–
ns
Very Narrow
–
0
–
ns
Narrow
–
0
–
ns
Wide
–
0
–
ns
Bypassed
–
12
–
ns
Very Narrow
–
22
–
ns
Narrow
–
100
–
ns
Wide
–
200
–
ns
Bypassed
–
0
–
ns
Very Narrow
–
0
–
ns
Narrow
–
0
–
ns
Wide
–
0
–
ns
Bypassed
2 x TC + 10
10
–
ns
Very Narrow
2 x TC + 30
40
–
ns
Narrow
2 x TC + 60
70
–
ns
Wide
–
100.0
–
ns
CPHA = 0
CPHA = 1
28
29
30
Slave
Last SCK edge to SS not asserted
Data input valid to SCK edge (data input
set-up time)
SCK last sampling edge to data input not
valid
Slave
Master
/Slave
Master
/Slave
31
SS assertion to data out active
Slave
–
–
5
–
ns
32
SS deassertion to data high impedance2
Slave
–
–
–
9
ns
33
SCK edge to data out valid
(data out delay time)
Master
/Slave
Bypassed
–
–
46.2
ns
Very Narrow
–
–
270
ns
Narrow
–
–
376
ns
Wide
–
–
521
ns
Bypassed
–
11.67
–
ns
Very Narrow
–
15
–
ns
Narrow
–
55
–
ns
Wide
–
105
–
ns
–
–
–
14.0
ns
34
35
SCK edge to data out not valid
(data out hold time)
SS assertion to data out valid
(CPHA = 0)
Master
/Slave
Slave
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
19
Table 11. Serial Host Interface SPI Protocol Timing Parameters (Continued)
No.
Characteristics1,3,4
Mode
Filter Mode
Expression
Min
Max
Unit
36
First SCK sampling edge to HREQ output
deassertion
Slave
Bypassed
–
45
–
ns
Very Narrow
–
55
–
ns
Narrow
–
95
–
ns
Wide
–
145
–
ns
Bypassed
–
50.0
–
ns
Very Narrow
–
60.0
–
ns
Narrow
–
100.0
–
ns
Wide
–
150.0
–
ns
37
Last SCK sampling edge to HREQ output
not deasserted (CPHA = 1)
Slave
38
SS deassertion to HREQ output not
deasserted (CPHA = 0)
Slave
–
–
45.0
–
ns
39
SS deassertion pulse width (CPHA = 0)
Slave
–
TC + 6
11.0
–
ns
40
HREQ in assertion to first SCK edge
Master
–
0.5 x TSPICC + 3.0 x
TC + 43
96.0
–
ns
41
HREQ in deassertion to last SCK sampling
edge (HREQ in set-up time) (CPHA = 1)
Master
–
–
0
–
ns
42
First SCK edge to HREQ in not asserted
(HREQ in hold time)
Master
–
–
0
–
ns
43
HREQ assertion width
Master
–
3.0 x TC
15
–
ns
Notes:
1.
2.
3.
4.
5.
VCORE_VDD = 1.0± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.
Periodically sampled, not 100% tested.
All times assume noise free inputs.
All times assume internal clock frequency of 200 MHz.
SHI_1 specs match those of SHI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
20
Freescale Semiconductor
SS
(Input)
25
23
24
26
26
SCK (CPOL = 0)
(Output)
24
23
26
25
26
SCK (CPOL = 1)
(Output)
29
MISO
(Input)
30
LSB
Valid
MSB
Valid
34
33
MOSI
(Output)
30
29
MSB
40
LSB
42
HREQ
(Input)
43
Figure 15. SPI Master Timing Diagram (CPHA = 0)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
21
SS
(Input)
25
23
24
26
26
SCK (CPOL = 0)
(Output)
24
26
25
SCK (CPOL = 1)
(Output)
23
26
29
29
30
MISO
(Input)
30
MSB
Valid
LSB
Valid
33
MOSI
(Output)
34
MSB
LSB
40
41
42
HREQ
(Input)
43
Figure 16. SPI Master Timing Diagram (CPHA = 1)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
22
Freescale Semiconductor
SS
(Input)
25
23
24
26
28
26
39
SCK (CPOL = 0)
(Input)
27
24
23
26
25
26
SCK (CPOL = 1)
(Input)
35
33
34
31
MISO
(Output)
34
32
MSB
LSB
29
29
30
MOSI
(Input)
MSB
Valid
30
LSB
Valid
36
38
HREQ
(Output)
Figure 17. SPI Slave Timing Diagram (CPHA = 0)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
23
SS
(Input)
25
23
24
26
28
26
SCK (CPOL = 0)
(Input)
27
24
26
25
26
SCK (CPOL = 1)
(Input)
33
MISO
(Output)
33
34
31
32
MSB
LSB
29
29
30
MOSI
(Input)
30
MSB
Valid
LSB
Valid
37
36
HREQ
(Output)
Figure 18. SPI Slave Timing Diagram (CPHA = 1)
Serial Host Interface (SHI) I2C Protocol Timing
2.2.2
See Table 12 for SHI I2C protocol timing parameters and Figure 19 for the timing diagram.
Table 12. SHI I2C Protocol Timing Parameters
Standard I2C
No.
Characteristics1,2,3,4,5
Tolerable Spike Width on SCL or SDA
Filters Bypassed
Very Narrow Filters enabled
Narrow Filters enabled
Wide Filters enabled.
Symbol/
Expression
Standard
Fast-Mode
Unit
Min
Max
Min
Max
–
–
–
–
0
10
50
100
–
–
–
–
0
10
50
100
ns
ns
ns
ns
–
44
SCL clock frequency
FSCL
–
100
–
400
kHz
44
SCL clock cycle
TSCL
10
–
2.5
–
μs
45
Bus free time
TBUF
4.7
–
1.3
–
μs
46
Start condition set-up time
TSUSTA
4.7
–
0.6
–
μs
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
24
Freescale Semiconductor
Table 12. SHI I2C Protocol Timing Parameters (Continued)
Standard I2C
Characteristics1,2,3,4,5
No.
Symbol/
Expression
Standard
Fast-Mode
Unit
Min
Max
Min
Max
THD;STA
4.0
–
0.6
–
μs
47
Start condition hold time
48
SCL low period
TLOW
4.7
–
1.3
–
μs
49
SCL high period
THIGH
4.0
–
1.3
–
μs
50
SCL and SDA rise time
TR
–
5.0
–
5.0
ns
51
SCL and SDA fall time
TF
–
5.0
–
5.0
ns
52
Data set-up time
TSU;DAT
250
–
100
–
ns
53
Data hold time
THD;DAT
0.0
–
0.0
0.9
μs
54
DSP clock frequency
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
10.6
10.6
11.8
13.1
–
–
–
–
28.5
28.5
39.7
61.0
–
–
–
–
MHz
MHz
MHz
MHz
FOSC
55
SCL low to data out valid
TVD;DAT
–
3.4
–
0.9
μs
56
Stop condition setup time
TSU;STO
4.0
–
0.6
–
μs
57
HREQ in deassertion to last SCL edge
(HREQ in set-up time)
tSU;RQI
0.0
–
0.0
–
ns
58
First SCL sampling edge to HREQ output
deassertion2
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
–
–
–
–
50.0
70.0
250.0
150.0
–
–
–
–
50.0
70.0
150.0
250.0
ns
ns
ns
ns
40
50
90
140
–
–
–
–
40
50
90
140
–
–
–
–
ns
ns
ns
ns
4327
4317
4282
4227
–
–
–
–
927
917
877
827
–
–
–
–
ns
ns
ns
ns
0.0
–
0.0
–
ns
59
Last SCL edge to HREQ output not
deasserted2
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
60
61
TNG;RQO
4 × TC + 30
4 × TC + 50
4 × TC + 130
4 × TC + 230
TAS;RQO
2 × TC + 30
2 × TC + 40
2 × TC + 80
2 × TC + 130
HREQ in assertion to first SCL edge
• Filters bypassed
• Very Narrow filters enabled
• Narrow filters enabled
• Wide filters enabled
TAS;RQI
First SCL edge to HREQ is not asserted
(HREQ in hold time.)
tHO;RQI
Notes:
1.
2.
3.
4.
5.
6.
VCORE_VDD = 1.00± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.
Pull-up resistor: R P (min) = 1.5K Ohms.
Capacitive load: C b (max) = 50 pF.
All times assume noise free inputs.
All times assume internal clock frequency of 200 MHz.
SHI_1 specs match those of SHI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
25
2.2.3
Programming the SHI I2C Serial Clock
The programmed serial clock cycle, T I2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock
control register).
The expression for T I2CCP is
T I2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
Eqn. 1
where
— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed
divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be
selected.
In I2C mode, the user may select a value for the programmed serial clock cycle from
6 × TC (if HDM[7:0] = $02 and HRS = 1)
Eqn. 2
4096 × TC (if HDM[7:0] = $FF and HRS = 0)
Eqn. 3
to
The programmed serial clock cycle (TI2CCP ) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as
shown in Equation 4.
TI2CCP + 3 × TC + 45ns + TR
(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)
Eqn. 4
44
46
49
48
SCL
50
SDA
Stop
53
51
45
52
Start
MSB
47
60
LSB
58
61
55
ACK
Stop
56
57
59
HREQ
Figure 19. I2C Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
26
Freescale Semiconductor
2.2.4
Enhanced Serial Audio Interface (ESAI) Timing
See Table 13 For ESAI timing parameters and Figure 20, Figure 21, Figure 22, and Figure 23 for timing diagrams.
Table 13. Enhanced Serial Audio Interface Timing Parameters
Characteristics1, 3, 4
No.
62
Clock cycle5
63
Clock high period
• For internal clock
Symbol
Expression5
Min
Max
tSSICC
4 × Tc
4 × Tc
20.0
20.0
–
–
i ck
i ck
–
2 × Tc
10
–
–
2 × Tc
10
–
–
Clock low period
• For internal clock
2 × Tc
10
–
–
2 × Tc
10
–
–
ns
ns
• For external clock
64
Condition2 Unit
ns
–
• For external clock
65
SCKR rising edge to FSR out (bl) high
–
–
–
–
17.0
7.0
x ck
i ck a
ns
66
SCKR rising edge to FSR out (bl) low
–
–
–
–
17.0
7.0
x ck
i ck a
ns
67
SCKR rising edge to FSR out (wr) high6
–
–
–
–
19.0
9.0
x ck
i ck a
ns
68
SCKR rising edge to FSR out (wr) low6
–
–
–
–
19.0
9.0
x ck
i ck a
ns
69
SCKR rising edge to FSR out (wl) high
–
–
–
–
16.0
6.0
x ck
i ck a
ns
70
SCKR rising edge to FSR out (wl) low
–
–
–
–
17.0
7.0
x ck
i ck a
ns
71
Data in setup time before SCKR (SCK in synchronous
mode) falling edge
–
–
12.0
19.0
–
–
x ck
i ck
ns
72
Data in hold time after SCKR falling edge
–
–
3.5
9.0
–
–
x ck
i ck
ns
73
FSR input (bl, wr) high before SCKR falling edge 6
–
–
2.0
12.0
–
–
x ck
i ck a
ns
74
FSR input (wl) high before SCKR falling edge
–
–
2.0
12.0
–
–
x ck
i ck a
ns
75
FSR input hold time after SCKR falling edge
–
–
2.5
8.5
–
–
x ck
i ck a
ns
76
Flags input setup before SCKR falling edge
–
–
0.0
19.0
–
–
x ck
i ck s
ns
77
Flags input hold time after SCKR falling edge
–
–
6.0
0.0
–
–
x ck
i ck s
ns
78
SCKT rising edge to FST out (bl) high
–
–
–
–
18.0
8.0
x ck
i ck
ns
79
SCKT rising edge to FST out (bl) low
–
–
–
–
20.0
10.0
x ck
i ck
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
27
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
No.
Characteristics1, 3, 4
Symbol
Expression5
Min
Max
Condition2 Unit
80
SCKT rising edge to FST out (wr) high6
–
–
–
–
20.0
10.0
x ck
i ck
ns
81
SCKT rising edge to FST out (wr) low6
–
–
–
–
22.0
12.0
x ck
i ck
ns
82
SCKT rising edge to FST out (wl) high
–
–
–
–
19.0
9.0
x ck
i ck
ns
83
SCKT rising edge to FST out (wl) low
–
–
–
–
20.0
10.0
x ck
i ck
ns
84
SCKT rising edge to data out enable from high
impedance
–
–
–
–
22.0
17.0
x ck
i ck
ns
85
SCKT rising edge to transmitter #0 drive enable
assertion
–
–
–
–
17.0
11.0
x ck
i ck
ns
86
SCKT rising edge to data out valid
–
–
–
–
18.0
13.0
x ck
i ck
ns
87
SCKT rising edge to data out high impedance7
–
–
–
–
21.0
16.0
x ck
i ck
ns
88
SCKT rising edge to transmitter #0 drive enable
deassertion7
–
–
–
–
14.0
9.0
x ck
i ck
ns
89
FST input (bl, wr) setup time before SCKT falling edge6
–
–
2.0
18.0
–
–
x ck
i ck
ns
90
FST input (wl) setup time before SCKT falling edge
–
–
2.0
18.0
–
–
x ck
i ck
ns
91
FST input hold time after SCKT falling edge
–
–
4.0
5.0
–
–
x ck
i ck
ns
92
FST input (wl) to data out enable from high impedance
–
–
–
21.0
–
ns
93
FST input (wl) to transmitter #0 drive enable assertion
–
–
–
14.0
–
ns
94
Flag output valid after SCKT rising edge
–
–
–
–
14.0
9.0
x ck
i ck
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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Freescale Semiconductor
Table 13. Enhanced Serial Audio Interface Timing Parameters (Continued)
Characteristics1, 3, 4
No.
Symbol
Expression5
Min
Max
Condition2 Unit
95
HCKR/HCKT clock cycle
–
2 x TC
10
–
–
ns
96
HCKT input rising edge to SCKT output
–
–
–
18.0
–
ns
97
HCKR input rising edge to SCKR output
–
–
–
18.0
–
ns
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
VCORE_VDD = 1.00 ± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF.
i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(Asynchronous implies that SCKT and SCKR are two different clocks.)
i ck s = internal clock, synchronous mode
(Synchronous implies that SCKT and SCKR are the same clock.)
bl = bit length
wl = word length
wr = word length relative
SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
For the internal clock, the external clock cycle is defined by Tc and the ESAI control register.
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal
waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit
clock of the first word in frame.
Periodically sampled and not 100% tested.
ESAI_1, ESAI_2, ESAI_3 specs match those of ESAI.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
29
62
63
64
SCKT
(Input/Output)
78
79
FST (Bit)
Out
82
83
FST (Word)
Out
86
86
84
87
First Bit
Data Out
Last Bit
93
Transmitter #0
Drive Enable
(Internal Signal)
89
85
88
91
FST (Bit) In
92
91
90
FST (Word) In
94
See Note
Flags Out
Note: In network mode, output flag transitions can occur at the start of each time slot within the
frame. In normal mode, the output flag state is asserted for the entire frame period.
Figure 20. ESAI Transmitter Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
30
Freescale Semiconductor
62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
First Bit
Last Bit
75
73
FSR (Bit)
In
74
75
FSR (Word)
In
76
77
Flags In
Figure 21. ESAI Receiver Timing Diagram
HCKT
SCKT
(Output)
95
96
Figure 22. ESAI HCKT Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
31
HCKR
95
SCKR
(Output)
97
Figure 23. ESAI HCKR Timing
2.2.5
Timer Timing
See Table 14 for timer timing parameters and Figure 24 for the timing diagram.
Table 14. Timer Timing Parameters
No.
Characteristics
Expression
Unit
Min
Max
98
TIO Low
2 × TC + 2.0
12.0
–
ns
99
TIO High
2 × TC + 2.0
12.0
–
ns
Notes:
1.
2.
VCORE_VDD = 1.00 V ± 0.10 V; TJ = -40°C to 125°C, CL = 50 pF
TIMER_1 specs match those of TIMER
TIO
98
99
Figure 24. TIO Timer Event Input Restrictions Diagram
2.2.6
GPIO Timing
See Table 15 for general purpose input and output (GPIO) timing and Figure 25 for the timing diagram.
Table 15. GPIO Timing Parameters
No.
100
101
102
Characteristics1
Fsys edge to GPIO out valid (GPIO out delay time)2
2
104
Minimum GPIO pulse high width
Max
Unit
–
–
7
ns
–
–
7
ns
–
2
–
ns
time)2
–
0
–
ns
2 x TC
10
–
ns
Fsys In valid to EXTAL edge (GPIO in set-up time)
Fsys edge to GPIO in not valid (GPIO in hold
Min
2
Fsys edge to GPIO out not valid (GPIO out hold time)
103
Expression
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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Freescale Semiconductor
Table 15. GPIO Timing (Continued)Parameters
Characteristics1
No.
Expression
Min
Max
Unit
2 x TC
10
–
ns
105
Minimum GPIO pulse low width
106
GPIO out rise time
–
–
13.0
ns
107
GPIO out fall time
–
–
13.0
ns
Notes:
1.
VCORE_VDD = 1.0 V ± 0.10 V; TJ = -40°C to 125°C; CL = 50 pF
Fsys
100
101
GPIO
(Output)
102
GPIO
Input)
103
Valid
GPIO
(Output)
104
106
105
107
Figure 25. GPIO Timing Diagram
2.2.7
JTAG Timing
See Table 16 for joint test action group (JTAG) timing parameters, and Figure 26, Figure 27, and Figure 28 for timing diagrams.
Table 16. JTAG Timing Parameters
All Frequencies
No.
Characteristics
Unit
Min
Max
–
10.0
MHz
108
TCK frequency of operation (1/(TC × 3); maximum 10 MHz)
109
TCK cycle time in Crystal mode
100.0
–
ns
110
TCK clock pulse width measured at 1.65 V
50.0
–
ns
111
TCK rise and fall times
–
3.0
ns
112
Boundary scan input data setup time
15.0
–
ns
113
Boundary scan input data hold time
24.0
–
ns
114
TCK low to output data valid
–
40.0
ns
115
TCK low to output high impedance
–
40.0
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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33
Table 16. JTAG Timing Parameters (Continued)
All Frequencies
No.
Characteristics
Unit
Min
Max
116
TMS, TDI data setup time
5.0
–
ns
117
TMS, TDI data hold time
25.0
–
ns
118
TCK low to TDO data valid
–
44.0
ns
119
TCK low to TDO high impedance
–
44.0
ns
Notes:
1.
2.
VCORE_VDD = 1.0 V ± 0.10 V; TJ = -40°C to 125°C , CL = 50 pF
All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
109
TCK
(Input)
VIH
110
110
VM
VM
VIL
111
111
Figure 26. Test Clock Input Timing Diagram
TCK
(Input)
VIH
VIL
112
Data
Inputs
113
Input Data Valid
114
Data
Outputs
Output Data Valid
115
Data
Outputs
114
Data
Outputs
Output Data Valid
Figure 27. Debugger Port Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
34
Freescale Semiconductor
VIH
TCK
(Input)
VIL
117
116
TDI
TMS
(Input)
Input Data Valid
118
TDO
(Output)
Output Data Valid
119
TDO
(Output)
118
TDO
(Output)
Output Data Valid
Figure 28. Test Access Port Timing Diagram
2.2.8
Watchdog Timer Timing
For watchdog timer timing, see Table 17.
Table 17. Watchdog Timer Timing Parameters
No.
Characteristics
Expression
Min
Max
Unit
120
Delay from time-out to fall of WDT, WDT_1
2 × Tc
10.0
–
ns
121
Delay from timer clear to rise of WDT, WDT_1
2 × Tc
10.0
–
ns
2.2.9
Host Data Interface (HDI24) Timing
The HDI24 module is only on the DSP56721 device; the DSP56720 device does not have a HDI24 module. Also, only 16 bits
of the HDI24 interface are pinned out on the DSP56721 device. See Table 18 for HDI24 timing and Figure 29, Figure 30,
Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, and Figure 35 for timing diagrams.
Table 18. HDI24 Timing Parameters
Characteristics2
No.
317
Read data strobe assertion width3
HACK read assertion width
318
Read data strobe deassertion width3
HACK read deassertion width
319
Read data strobe deassertion width3 after “Last Data Register” reads4,5,
or between two consecutive CVR, ICR, or ISR reads6
HACK deassertion width after “Last Data Register” reads4,5
200 MHz
Expression
Unit
Min
Max
TC + 9.9
14.9
–
ns
–
9.9
–
ns
2 × TC + 6.6
16.6
–
ns
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
35
Table 18. HDI24 Timing Parameters (Continued)
200 MHz
Characteristics2
No.
Expression
Unit
Min
Max
–
13.2
–
ns
2 × TC + 6.6
16.6
–
ns
• after IVR writes, or
• after TXH:TXM writes (with HBE=0), or
• after TXL:TXM writes (with HBE=1)
–
16.5
–
322
HAS assertion width
–
9.9
–
ns
323
HAS deassertion to data strobe assertion8
–
0.0
–
ns
324
Host data input setup time before write data strobe deassertion7
Host data input setup time before HACK write deassertion
–
9.9
–
ns
325
Host data input hold time after write data strobe deassertion7
Host data input hold time after HACK write deassertion
–
3.3
–
ns
326
Read data strobe assertion to output data active from high impedance3
HACK read assertion to output data active from high impedance
–
3.3
–
ns
327
Read data strobe assertion to output data valid3
HACK read assertion to output data valid
–
–
24.2
ns
328
Read data strobe deassertion to output data high impedance3
HACK read deassertion to output data high impedance
–
–
9.9
ns
329
Output data hold time after read data strobe deassertion3
Output data hold time after HACK read deassertion
–
3.3
–
ns
330
HCS assertion to read data strobe deassertion3
TC + 9.9
14.9
–
ns
331
HCS assertion to write data strobe deassertion
7
–
9.9
–
ns
332
HCS assertion to output data valid
–
–
19.1
ns
333
HCS hold time after data strobe deassertion8
–
0.0
–
ns
334
Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)
–
4.7
–
ns
335
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
–
3.3
–
ns
336
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
strobe assertion8
• Read
–
0
–
ns
• Write
–
4.7
–
337
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
deassertion8
–
3.3
–
ns
338
Delay from read data strobe deassertion to
host request assertion for “Last Data Register” read3, 4, 9
TC
5.0
–
ns
320
Write data strobe assertion width7
HACK write assertion width
321
Write data strobe deassertion width7
HACK write deassertion width
• after ICR, CVR and “Last Data Register” writes4
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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Freescale Semiconductor
Table 18. HDI24 Timing Parameters (Continued)
Characteristics2
No.
200 MHz
Expression
Unit
Min
Max
2 × TC
10.0
–
ns
339
Delay from write data strobe deassertion to
host request assertion for “Last Data Register” write4, 7, 9
340
Delay from data strobe assertion to
host request deassertion for “Last Data Register” read or write (HROD =
0)4, 8, 9
–
–
19.1
ns
341
Delay from data strobe assertion to
host request deassertion for “Last Data Register” read or write (HROD =
1, open drain Host Request)4, 8, 9, 10
–
–
300.0
ns
342
Delay from DMA HACK deassertion to HOREQ assertion
ns
• For “Last Data Register” read4
2 × TC + 19.1
29.1
–
• For “Last Data Register” write4
1 × TC + 19.1
24.1
–
• For other cases
–
0.0
–
343
Delay from DMA HACK assertion to HOREQ deassertion
• HROD = 04
–
–
20.2
ns
344
Delay from DMA HACK assertion to HOREQ deassertion for “Last Data
Register” read or write
• HROD = 1, open drain Host Request4, 10
–
–
300.0
ns
Notes:
1.
2.
3.
4.
5.
In the timing diagrams that follow, the controls pins are drawn as active low. The pin polarity is programmable.
VCC = 1.0 V ± 10%; TJ = –40°C to +125°C; CL = 50 pF.
The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode.
The “last data register” is the register at address $7, which is the last location to be read or written in data transfers.
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without
first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal.
6. This timing is applicable only if two consecutive reads from one of these registers are executed.
7. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
8. The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data
strobe mode.
9. The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode.
10. In this calculation, the host request signal is pulled up by a 4.7 kW resistor in the open-drain mode.
11. HDI24_1 specs match those of HDI24.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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37
317
318
HACK
328
327
329
326
HD23–HD0
HOREQ
Figure 29. HDI24 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0–HA2
336
337
333
330
HCS
317
HRD, HDS
318
328
332
319
327
329
326
HD0–HD23
340
338
341
HOREQ,
HRRQ,
HTRQ
Figure 30. HDI24 Read Timing Diagram, Non-Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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Freescale Semiconductor
HA0–HA2
337
336
331
333
HCS
320
HWR, HDS
321
324
325
HD0–HD23
340
339
341
HOREQ,
HRRQ,
HTRQ
Figure 31. HDI24 Write Timing Diagram, Non-Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
39
HA8–HA10
336
337
322
HAS
323
317
HRD, HDS
334
318
335
319
327
328
329
HAD0–HAD23
Address
Data
326
340
338
341
HOREQ,
HRRQ,
HTRQ
Figure 32. HDI24 Read Timing Diagram, Multiplexed Bus
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
40
Freescale Semiconductor
HA8–HA10
336
322
HAS
323
320
HWR, HDS
334
324
321
335
HAD0–HAD23
325
Address
Data
340
339
341
HOREQ,
HRRQ,
HTRQ
Figure 33. HDI24 Write Timing Diagram, Multiplexed Bus
HOREQ
(Output)
342
343
344
320
HACK
(Input)
321
TXH/M/L
Write
324
325
H0–H23
(Input)
Data
Valid
Figure 34. HDI24 Host DMA Write Timing Diagram
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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HOREQ
(Output)
343
342
342
318
317
RXH
Read
HACK
(Input)
327
328
326
H0-H23
(Output)
329
Data
Valid
Figure 35. HDI24 Host DMA Read Timing Diagram
2.2.10
S/PDIF Timing
See Table 19 for Sony/Philips Digital Interconnect Format (S/PDIF) timing parameters and Figure 36 and Figure 37 for timing
diagrams.
Table 19. S/PDIF Timing Parameters
All Frequency
Characteristics
Symbol
Unit
Min
Max
–
–
0.7
ns
SPDIFOUT1,SPDIFOUT2 output (Load = 50 pf)
• Skew
• Transition Risng
• Transition Falling
–
–
–
–
–
–
1.5
24.2
31.3
ns
SPDIFOUT1, SPDIFOUT2 output (Load = 30 pf)
• Skew
• Transition Risng
• Transition Falling
–
–
–
–
–
–
1.5
13.6
18.0
ns
SRCK period
srckp
40.0
–
ns
SRCK high period
srckph
16.0
–
ns
SRCK low period
srckpl
16.0
–
ns
STCLK period
stclkp
40.0
–
ns
STCLK high period
stclkph
16.0
–
ns
STCLK low period
stclkpl
16.0
–
ns
SPDIFIN1, SPDIFIN2, SPDIFIN3, SPDIFIN4 Skew:
asynchronous inputs, no specs apply
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Freescale Semiconductor
srckp
srckpl
srckph
VM
VM
SRCK
(Output)
Figure 36. S/PDIF SRCK Timing Diagram
stclkp
stclkpl
stclkph
VM
VM
STCLK
(Input)
Figure 37. S/PIDF STCLK Timing Diagram
2.2.11
EMC Timing (DSP56720 only)
The DSP56721 device does not have an EMC module. For EMC timing parameters in DSP56720 devices, see Table 20,
Table 21, and Table 22; for timing diagrams, see Figure 38, Figure 39, and Figure 40.
Table 20. EMC Timing Parameters (EMC PLL Enabled; LCRR[CLKDIV] = 2)
Parameter
Symbol
Min
Max
Unit
Tclk
10
–
ns
Tclk_skew
–
160
ps
Input setup to LSYNC_IN (except LGTA/LUPWAIT)
Tin_s
2
–
ns
Input hold from LSYNC_IN (except LGTA/LUPWAIT)
Tin_h
2
–
ns
LGTA valid time
Tgta
12
–
ns
LUPWAIT valid time
Tupwait
12
–
ns
LALE negedge to LAD(address phase) invaild (address latch
hold time)
Tale_h
3
–
ns
Tale
3.8
–
ns
Output setup from LSYNC_IN (except LAD[23:0] and LALE)
Tout_s
4
–
ns
Output hold from LSYNC_IN (except LAD[23:0] and LALE)
Tout_h
2
–
ns
LAD[23:0] output setup from LSYNC_IN
Tad_s
3.5
–
ns
LAD[23:0] output hold from LSYNC_IN
Tad_h
1.5
–
ns
LSYNC_IN to output high impedance for LAD[23:0]
Tad_z
–
4.3
ns
LCLK cycle time
LCLK skew to LSYNC_OUT
LALE valid time
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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43
Tclk
LCLK
Tclk_skew
LSYNC_OUT
Tsync_in_skew
LSYNC_IN
Tin_s
Tin_h
LAD[23:0] (data)
Tgta
asynchronous input
LGTA
Tupwait
asynchronous input
LUPWAIT
Tout_s
Output Signals
Tout_h
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LCKE/LSDA10/LSDDQM
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
Tad_z
Tad_s
Tad_h
LAD[23:0]
Tale
Tale_h
LALE
Figure 38. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV] = 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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Freescale Semiconductor
Table 21. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Parameter
Symbol
Min
Max
Unit
LCLK cycle time
Tclk
20
–
ns
Input setup to LCLK (except LGTA/LUPWAIT)
Tin_s
8
–
ns
Input hold from LCLK (except LGTA/LUPWAIT)1
Tin_h
-1
–
ns
LGTA valid time
Tgta
22
–
ns
LUPWAIT valid time
Tupwait
22
–
ns
LALE negedge to LAD (address phase) invalid (address latch hold time)
Tale_h
4
–
ns
Tale
14
–
ns
Output setup from LCLK (except LAD[23:0] and LALE)
Tout_s
9
–
ns
Output hold from LCLK (except LAD[23:0] and LALE)
Tout_h
8
–
ns
LAD[23:0] output setup from LCLK
Tad_s
8
–
ns
LAD[23:0] output hold from LCLK
Tad_h
7
–
ns
LCLK to output high impedance for LAD[23:0]
Tad_z
–
9
ns
LALE valid time
Notes:
1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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45
Tclk
LCLK
Tin_s
Tin_h
LAD[23:0] (data)
Tgta
asynchronous input
LGTA
Tupwait
asynchronous input
LUPWAIT
Tout_s
Output Signals
Tout_h
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LCKE/LSDA10/LSDDQM
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
Tad_z
Tad_s
Tad_h
LAD[23:0]
Tale
Tale_h
LALE
Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
Parameter
Symbol
Min
Max
Unit
Tclk
40
–
ns
Tin_s
8
–
ns
Tin_h
-1
–
ns
Tgta
42
–
ns
LUPWAIT valid time
Tupwait
42
–
ns
LALE negedge to LAD (address phase) invalid (address
latch hold time)
Tale_h
5
–
ns
Tale
34
–
ns
Output setup from LCLK (except LAD[23:0] and LALE)
Tout_s
19
–
ns
Output hold from LCLK (except LAD[23:0] and LALE)
Tout_h
18
–
ns
LCLK cycle time
Input setup to LCLK (except LGTA/LUPWAIT)
Input hold from LCLK (except
LGTA/LUPWAIT)1
LGTA valid time
LALE valid time
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Freescale Semiconductor
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued)
Parameter
Symbol
Min
Max
Unit
LAD[23:0] output setup from LCLK
Tad_s
18
–
ns
LAD[23:0] output hold from LCLK
Tad_h
17
–
ns
LCLK to output high impedance for LAD[23:0]
Tad_z
–
19
ns
Notes:
1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
Tclk
LCLK
Tin_s
Tin_h
LAD[23:0] (data)
Tgta
asynchronous input
LGTA
Tupwait
asynchronous input
LUPWAIT
Tout_s
Output Signals
Tout_h
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LCKE/LSDA10/LSDDQM
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
Tad_z
Tad_s
Tad_h
LAD[23:0]
Tale
Tale_h
LALE
Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
47
3
Functional Description and Application Information
See the DSP56720 Reference Manual (DSP56720RM) for detailed functional and applications information.
4
Hardware Design Considerations
For design considerations, also see Section 2.1.3, “Power Requirements.”
5
Ordering Information
Table 23 provides ordering information for both the DSP56720 and DSP56721.
Table 23. Ordering Information
Product
DSP56720
DSP56721
6
ROM
Version
Package
Part Number
A
144-pin plastic LQFP
DSPA56720AG
B
144-pin plastic LQFP
DSPB56720AG
A
144-pin plastic LQFP
DSPA56721AG
B
144-pin plastic LQFP
DSPB56721AG
A
80-pin plastic LQFP
DSPA56721AF
B
80-pin plastic LQFP
DSPB56721AF
Package Information
For the outline drawings of available device packages, see Table 24 and sections 6.1–6.2.
Table 24. Package Outline Drawings
Device
6.1
Package
See
DSP56720
144-pin plastic LQFP
Figure 43 on page 51 and
Figure 44 on page 52
DSP56721
80-pin plastic LQFP
Figure 41 on page 49 and
Figure 42 on page 50
144-pin plastic LQFP
Figure 43 on page 51 and
Figure 44 on page 52
80-Pin Package Outline Drawing
For the 80-pin package outline drawings, see Figure 41 and Figure 42.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
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Freescale Semiconductor
Figure 41. 80-Pin Package Outline Drawing (1 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
49
Figure 42. 80-Pin Package Outline Drawing (2 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
50
Freescale Semiconductor
6.2
144-Pin Package Outline Drawing
For the 144-pin package drawings, see figures Figure 43 and Figure 44.
Figure 43. 144-Pin Package Outline Drawing (1 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
51
Figure 44. 144-Pin Package Outline Drawing (2 of 2)
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
52
Freescale Semiconductor
7
Product Documentation
This Data Sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these
types are available at: http://www.freescale.com. Documentation is available from a local Freescale Semiconductor, Inc.
distributor, semiconductor sales office, Literature Distribution Center, or through the Freescale DSP home page on the Internet
(the source for the latest information).
The following documents are required for a complete description of the device and are necessary to design properly with the
parts:
DSP56300 Family Manual (document number DSP56300FM). Detailed description of the 56300-family architecture and the
24-bit core processor and instruction set.
DSP56720/DSP56721 Reference Manual (document number DSP56720RM). Detailed description of memory, peripherals, and
interfaces.
DSP56720 Product Brief (DSP56720PB). Brief description of the DSP56720 device.
DSP56721 Product Brief (DSP56721PB). Brief description of the DSP56721 device.
8
Revision History
Table 25 summarizes revisions to this document.
Table 25. Revision History
Revision
Date
1
December 2007
Description
• Initial public release.
SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
53
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Document Number: DSP56720
Rev.1
12/2007
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