Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... M5206EC3 USER'S MANUAL REVISION 1.2 Cadre III A Framework for Solutions 4150 Freidrich Lane Suite D Austin, Texas 78744 Support: (USA only): (800) 410-2031 (512) 326-9455 Email: [email protected] Web: [email protected] For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIMITED WARRANTY Cadre III warrants this product against defects in material and workmanship for a period of sixty (60) days from the original date of purchase. This warranty extends to the original customer only and is in lieu of all other warrants, including implied warranties of merchantability and fitness. In no event will the seller be liable for any incidental or consequential damages. During the warranty period, Cadre III will replace, at no charge, components that fail, provided the product is returned (properly packed and shipped prepaid) to Cadre III at the address below. Dated proof of purchase, such as a copy of the invoice, must be enclosed with the shipment. We will return the shipment prepaid via UPS. Freescale Semiconductor, Inc... This warranty does not apply if, in the opinion of Cadre III, the product has been damaged by accident, misuse, neglect, misapplication, or as a result of service or modification (other than specified in the manual) by others. Please send the board and cables with a complete description of the problem to: Cadre III 4150 Freidrich Lane, Suite D Austin, Texas 78744 HELPFUL INFORMATION Information for the MCF5206e processor and evaluation board is updated frequently at the following URL: http://www.motorola.com/ColdFire. Visit http://www.motorola.com/ColdFire to obtain the follow information. 1. 2. 3. 4. 5. 6. 7. Source code for the assembler Most current User manual for the MCF5206e processor Most current User manual for the M5206EC3 Addendum for the MCF5206e Application notes Example code for the MCF5206e B.O.M. for the M5206EC3 These example files are also available on the web site: S-REC, COFF, ELF. Refer to the electronic version of this user manual at www.motorola.com/ColdFire for the most current information. Want to find out how others are using ColdFire integrated microprocessors in their applications? Sign up at www.wildrice.com and follow the instructions. iii For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Disclaimer The information in this manual has been carefully examined and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any product(s) herein to improve reliability, function, or design. The M5206EC3 board is not intended for use in life and/or property critical applications. Here, such applications are defined to be any situation in which any failure, malfunction, or unintended operation of the board could, directly, or indirectly, threaten life, result in personal injury, or cause damage to property. Although every effort has been made to make the supplied software and its documentation as accurate and functional as possible. Motorola Inc. will not assume responsibility for any damages incurred or generated by this product. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights, if any, or the rights of others. Freescale Semiconductor, Inc... Warning This board generates, uses, and can radiate radio frequency energy and, if not installed properly, may cause interference to radio communications. As temporarily permitted by regulation, it has not been tested for compliance with the limits for class a computing devices pursuant to Subpart J of Part 15 of the FCC rules, which provide reasonable protection against such interference. Operation of this product in a residential area is likely to cause interference, in which case users, at their own expense, will be required to correct the interference. Motorola is a registered trademark of Motorola Inc. IBM PC and IBM AT is registered trademarks of IBM Corp. I2C is a proprietary bus of Philips iv For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc... 1 INTRODUCTION TO THE M5206EC3 BOARD ................................................................................... 1-1 1.1 OVERVIEW........................................................................................................................................ 1-1 1.2 GENERAL HARDWARE DESCRIPTION .......................................................................................... 1-1 1.3 SYSTEM MEMORY........................................................................................................................... 1-2 1.4 SERIAL COMMUNICATION CHANNELS........................................................................................ 1-3 1.5 PARALLEL I/O PORTS...................................................................................................................... 1-3 1.6 PROGRAMMABLE TIMER/COUNTER ............................................................................................ 1-3 1.7 ON-BOARD ETHERNET ................................................................................................................... 1-3 1.8 SYSTEM CONFIGURATION............................................................................................................. 1-3 1.9 INSTALLATION AND SETUP........................................................................................................... 1-4 1.9.1 Unpacking.................................................................................................................................... 1-4 1.9.2 Preparing the Board for Use ........................................................................................................ 1-4 1.9.3 Providing Power to the Board ...................................................................................................... 1-5 1.9.4 Selecting Terminal Baud Rate ...................................................................................................... 1-5 1.9.5 The Terminal Character Format................................................................................................... 1-5 1.9.6 Connecting the Terminal.............................................................................................................. 1-5 1.9.7 Using a Personal Computer as a Terminal ................................................................................... 1-6 1.10 SYSTEM POWER-UP AND INITIAL OPERATION .......................................................................... 1-7 1.11 M5206EC3 JUMPER SETUP .............................................................................................................. 1-8 1.11.1 Jumper JP1 .................................................................................................................................. 1-8 1.11.2 Jumper JP2 - Flash Upper Half/Lower Half Boot......................................................................... 1-8 1.11.3 Jumper J6 and J7 - CPU Power JP6 and 7................................................................................... 1-8 1.12 USING THE BDM............................................................................................................................... 1-8 2 USING THE MONITOR/DEBUG FIRMWARE..................................................................................... 2-9 2.1 WHAT IS DBUG? ............................................................................................................................... 2-9 2.2 OPERATIONAL PROCEDURE ........................................................................................................ 2-10 2.2.1 System Power-Up ....................................................................................................................... 2-10 2.2.2 System Initialization................................................................................................................... 2-11 2.3 TERMINAL CONTROL CHARACTERS.......................................................................................... 2-12 2.4 DBUG COMMAND SET................................................................................................................... 2-13 2.4.1 AS - Assemble ......................................................................................................................... 2-14 2.4.2 BC - Compare Blocks of Memory ............................................................................................... 2-16 2.4.3 BF - Block of Memory Fill ......................................................................................................... 2-17 2.4.4 BM - Block Move ....................................................................................................................... 2-18 2.4.5 BR - Breakpoin .......................................................................................................................... 2-19 2.4.6 BS - Block Search ...................................................................................................................... 2-20 2.4.7 DATA - Data Conversion ........................................................................................................... 2-21 2.4.8 DI - Disassemble........................................................................................................................ 2-22 2.4.9 DL - Download Serial ................................................................................................................ 2-23 2.4.10 DN - Download Network ............................................................................................................ 2-24 2.4.11 Go - Execute .............................................................................................................................. 2-26 2.4.12 GT - Execute Till a Temporary Breakpoint................................................................................. 2-27 2.4.13 HELP - Help .............................................................................................................................. 2-28 2.4.14 IRD - Internal Registers Display ................................................................................................ 2-29 2.4.15 IRM - Internal Registers MODIFY ............................................................................................. 2-30 2.4.16 MD - Memory Display................................................................................................................ 2-31 2.4.17 MM - Memory Modify .............................................................................................................. 2-32 2.4.18 RD - Register Display ................................................................................................................ 2-33 2.4.19 RM - Register Modify................................................................................................................. 2-34 2.4.20 RESET - Reset the board and dBUG .......................................................................................... 2-35 2.4.21 SET - Set Configuration ............................................................................................................. 2-36 2.4.22 SHOW - Show Configuration...................................................................................................... 2-38 2.4.23 STEP - Step Over ....................................................................................................................... 2-39 2.4.24 SYMBOL - Symbol Name Management....................................................................................... 2-40 2.4.25 TRACE - Trace Into ................................................................................................................... 2-41 2.4.26 UPDBUG - Update the dBUG Image ......................................................................................... 2-42 v For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.27 UPUSER - Update User Code In Flash ...................................................................................... 2-43 2.4.28 VERSION - Display dBUG Version ............................................................................................ 2-44 2.5 TRAP #15 FUNCTIONS ..................................................................................................................... 2-45 2.5.1 OUT_CHAR............................................................................................................................... 2-45 2.5.2 IN_CHAR................................................................................................................................... 2-45 2.5.3 CHAR_PRESENT....................................................................................................................... 2-46 2.5.4 EXIT_TO_dBUG........................................................................................................................ 2-46 Freescale Semiconductor, Inc... 3 HARDWARE DESCRIPTION AND RECONFIGURATION............................................................... 3-47 3.1 PROCESSOR AND SUPPORT LOGIC ............................................................................................. 3-47 3.1.1 Processor ................................................................................................................................... 3-47 3.1.2 Reset Logic ................................................................................................................................ 3-47 3.1.3 -HIZ Signal ................................................................................................................................ 3-47 3.1.4 Clock Circuitry .......................................................................................................................... 3-48 3.1.5 Watchdog Timer (Bus Monitor) .................................................................................................. 3-48 3.1.6 Interrupt Sources ....................................................................................................................... 3-48 3.1.7 Internal SRAM ........................................................................................................................... 3-49 3.1.8 MCF5206e Registers and Memory Map ..................................................................................... 3-49 3.1.9 Reset Vector Mapping ................................................................................................................ 3-50 3.1.10 -TA Generation .......................................................................................................................... 3-50 3.1.11 Wait State Generator.................................................................................................................. 3-50 3.2 ADRAM SIMM................................................................................................................................. 3-51 3.3 FLASH ROM..................................................................................................................................... 3-51 3.3.1 JP2 Jumper and User’s Program................................................................................................ 3-51 3.4 SERIAL COMMUNICATION CHANNELS...................................................................................... 3-51 3.4.1 MCF5206e Two UARTs.............................................................................................................. 3-51 3.4.2 Motorola Bus (M-Bus) Module................................................................................................... 3-52 3.5 PARALLEL I/O PORT ...................................................................................................................... 3-52 3.6 ONBOARD ETHERNET LOGIC ...................................................................................................... 3-52 3.7 CONNECTORS AND THE EXPANSION BUS ................................................................................ 3-54 3.7.1 The Terminal Connector P1 ....................................................................................................... 3-54 3.7.2 The Auxiliary Serial Communication Connector P2 ................................................................... 3-54 3.7.3 Logical Analyzer Connectors LA1-4 and Processor Expansion Bus J2, J3, and J4 ..................... 3-54 3.7.4 Debug Connector J5 .................................................................................................................. 3-60 APPENDIX A CONFIGURING DBUG FOR NETWORK DOWNLOADS .................................................... 1 A.1 REQUIRED NETWORK PARAMETERS........................................................................................................ 1 A.2 CONFIGURING DBUG NETWORK PARAMETERS ...................................................................................... 2 A.3 TROUBLESHOOTING NETWORK PROBLEMS ............................................................................................ 3 APPENDIX B FPLA CODE ............................................................................................................................... 5 APPENDIX C SCHEMATICS ........................................................................................................................... 9 APPENDIX D MC5206EC3 BILL OF MATERIALS ..................................................................................... 19 vi For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLES Freescale Semiconductor, Inc... TABLE 1. JP1, -CS0 SELECT ........................................................................................................................... 1-8 TABLE 2. JP2, UPPER/LOWER HALF BOOT ................................................................................................. 1-8 TABLE 3. DBUG COMMANDS ........................................................................................................................ 2-13 TABLE 4. ROM MONITOR DEFAULT M5206EC3 MEMORY MAP ................................................................ 3-50 TABLE 5. P1 (TERMINAL) CONNECTOR PIN ASSIGNMENT......................................................................... 3-54 TABLE 6. P2 CONNECTOR PIN ASSIGNMENT .............................................................................................. 3-54 TABLE 7. J2 CONNECTOR PIN ASSIGNMENT .............................................................................................. 3-55 TABLE 8. J3 CONNECTOR PIN ASSIGNMENT .............................................................................................. 3-56 TABLE 9. J4 CONNECTOR PIN ASSIGNMENT .............................................................................................. 3-57 TABLE 10. LA1 CONNECTOR PIN ASSIGNMENT.......................................................................................... 3-57 TABLE 11. LA2 CONNECTOR PIN ASSIGNMENT.......................................................................................... 3-58 TABLE 12. LA3 CONNECTOR PIN ASSIGNMENT.......................................................................................... 3-58 TABLE 13. LA4 CONNECTOR PIN ASSIGNMENT.......................................................................................... 3-59 TABLE 14. J5 CONNECTOR PIN ASSIGNMENT ............................................................................................ 3-60 vii For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. FIGURES Freescale Semiconductor, Inc... FIGURE 1. BLOCK DIAGRAM OF THE M5206EC3 BOARD................................................................................. 1-2 FIGURE 2. PIN ASSIGNMENT FOR P1 (TERMINAL) CONNECTOR ...................................................................... 1-6 FIGURE 3. SYSTEM CONFIGURATION ............................................................................................................... 1-6 FIGURE 4. JUMPER AND CONNECTOR PLACEMENT ......................................................................................... 1-7 FIGURE 5. FLOW DIAGRAM OF DBUG OPERATIONAL MODE......................................................................... 2-11 viii For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1 INTRODUCTION TO THE M5206EC3 BOARD 1.1 OVERVIEW Freescale Semiconductor, Inc... The M5206EC3 is a versatile single-board computer based on the MCF5206e ColdFire® processor, which you can use as a powerful microprocessor-based controller in a variety of applications. With the addition of a terminal, the M5206EC3 serves as a complete microcomputer for development/evaluation, training, and educational use. You just have to connect an RS-232compatible terminal (or a personal computer with terminal emulation software) and a power supply to have a fully functional system. Provisions have been made to connect this board to additional user-supplied boards via the Microprocessor Expansion Bus connectors to expand memory and I/O capabilities. Additional boards may require bus buffers to compensate for added bus loading. Furthermore, the PC-board permits configuration in a way that best suits an application. Available features include: as much as 4 MBytes DRAM, 1 MByte of SRAM (not included), timer, serial and parallel I/O, Ethernet, DMA, I-cache, internal SRAM, chip select module, and 1 MByte of Flash. In addition, all of the signals are easily accessible to any logical analyzer with mictor probes or berg connectors to assist with debug. All of the processor’s signals are also available via connectors J8 and J9 for expansion purposes. 1.2 GENERAL HARDWARE DESCRIPTION The M5206EC3 board provides the RAM, Flash ROM, on-board NE2000-compatible Ethernet interface (10 Mbit/sec), RS-232, and all the built-in I/O functions of the MCF5206e for learning and evaluating the attributes of the MCF5206e. The MCF5206e— a member of the ColdFire Family of processors— is a 32-bit processor with 32 bits of addressing and 32 lines of data. The processor has eight 32-bit data registers, eight 32-bit address registers, a 32-bit program counter, and a 16bit status register. The MCF5206e has a System Integration Module (SIM) that incorporates many system design functions, such as programmable chip-select logic, system protection logic, general-purpose I/O, and interrupt controller logic. The chip-select logic can select as many as eight memory banks or peripherals and the DRAM controller allows a glueless interface to two banks of DRAMs. The chip-select logic also allows a programmable number of wait states for using slower memory (refer to MCF5206e User's Manual , downloadable at http://www.Motorola.com/ColdFire, for detail information about the SIM.) The M5206EC3 only uses three of the chip selects to access the Flash ROMs, SRAM (which is not populated on board, but you can add later) and the Ethernet. The DRAM controller controls one SIMM module, 4 MBytes of DRAM, both RAS lines, and all four CAS lines are used. All other functions of the SIM are available. A hardware watchdog timer (bus monitor) circuit is included in the SIM that monitors the bus activities. If a bus cycle is not terminated within a programmable time, the watchdog timer will assert an internal transfer error signal to terminate the bus cycle. The ROM monitor never uses the hardware watchdog timer feature but it is available to enable it in your code. 1-1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. BDM Connector MCF5206e ColdFire XCEIVERS P1, P2 RS232 Freescale Semiconductor, Inc... P5 RJ45 Ethernet U17 SRAM (Optional) ispLSI 2032LV U10 Flash 1Mbyte U13, U15 Data Buffers U6 ADRAM SIMM U7 I/O Ports Data Bus Addr Bus Contr Bus Mictor & Expansion Connectors Figure 1. Block Diagram of the M5206EC3 Board 1.3 SYSTEM MEMORY There are two on-board Flash ROMs (U13, U15). U13 is the most significant byte; U15, the least significant byte. The M5206EC3 comes with two 29LV004 Flash ROMs programmed with a debugger/monitor firmware. Both AM29LV004DT Flash are 4 Mbits, each giving a total of 1 MByte of Flash memory. The Debug only supports 29LV004 Flash ROM. The one 72-pin SIMM socket for ADRAM supports as much as 32 MBytes of 3.3V ADRAM. The board comes with 4 MBytes of 3.3V ADRAM installed. The MCF5206e has 8 KBytes organized as 2048x32 bits of internal SRAM. The internal cache of the MCF5206e is a nonblocking 4 KByte direct-mapped instruction cache. The ROM monitor currently does not use the cache, but user code can enable and use the I-cache. 1-2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.4 SERIAL COMMUNICATION CHANNELS The MCF5206e has two built-in UARTs with independent baud-rate generators. The signals of channel one are passed through external driver/receivers to make the channel RS-232 compatible. The debugger uses UART1 to let you access with a terminal. In addition, the signals of both channels are available on the mictor connectors LA1 and LA3 to be viewed by a logic analyzer. The UART1 channel is the TERMINAL channel the debugger uses for communicating with the external terminal/PC. The TERMINAL baud rate is set at 19200. The MCF5206e also incorporates the M-Bus, which is compatible with I2C bus standard. Freescale Semiconductor, Inc... 1.5 PARALLEL I/O PORTS The MCF5206e offers one 8-bit general-purpose parallel I/O port. Each pin can be individually programmed as input or output. The parallel port bits PP(3:0) are multiplexed with PST(3:0) and PP(7:4) are multiplexed with DDATA(3:0). The Pin Assignment Register (PAR) controls both nibbles of the parallel port. After reset, all pins are configured as general-purpose parallel I/O. The ROM monitor configures the pins as PST(3:0) and DDATA(3:0). 1.6 PROGRAMMABLE TIMER/COUNTER The MCF5206e has two built-in general-purpose 16-bit timer/counters. The MCF5206EC3 ROM monitor does not use these timers, so they are available for you to use. The signals for the timer are available on the LA1 and J2. 1.7 ON-BOARD ETHERNET The M5206EC3 has an on-board Ethernet (NE2000 compatible) operating at 10 Mbits. The onboard ROM monitor is programmed to perform fast downs from a network to memory in SRecord, COFF, or ELF. See the Ethernet section in the appendix for more information. 1.8 SYSTEM CONFIGURATION The M5206EC3 board requires only the following items for minimum system configuration (see Figure 3): 1. The M5206EC3 board (provided) 2. Power supply, 7.5V to 9V with minimum of 1.5 amp 3. RS-232C-compatible terminal or any computer with terminal emulation software and an RS-232 port 4. Communication cable (provided) 1-3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.9 INSTALLATION AND SETUP The following sections describe all the steps needed to prepare the board for operation. Please read the following sections carefully before using the board. When you are preparing the board for the first time, be sure to check that all jumpers are in the default locations. After the board is functional in its standard configuration, you can use the Ethernet by following the instructions provided in the following sections. Freescale Semiconductor, Inc... 1.9.1 Unpacking 1. Unpack the computer board from its shipping box. 2. Save the box for storing or reshipping. 3. Refer to the following list and verify that all the items are present. You should have received: a. M5206EC3 single board computer b. M5206EC3 user's manual, this documentation c. One serial (RS-232) communication cable d. One Computer Systems BDM wiggler cable WARNING AVOID TOUCHING THE MOS DEVICES. STATIC DISCHARGE CAN AND WILL DAMAGE THESE DEVICES. Once you verified that all the items are present: 1. Remove the board from its protective jacket. 2. Check the board for any visible damage and ensure that there are no broken, damaged, or missing parts. If you have not received all the items listed above or they are damaged, please contact Cadre III immediately in order to correct the problem. Cadre III 4150 Freidrich Lane, Suite D Austin, Texas 78744 Support: (USA only): (800) 410-2031 (512) 326-9455 1.9.2 Preparing the Board for Use The board as shipped is ready to be connected to a terminal and the power supply without any modification. However, follow the steps below to ensure proper operation from the first time you apply the power. Figure 4 shows the placement of the jumpers and the connectors, and section 1.11 explains the default jumper settings. 1-4 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.9.3 Providing Power to the Board The board accepts two types of power supply connections. Connector P4 is a 2.1mm barrel connector power jack with center positive and P3 is a lever-actuated connector for bare-wire insertion. The board accepts 7.5V to 9V DC (regulated or unregulated) at 1.5 amp through either one of the connectors (see below). Power supplied to the processor passes through jumpers J6 and J7 (note: power connected to the pullup resistors attached to the processor does not pass through J6 or J7). Both J6 and J7 are in parallel with each other and can perform power analysis. Freescale Semiconductor, Inc... Note: On boards labeled R “ ev 1.2”, the silkscreen for D9 and D10 are incorrect. D9 should be labeled +3.3V and D10 should be labeled +5V. For those board revisions higher than Rev 1.2, ignore this note. Contact NO. 1 2 Voltage +7.5-9V Ground 1.9.4 Selecting Terminal Baud Rate The MCF5206e serial channel used for serial communication has a built-in timer the ROM monitor uses to generate the baud rate for terminal communication. You can program the serial channel to several baud rates. After power-up or a manual reset, the ROM monitor firmware configures the UART channel 1 for 19200 baud. Once the ROM monitor is running, you can issue the SET command to choose any baud rate the ROM monitor supports. Refer to Chapter 2 for more information on this command. 1.9.5 The Terminal Character Format The character format of the communication channel is fixed at power -up or reset. The character format is 8 bits per character, no parity, and one stop bit. Make sure your terminal is set to this format. Handshaking is set to none. 1.9.6 Connecting the Terminal Use the RS-232 serial cable to connect the terminal to the M5206EC3. The cable has a 9-pin female D subconnector at one end and a 9-pin male D subconnector at the other end (see Figure 2). Connect the 9-pin male connector to P1 connector on M5206EC3. Connect the 9-pin female connector to one of the available serial communication channels normally referred to as COMx (COM1, COM2, etc.) on the IBM PC or compatible machine. Depending on the kind of serial connector on the back of your PC, that connector may be a male 25-pin or 9-pin. 9-pin-to-25-pin adapters are available at most electronics stores. 1-5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.9.7 Using a Personal Computer as a Terminal You can use your personal computer as a terminal provided you also have installed terminal emulation software such as PROCOMM, KERMIT, QMODEM, Windows 95® Hyper Terminal or similar packages. Connect as described in 1.9.6 Connecting the Terminal. Freescale Semiconductor, Inc... Once the connection to the PC is made, you are ready to power-up the PC and run the terminal emulation software. When the PC is in terminal mode, you need to select the baud rate and the character format for the channel. Most terminal emulation software packages provide a command known as "Alt-p" (press the p key while pressing the Alt key) to choose the baud rate and character format. Select 8 bits, no parity, one stop bit. Then, select the baud rate as 19200. Now apply power to the board. Figure 2. Pin assignment for P1 (Terminal) connector 1. 2. 3. 4. 5. 6. 7. 8. 9. Data Carrier Detect, Output (shorted to pins 4 and 6) Receive Data, Output from board (receive refers to terminal side) Transmit Data, Input to board (transmit refers to terminal side) Data Terminal Ready, input (shorted to pin 1 and 6) Signal Ground Data Set Ready, Output (shorted to pins 1 and 4). Request to Send, input Clear to send, output Not connected RS232 DB-9 Connectors (P1-2) P1 J4 Microprocessor Expansion bus I/O (J3-J4) Background Debug Mode (BDM) Connector (J5) Ethernet RJ45 Microprocessor Expansion bus I/O J3 P2 Ethernet P5 LED -> 0 LA4 J2 3.3V -> 0 5V -> 0 J5 LED LA2 Mictor connectors (LA1-4) LA1 U7 MCF5206e LA3 P3 P4 +7.5 to 12v GND Power Supply Figure 3. System Configuration 1-6 For More Information On This Product, Go to: www.freescale.com ADRAM SIMM Freescale Semiconductor, Inc. JP6 JP7 P1 P2 J4 J3 Freescale Semiconductor, Inc... LA4 LA1 J5 TP1 P5 J2 LA2 U7 MCF5206e LA3 P3 P4 JP2 JP1 Figure 4. Jumper and Connector Placement 1.10 SYSTEM POWER-UP AND INITIAL OPERATION Now that you have connected all the cables, you can apply power to the board. After power is applied, dBUG initializes the board then displays the power-up message on the terminal, which includes the amount of the memory present. Hard Reset DRAM Size: 4M Copyright 1997-1998 Motorola, Inc. All Rights Reserved. ColdFire® MCF5206e EVS Debugger V1.4.1 (JUL 1998 12:10:48:) Enter ‘help’ for help. dBUG> Note: You can download from the web any updates to the ROM Monitor. The board is now ready for operation under the control of the debugger as described in Chapter 2. If you do not receive the above response, perform the following checks: 1. Make sure that the power supply is properly set and connected to the board. 2. Check that both LEDs D9 and D10 are lit (the board requires a minimum of 7.5 to 9 V DC). 3. Check that the terminal and board are set for the same character format and baud rate. 4. Press the black RESET button to ensure that the board has been initialized properly. If you still are not receiving the proper response, your board may have been damaged in shipping. Contact Cadre III for further instructions. 1-7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.11 M5206EC3 JUMPER SETUP The jumpers on the board are discussed in Chapter 3. However, here’s a brief discussion of the jumper settings. 1.11.1 Jumper JP1 This jumper selects between -CS0 to Flash or a header. Table 1. JP1, -CS0 Select Freescale Semiconductor, Inc... JP1 1 and 2 2 and 3 FUNCTION Flash (default) Header (TP1) 1.11.2 Jumper JP2 - Flash Upper Half/Lower Half Boot This jumper allows the MCF5206e to boot from the lower or upper half of the flash. The default is the lower half. Refer to Section 3.3.1 for information on using this jumper. Table 2. JP2, Upper/Lower Half BOOT JP2 1 and 2 2 and 3 FUNCTION Lower (default) Upper 1.11.3 Jumper J6 and J7 - CPU Power JP6 and 7 These jumpers pass power to the ColdFire CPU. Without a minimum of one jumper, the CPU will not get any power. JP6 ON OFF JP7 ON OFF FUNCTION Power (default) No Power 1.12 USING THE BDM The MCF5206e has a built-in debug mechanism referred to as BDM that uses the J5 header. The BDM cable (provided) is to be used with third-party developer software tools such as SDS or P&E. For a current list of third-party development tools, visit the Motorola ColdFire web site at http://www.motorola.com/ColdFire. The BDM cable connects to the parallel port of a computer and to the MC5206EC3 J5 header. IMPORTANT: There is no key to protect the BDM cable from being rotated and plugged in incorrectly. To prevent hooking up the BDM cable incorrectly, notice pin 1 on the cable and the notation on the board. A red strip on the ribbon cable normally notes which side of the cable pin 1 is located. There is also a pin-1 marking on the board near the connector. 1-8 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2 USING THE MONITOR/DEBUG FIRMWARE The M5206EC3 computer board has a resident firmware package that provides a self-contained programming and operating environment. The firmware, named dBUG, provides you with monitor/debug, disassembly, program download, and I/O control functions. This chapter explains how to use the dBUG package, including the user interface and command structure. Freescale Semiconductor, Inc... 2.1 WHAT IS dBUG? The dBUG package is a resident firmware package for the ColdFire® Family evaluation boards. The firmware (stored in two 512Kx8 Flash ROM devices) provides a self-contained programming and operating environment. The dBUG package interacts with you through predefined commands that are entered from the terminal. The user interface to dBUG is the command line. A number of features have been implemented to achieve an easy and intuitive command line interface. The dBUG package assumes that an 80x24 character dumb terminal is used to connect to the debugger. For serial communications, dBUG requires eight data bits, no parity, and one stop bit, 8N1. The baud rate is 19200 but can be changed after the power-up using the SET command (see Section 2.4.21). The command line prompt is d“ BUG>“. Enter any dBUG command from this prompt. Command lines cannot exceed 80 characters in length. Wherever possible, dBUG displays data in 80 columns or less. The dBUG echoes each character as you type them, eliminating the need for any l“ocal echo”on the terminal side. In general, dBUG is not case sensitive. You can enter commands in either upper or lower case. Only symbol names require the exact case. Most commands can be recognized by using an abbreviated name. For instance, entering h“ ”is the same as entering h“ elp”. Therefore, it is not necessary to type the entire command name. The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. The dBUG recognizes these commands and allows for repeated execution of these commands with minimal typing. After a command is entered, simply press <RETURN> or <ENTER> to invoke the command again. The command is executed as if no command line parameters were provided. An additional function called the "TRAP 15 handler" lets you program various routines within dBUG. The TRAP 15 handler is discussed at the end of this chapter. The operational mode of dBUG is demonstrated in Figure 5. After system initialization, the board waits for a command-line input from the user terminal. When a proper command is entered, the operation continues in one of the two basic modes. If the command causes execution of the user program, the dBUG firmware may or may not be re-entered, depending on programming of the user program (see Section 2.5.4). For the other mode, the command will be executed under 2-9 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. control of the dBUG firmware, and after command completion, the system will return to command-entry mode. During command execution, additional user input may be required depending on the command function. For commands that accept an optional <width> to modify the memory access size, the valid values are as follows: .B 8-bit (byte) access .W 16-bit (word) access .L 32-bit (long) access Freescale Semiconductor, Inc... When no <width> option is provided, the default width is .W, 16-bit. The dBUG maintains the core ColdFire register set. These are listed below. A0-A7 D0-D7 PC SR All control registers on ColdFire are not readable by the supervisor-programming model, and thus not accessible via dBUG. User code can change these registers, but be careful as changes may render dBUG useless. A reference to S “ P”actually refers to A “ 7”. 2.2 OPERATIONAL PROCEDURE 2.2.1 System Power-Up a. Be sure the power supply is connected properly prior to power-up. b. Make sure the terminal is connected to the terminal (P1) connector. c. Turn power on to the board. 2-10 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Initialize Command Line Input from Terminal? Freescale Semiconductor, Inc... Execute Comman d Function No Jump to User Program and Begin Execution Yes No Does Command Line Cause User Program Execution? Yes Figure 5. Flow Diagram of dBUG Operational Mode 2.2.2 System Initialization Powering up the board will initialize the system. The processor is reset and dBUG is invoked. The dBUG performs the following configurations of internal resources during the initialization. The instruction cache is invalidated and disabled. The Vector Base Register, VBR, points to the Flash. However, a copy of the exception table is made at address $00000000 in ADRAM. To take over an exception vector, place the address of the exception handler in the appropriate vector in the vector table located at 0x00000000, and then point the VBR to 0x00000000. The software watchdog timer is disabled, bus monitor is enabled, and internal timers are placed in a stop condition. Interrupt controller registers are initialized with unique interrupt level/priority pairs. After initialization, the terminal will display the following: Hard Reset DRAM Size: 4M NE2000: 0x300 Copyright 1997-1998 Motorola, Inc. All Rights Reserved. ColdFire® MCF5206e EVS Debugger Vx.x.x (xxx 199x xx:xx:xx:) Enter ‘help’ for help. dBUG> If you did not receive this response, recheck the setup. Refer to Section 1.10 System PowerUp And Initial Operation. Note, the date “xxx 199x xx:xx:xx” may vary in different revisions. 2-11 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. You can re-initialize the M5206EC3 computer board firmware using other methods, which are discussed in the following paragraphs. Freescale Semiconductor, Inc... 2.2.2.1 HARD RESET BUTTON Hard RESET is the red button located in the lower right side of the board. Depressing this button terminates all processes, resets the MCF5206e processor and board logic, and restarts the dBUG firmware. Pressing the RESET button would be the appropriate action if all else fails. 2.2.2.2 ABORT BUTTON ABORT is the black button located next to RESET button on the right side of the board. The abort function interrupts the present processing (a level 7 interrupt on MCF5206e) and passes control to the dBUG firmware. This action differs from RESET in that no processor register or memory contents are changed, the processor and peripherals are not reset, and dBUG is not restarted. Also, in response to depressing the ABORT button, the contents of the MCF5206e core internal registers are displayed. The abort function is most appropriate when software is being debugged. You can interrupt the processor without destroying the present state of the system. 2.2.2.3 SOFTWARE RESET COMMAND The dBUG does have a command that restarts the dBUG as if a hardware reset was invoked. The command is R “ ESET”. 2.2.2.4 USER MEMORY ADDRESS User memory is located at addresses $00020000-$xxxxxxxx, where $xxxxxxxx is the maximum RAM address of the memory installed in the board. When first learning the system, you should limit your activities to this area of the memory map. The dBUG uses the address range $00000000-$0001FFFF. The memory map is documented in detail in Section 3.1.8. 2.3 TERMINAL CONTROL CHARACTERS The command line editor uses a history buffer to remember the last five commands issued. These commands can be recalled and then executed using control keys. Several keys serve as a command line edit and control functions. It is best to become familiar with these functions before working with the system. These functions include: a. b. c. d. e. RETURN (carriage- return) - will enter the command line and initiates processing Delete (Backspace) key or CTRL-H - will delete the last character entered CTRL-D - Go down in the command history buffer; you can modify, then press enter CTRL-U - Go up in the command history buffer; you can modify, then press enter CTRL-R - Recall and execute the last command entered; does not require pressing RETURN For characters requiring the control key (CTRL), the CTRL should be held down while the other key is pressed. 2-12 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4 dBUG COMMAND SET Table 3 lists the dBUG commands. Each of the individual commands is described in the following pages. Freescale Semiconductor, Inc... Table 3. dBUG Commands COMMAND MNEMONIC AS BC BF BM BS BR DATA DI DL DN GO GT HELP IRD IRM MD MM RD RM RESET SET SHOW STEP SYMBOL DESCRIPTION Assemble Block Compare Block Fill Block Move Block Search Breakpoint Data Convert Disassemble Download Serial Download Network Execute Go TILL BREAKPOINT Help Internal Register Display Internal Register Modify Memory Display Memory Modify Register Display Register Modify Reset Set Configurations Show Configurations Step (Over) Symbol Management TRACE UPDBUG UPUSER VERSION Trace(Into) Update Dbug Update User Flash Show Version SYNTAX PAGE AS <addr> <instruction> BD <1ST ADDR> <2ND ADDR> <LENGTH> BF<WIDTH> BEGIN END DATA BM BEGIN END DEST BS <WIDTH> BEGIN END DATA BR ADDR <-R> <-C COUNT> <-T TRIGGER> DATA VALUE DI <ADDR> DL <OFFSET> DN <-C> <-E> <-S> <-I> <-O OFFSET> <FILENAME> GO <ADDR> GT <ADDR> HELP <COMMAND> IRD <MODULE.REGISTER> IRM <MODULE.REGISTER> <DATA> MD <WIDTH> <BEGIN> <END> MM <WIDTH> ADDR <DATA> RD <REG> RM REG DATA RESET SET OPTION <VALUE> SHOW OPTION STEP SYMBOL <SYMB> <-A SYMB VALUE> <-R SYMB> <-C | L | S> TRACE <NUM> UPDBUG UPUSER VERSION 2-6 2-7 2-8 2-9 2-11 2-10 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-28 2-29 2-30 2-31 2-32 2-33 2-34 Note: If a command causes the system to access an unused address (i.e., no memory or peripheral devices are mapped at that address), a bus trap error will occur, which results in a trap error message and reveals the contents of all the MCF5206e core registers. Control is returned to the dBUG monitor. Parameters enclosed in < > symbols are optional. 2-13 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.1 AS - Assemble Usage: AS <addr> <instruction> AS The AS command assembles instructions. The value for addr can be an absolute address specified as a hexadecimal value or a symbol name. The instruction can be any valid instruction for the target processor. Freescale Semiconductor, Inc... The assembler keeps track of the address where the last instruction’s opcode was written. If no address is provided to the AS command and the AS command has not been used since system reset, then AS defaults to the beginning address of user space for the target board. If no instruction is forwarded to the AS command, then AS prompts with the address where opcode will be written, and continues to assemble instructions until you terminate the AS command by inputting a period (.). The inline assembler allows the use of case-sensitive symbols defined by equate statements and labels that are stored in the symbol table. The syntax for defining symbols and labels is as follows: Symbol equ value Symbol: equ value Symbol .equ value Symbol: .equ value Label: instruction Label: Constants and operands may be input in several different bases: 0x $ @ % digit followed by hexadecimal constant followed by hexadecimal constant followed by octal constant followed by binary constant decimal constant The assembler also supports the different syntax allowed for the indexed, displacement and immediate addressing modes: (12,An) (4,PC,Xn) (0x1234).L or or or 12(An) 4(PC,Xn) 0x1234.L Examples: To assemble one ‘move’instruction at the next assemble address, the command is: as move.l #0x25,d0 To assemble multiple lines at 0x12000, the command is: as 12000 then: 2-14 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. start: nop lsr.l cmp beq nop #1,d0 #4,d0 start Freescale Semiconductor, Inc... 0x00012000: 0x00012002: 0x00012004: 0x00012006: 0x00012008: 0x0001200A: 2-15 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.2 BC - Compare Blocks of Memory Usage: BC first second length BC The BC command compares two contiguous blocks of memory; the first block starting at address f“irst”, the second block starting at address s“econd”, both of length l“ength”. If the blocks are not identical, the addresses of the first mismatch are displayed. The value for addresses f“irst”and s“econd”can be an absolute address specified as a hexadecimal value or a symbol name. The value for length can be a symbol name or a number converted according to the user-defined radix, normally hexadecimal. Freescale Semiconductor, Inc... Examples: To verify that the code in the first block of user FLASH space (128K) is identical to the code in user ADRAM space, the command is, bc 20000 FFE20000 20000 . 2-16 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.3 BF - Block of Memory Fill Usage: BF<width> begin end data BF The BF command fills a contiguous block of memory starting at address b“ egin”, stopping at address e“nd”, with the value, d“ ata”. Width modifies the size of the data that is written. The value for addresses b“ egin”and e“nd”can be an absolute address specified as a hexadecimal value, or a symbol name. The value for d“ ata”can be a symbol name or a number converted according to the user defined radix, normally hexadecimal. Freescale Semiconductor, Inc... This command first aligns the starting address for the data access size and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly aligned memory accesses. Examples: To fill a memory block starting at 0x00010000 and ending at 0x00040000 with the value 0x1234, the command is: bf 10000 40000 1234 To fill a block of memory starting at 0x00010000 and ending at 0x0004000 with a byte value of 0xAB, the command is: bf.b 10000 40000 AB To zero out the BSS section of the target code (defined by the symbols bss_start and bss_end), the command is: bf bss_start bss_end 0 2-17 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.4 BM - Block Move Usage: BM begin end dest BM The BM command moves a contiguous block of memory starting at address b“ egin”, stopping at address e“nd”, to the new address, d“ est”. The BM command copies memory as a series of bytes and does not alter the original block. The value for addresses b“ egin”, e“nd”, and d“ est”can be an absolute address specified as a hexadecimal value or a symbol name. If the destination address overlaps the block defined by b“ egin”and e“nd”, an error message is produced and the command exits. Freescale Semiconductor, Inc... Examples: To copy a block of memory starting at 0x00040000 and ending at 0x00080000 to the location 0x00200000, the command is: bm 40000 80000 200000 To copy the target code’s data section (defined by the symbols data_start and data_end) to 0x00200000, the command is: bm data_start data_end 200000 2-18 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. BR - Breakpoint Usage: BR addr <-r> <-c count> <-t trigger> 2.4.5 BR The BR command inserts or removes breakpoints at address addr. The value for addr can be an absolute address specified as a hexadecimal value, or a symbol name. Count and trigger are numbers converted according to the user-defined radix, normally hexadecimal. If no argument is provided to the BR command, a listing of all defined breakpoints is displayed. Freescale Semiconductor, Inc... The -r option to the BR command removes a breakpoint defined at address addr. If no address is specified in conjunction with the -r option, all breakpoints are removed. Each time a breakpoint is encountered during the execution of target code, its count value is incremented by one. By default, the initial count value for a breakpoint is zero, but the -c option allows setting the initial count for the breakpoint. Each time a breakpoint is encountered during the execution of target code, the count value is compared against the trigger value. If the count value is equal to or greater than the trigger value, a breakpoint is encountered and control returned to dBUG. By default, the initial trigger value for a breakpoint is one, but the -t option allows setting the initial trigger for the breakpoint. If no address is specified in conjunction with the -c or -t options, then all breakpoints are initialized to the values specified by the -c or -t option. Examples: To set a breakpoint at the C function main(), the command is: br _main When the target code is executed and the processor reaches main(), control will returned to dBUG. To set a breakpoint at the C function bench() and set its trigger value to 3, the command is: br _bench -t 3 When the target code is executed, the processor must try to execute the function bench() a third time before returning control back to dBUG. To remove all breakpoints, the command is: br -r 2-19 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.6 BS - Block Search Usage: BS<width> begin end data BS The BS command searches a contiguous block of memory starting at address b“ egin”, stopping at address e“nd”, for the value, d“ ata”. W “ idth”modifies the size of the data that is compared during the search. Freescale Semiconductor, Inc... The value for addresses b“ egin”and e“nd”can be an absolute address specified as a hexadecimal value or a symbol name. The value for d“ ata”can be a symbol name or a number converted according to the user-defined radix, normally hexadecimal. This command first aligns the starting address for the data access size, and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly aligned memory accesses. Examples: To search for the 16-bit value 0x1234 in the memory block starting at 0x00040000 and ending at 0x00080000 the command is: bs 40000 80000 1234 This reads the 16-bit word located at 0x00040000 and compares it against the 16-bit value 0x1234. If no match is found, the address increments to 0x00040002 and the next 16-bit value is read and compared. To search for the 32-bit value 0xABCD in the memory block starting at 0x00040000 and ending at 0x00080000, the command is: bs.l 40000 80000 ABCD This reads the 32-bit word located at 0x00040000 and compares it against the 32-bit value 0x0000ABCD. If no match is found, the address increments to 0x00040004 and the next 32-bit value is read and compared. To search the BSS section (defined by the symbols bss_start and bss_end) for the byte value 0xAA, the command is: bs.b bss_start bss_end AA 2-20 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.7 DATA - Data Conversion Usage: DATA data DATA The DATA command displays data in both decimal and hexadecimal notation. The value for data can be a symbol name or an absolute value. If an absolute value passed into the DATA command is prefixed by 0“ x”, data is interpreted as a hexadecimal value. Otherwise, data is interpreted as a decimal value. All values are treated as 32-bit quantities. Examples: Freescale Semiconductor, Inc... To display the decimal equivalent of 0x1234, the command is: data 0x1234 To display the hexadecimal equivalent of 1234, the command is: data 1234 2-21 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DI - Disassemble Usage: DI <addr> DI 2.4.8 The DI command disassembles target code pointed to by addr. The value for addr can be an absolute address specified as a hexadecimal value or a symbol name. Wherever possible, the disassembler will use information from the symbol table to produce a more meaningful disassembly. This is especially useful for branch target addresses and subroutine calls. The DI command tries to track the address of the last disassembled opcode. If no address is provided to the DI command, the DI command uses the address of the last disassembled opcode. Freescale Semiconductor, Inc... Examples: To disassemble code that starts at 0x00040000, the command is: di 40000 To disassemble code of the C function main(), the command is: di _main 2-22 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.9 DL - Download Serial Usage: DL <offset> DL The DL command performs an S-record download of data obtained from the serial port. The value for offset is converted according to the user-defined radix, normally hexadecimal. If offset is provided, the destination address of each S-record is adjusted by offset. The DL command checks the destination address for validity. If the destination is an address below the defined user space (0x00000000-0x00020000), an error message is displayed and downloading aborted. Freescale Semiconductor, Inc... If the S-record file contains the entry point address, the program counter is set to reflect this address. Examples: To download an S-record file through the serial port, the command is: dl To download an S-record file through the serial port and adjust the destination address by 0x40, the command is: dl 0x40 2-23 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DN - Download Network Usage: DN <-c> <-e> <-i> <-s> <-o offset> <filename> 2.4.10 DN The DN command downloads code from the network. The DN command handle files that are S-record, COFF, or ELF formats. The DN command uses Trivial File Transfer Protocol, TFTP, to transfer files from a network host. Freescale Semiconductor, Inc... In general, the type of file to be downloaded and the name of the file must be specified to the DN command. The -c option indicates a COFF download, the -e option indicates an ELF download, I option indicates an image download, and the -s indicates an S-record download. The -o option works only in conjunction with the -s option to indicate and optional offset for S-record download. The filename is passed directly to the TFTP server and, therefore, must be a valid filename on the server. If neither of the -c, -e, -i, -s or filename options are specified, then a default filename and file type will be used. Default filename and file type parameters are manipulated using the SET and SHOW commands. The DN command checks the destination address for validity. If the destination is an address below the defined user space, an error message is displays and downloading is aborted. For ELF and COFF files, which contain symbolic debug information, the symbol tables are extracted from the file during download and used by dBUG. Only global symbols are kept in dBUG. Note: The dBUG symbol table is not cleared prior to downloading, so it is your responsibility to clear the symbol table as necessary prior to downloading. If an entry point address is specified in the S-record, COFF, or ELF file, the program counter is set accordingly. Examples: To download an S-record file with the name s“rec.out”, the command is: dn -s srec.out To download a COFF file with the name c“off.out”, the command is: dn -c coff.out To download a file using the default file type with the name b“ ench.out”, the command is: dn bench.out To download a file using the default filename and file type, the command is: dn 2-24 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... This command requires proper Network address and parameter setup. Refer to Appendix A for this procedure. 2-25 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.11 Go - Execute Usage: GO <addr> GO The GO command executes target code starting at address addr. The value for addr can be an absolute address specified as a hexadecimal value or a symbol name. If no argument is provided, the GO command begins executing instructions at the current program counter. When the GO command is executed, all user-defined breakpoints are inserted into the target code, and the context is switched to the target program. Control is regained only when the target code encounters a breakpoint, illegal instruction, or other exception that hands control back to dBUG. Freescale Semiconductor, Inc... Examples: To execute code at the current program counter, the command is: go To execute code at the C function main(), the command is: go _main To execute code at the address 0x00040000, the command is: go 40000 2-26 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.12 GT - Execute Till a Temporary Breakpoint Usage: GT <addr> GT The GT command executes the target code starting at the address in PC (whatever the PC has) until a temporary breakpoint as given in the command line is reached. Example: Freescale Semiconductor, Inc... To execute code at the current program counter and stop at breakpoint address 0x10000, the command is: GT 10000 2-27 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. HELP - Help Usage: HELP <command> 2.4.13 HE The HELP command displays a brief syntax of the commands available within dBUG. In addition, the address of where user code can start is given. If <command> is provided, a brief listing of the syntax of the specified command is displayed. Examples: To obtain a listing of all the commands available within dBUG, the command is: Freescale Semiconductor, Inc... help The help list is longer than one page. The help command displays one full screen and asks for an input to display the rest of the list. To obtain help on the breakpoint command, the command is: help br 2-28 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.14 IRD - Internal Registers Display Usage: IRD <module.register> IRD This commands displays the internal registers of different modules inside the MCF5206e. In the command line, the module refers to the module name where the register is located and the register refers to the specific register needed. The registers are organized according to the module to which they belong. The available modules on the MCF5206e are SIM, UART1, UART2, TIMER, DMA, M-Bus, DRAMC, and Chip Select. Refer to the MCF5206e User’s Manual for more details. Freescale Semiconductor, Inc... Example: ird sim.sypcr ;display the SYPCR register in the SIM module. 2-29 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. IRM - Internal Registers MODIFY Usage: IRM module.register data 2.4.15 IRM This commands modifies the contents of the internal registers of different modules inside the MCF5206e. In the command line, the module refers to the module name where the register is located, register refers to the specific register needed, and data is the new value to be written into that register. The registers are organized according to the module to which they belong. The available modules on the MCF5206e are SIM, UART1, UART2, TIMER, M-Bus, DRAMC, Chip-Select. Refer to MCF5206e User’s Manual for more information. Freescale Semiconductor, Inc... Example: irm timer.tmr1 0021 ;write 0021 into TMR1 register in the TIMER module. 2-30 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.16 MD - Memory Display Usage: MD<width> <begin> <end> MD The MD command displays a contiguous block of memory starting at address b“ egin”and stopping at address e“nd”. The value for addresses b“ egin” and e“nd” can be an absolute address specified as a hexadecimal value or a symbol name. W “ idth”modifies the size of the data that is displayed. Freescale Semiconductor, Inc... Memory display starts at the address b“ egin”. If no beginning address is provided, the MD command uses the last displayed address. If no ending address is provided, MD will display memory up to an address that is 128 beyond the starting address. This command first aligns the starting address for the data access size, and then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly aligned memory accesses. Examples: To display memory at address 0x00400000, the command is: md 400000 To display memory in the data section (defined by the symbols data_start and data_end), the command is: md data_start To display a range of bytes from 0x00040000 to 0x00050000, the command is: md.b 40000 50000 To display a range of 32-bit values starting at 0x00040000 and ending at 0x00050000, the command is: md.l 40000 50000 This command can be repeated by pressing the RETURN key. It will continue with the address after the last display address. 2-31 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.17 MM - Memory Modify Usage: MM<width> addr <data> MM The MM command modifies memory at the address addr. The value for address addr can be an absolute address specified as a hexadecimal value or a symbol name. W “ idth”changes the size of the data that is modified. The value for data may be a symbol name or a number converted according to the user defined radix, normally hexadecimal. Freescale Semiconductor, Inc... If a value for data is provided, the MM command immediately sets the contents of addr to data. If no value for data is provided, the MM command enters into a loop. The loop obtains a value for data, sets the contents of the current address to data, increments the address according to the data size, and repeats. The loop terminates when an invalid entry for the data value is entered, i.e., a period. This command first aligns the starting address for the data access size then increments the address accordingly during the operation. Thus, for the duration of the operation, this command performs properly aligned memory accesses. Examples: To set the byte at location 0x00010000 to be 0xFF, the command is: mm.b 10000 FF To interactively modify memory beginning at 0x00010000, the command is: mm 10000 2-32 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. RD - Register Display Usage: RD <reg> 2.4.18 RD The RD command displays the register set of the target. If no argument for reg is provided, then all registers are displayed. Otherwise, the value for reg is displayed. Examples: To display all the registers and their values, the command is: rd Freescale Semiconductor, Inc... To display only the program counter, the command is: rd pc 2-33 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.19 RM - Register Modify Usage: RM reg data RM The RM command modifies the contents of the register r“eg to data”. The value for r“eg”is the name of the register, and the value for d“ ata”can be a symbol name or it is converted according to the user defined radix, normally hexadecimal. The dBUG preserves the registers by storing a copy of the register set in a buffer. The RM command updates the copy of the register in the buffer. The actual value will not be written to the register until target code is executed. Freescale Semiconductor, Inc... Examples: To change register D0 to contain the value 0x1234, the command is: rm D0 1234 2-34 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. RESET - Reset the board and dBUG Usage: RESET 2.4.20 RESET The RESET command tries to reset the board and dBUG to their initial power-up states. The RESET command executes the same sequence of code that occurs at power up. This code tries to initialize the devices on the board and dBUG data structures. If the RESET command fails to reset the board to your satisfaction, cycle power or press the reset button. Examples: Freescale Semiconductor, Inc... To reset the board and clear the dBUG data structures, the command is: reset 2-35 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.21 SET - Set Configuration Usage: SET option <value> SET SET The SET command allows the setting of user-configurable options within dBUG. The options are listed below. If the SET command is issued without an option, it will show the available options and values. Freescale Semiconductor, Inc... See Appendix A for information on configuring dBUG for network downloads. The board needs a RESET after this command in order for the new option(s) to take effect. baud - This is the baud rate for the first serial port on the board. All communication between dBUG and you occur using either 9600 or 19200 bps, eight data bits, no parity, and one stop bit, 8N1. Do not choose 38400 baud. base - This is the default radix for use in converting number from their ASCII text representation to the internal quantity used by dBUG. The default is hexadecimal (base 16), and other choices are binary (base 2), octal (base 8), and decimal (base 10). client - This is the network Internet Protocol (IP) address of the board. For network communications, the client IP must be set to a unique value, usually assigned by your local network administrator. server - This is the network IP address of the machine that contains files accessible via TFTP. Your local network administrator will have this information and can assist in properly configuring a TFTP server if one does not exist. gateway - This is the network IP address of the gateway for your local subnetwork. If the client IP address and server IP address are not on the same subnetwork, then this option must be properly set. Your local network administrator will have this information. netmask - This is the network address mask to determine if use of a gateway is required. This field must be properly set. Your local network administrator will have this information. filename - This is the default filename to be used for network download if no name is provided to the DN command. filetype - This is the default file type to be used for network download if no type is provided to the DN command. Valid values are: s“-record”, c“off”, i“mage”, and e“lf”. autoboot - This option allows for the automatic download and execution of a file from the network. You can use this option to automatically boot an operating system from the network. Valid values are: o“ n”and o“ ff”. This option is not implemented on the current of dBUG. nicbase - This is base address of the network interface. This command is used to inform the dBUG of the address of the network interface. The default value shows 0x0000. However, this parameter is hard coded to 0x300. DO NOT CHANGE THIS OPTION. macaddr - This is the Ethernet MAC address of the board. For network communications, the MAC address must be set to a unique value. Any address that is not already in use is suitable. 2-36 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Examples: To see all the available options and supported choices, the command is: set To set the baud rate of the board to be 19200, the command is: set baud 19200 Freescale Semiconductor, Inc... Now press the RESET button (RED) or RESET command for the new baud to take effect. This baud will be programmed in Flash ROM and will be used during the power up. 2-37 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.22 SHOW - Show Configuration Usage: SHOW option SHOW SHOW The SHOW command displays the settings of the user-configurable options within dBUG. The SHOW command can display most configurable options via the SET commands. If the SHOW command is issued without any option, it will show all options. Examples: To display all the current options, the command is: Freescale Semiconductor, Inc... show To display the current baud rate of the board, the command is: show baud To display the TFTP server IP address, the command is: show server 2-38 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.23 STEP - Step Over Usage: STEP ST You can use the ST command to s“tep over”a subroutine call rather than trace every instruction in the subroutine. The ST command sets a breakpoint one instruction beyond the current program counter and then executes the target code. You can also use the ST command for BSR and JSR instructions. The ST command will work for other instructions as well, but note that if the ST command is used with an instruction that will not return, i.e. BRA, the temporary breakpoint may never be encountered and thus dBUG may not regain control. Freescale Semiconductor, Inc... Example: To pass over a subroutine call, the command is: step 2-39 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.24 SYMBOL - Symbol Name Management Usage: SYMBOL <symb> <-a symb value> <-r symb> <-c|l|s> SYMBOL The SYMBOL command adds or removes symbol names from the symbol table. If only a symbol name is provided to the SYMBOL command, the symbol table is searched for a match on the symbol name and its information displayed. The -a option adds a symbol name and its value into the symbol table. The -r option removes a symbol name from the table. Freescale Semiconductor, Inc... The -c option clears the entire symbol table; the -l option lists the contents of the symbol table; and the -s option displays usage information for the symbol table. Symbol names contained in the symbol table are truncated to 31 characters. Any symbol table lookups, either by the SYMBOL command or by the disassembler, will use only the first 31 characters. Symbol names are case sensitive. Examples: To define the symbol m “ ain”to have the value 0x00040000, the command is: symbol -a main 40000 To remove the symbol j“unk”from the table, the command is: symbol -r junk To see how full the symbol table is, the command is: symbol -s To display the symbol table, the command is: symbol -l 2-40 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.25 TRACE - Trace Into Usage: TRACE <num> TR The TRACE command allows single instruction execution. If <num> is provided, then <num> instructions are executed before control is returned to dBUG. The value for <num> is a decimal number. The TRACE command sets bits in the processors’supervisor registers to achieve single instruction execution, and the target code executed. Control returns to dBUG after a single instruction execution of the target code. Freescale Semiconductor, Inc... Examples: To trace one instruction at the program counter, the command is: tr To trace 20 instructions from the program counter, the command is: tr 20 2-41 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.26 UPDBUG - Update the dBUG Image Usage: UPDBUG UPDBUG Freescale Semiconductor, Inc... The UPDBUG command update the dBUG image in Flash. When updates to the MCF5206e EVS dBUG are available, the updated image is downloaded to address 0x00020000. The new image is placed into Flash using the UPDBUG command. You are prompted for verification before performing the operation. Use this command with extreme caution as any error can render dBUG --and thus the board--useless. 2-42 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.27 UPUSER - Update User Code In Flash Usage: UPUSER <number of sectors> UPUSER The UPUSER command places user code and data into space allocated for you in Flash. Six sectors of 128K each are available as user space. To place code and data in user Flash, the image is downloaded to address 0x00020000 and the UPUSER command issued. This command programs all six sectors of user Flash space. You access this space starting at address 0xFFE20000. To program less than six sectors, supply the number of sectors you want to program after the UPUSER command. Examples: Freescale Semiconductor, Inc... To program all 6 sectors of user FLASH space, the command is: upuser or upuser 6 To program only 128K of user FLASH space, the command is: upuser 1 2-43 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.4.28 VERSION - Display dBUG Version Usage: VERSION VERSION The VERSION command displays the version information for dBUG. The dBUG version number and build date are both given. The version number is separated by a decimal, for example, v“ 1.1.1”. The first number indicates the version of the CPU specific code, the second indicates the version of the board specific code, and the third indicates the version of the board-specific code. The version date is the day and time at which the entire dBUG monitor was compiled and built. Freescale Semiconductor, Inc... Examples: To display the version of the dBUG monitor, the command is: version 2-44 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 2.5 TRAP #15 Functions An additional utility within the dBUG firmware is a function called the TRAP 15 handler. The user program to use various routines within the dBUG, to perform a special task, and to return control to the dBUG can call this function. This section describes the TRAP 15 handler and how it is used. There are four TRAP #15 functions. These are: OUT_CHAR, IN_CHAR, CHAR_PRESENT, and EXIT_TO_dBUG. Freescale Semiconductor, Inc... 2.5.1 OUT_CHAR This function ( function code 0x0013) sends a character, which is in lower 8 bits of D1, to terminal. Assembly example: /* assume d1 contains the character */ move.l #$0013,d0 Selects the function TRAP #15 The character in d1 is sent to terminal C example: void board_out_char (int ch) { /* If your C compiler produces a LINK/UNLK pair for this routine, * then use the following code which takes this into account */ #if l /* LINK a6,#0 -- produced by C compiler */ asm (“ move.l 8(a6),d1”); /* put ‘ch’into d1 */ asm (“ move.l #0x0013,d0”); /* select the function */ /* make the call */ /* UNLK a6 -- produced by C compiler */ #else /* If C compiler does not produce a LINK/UNLK pair, the use * the following code. */ asm (“ move.l 4(sp),d1”); /* put ‘ch’into d1 */ asm (“ move.l #0x0013,d0”); /* select the function */ /* make the call */ #endif } 2.5.2 IN_CHAR This function (function code 0x0010) returns an input character (from terminal) to the caller. The returned character is in D1. Assembly example: move.l #$0010,d0 trap #15 Select the function Make the call, the input character is in d1. C example: int board_in_char (void) { asm (“ move.l #0x0010,d0”); /* select the function */ asm (“ trap #15”); /* make the call */ asm (“ move.l d1,d0”); /* put the character in d0 */ 2-45 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. } 2.5.3 CHAR_PRESENT This function (function code 0x0014) checks if an input character is present to receive. A value of zero is returned in D0 when no character is present. A non-zero value in D0 means a character is present. Assembly example: move.l #$0014,d0 trap #15 Select the function Make the call, d0 contains the response (yes/no). Freescale Semiconductor, Inc... C example: int board_char_present (void) { asm (“ move.l #0x0014,d0”); /* select the function */ asm (“ trap #15”); /* make the call */ } 2.5.4 EXIT_TO_dBUG This function (function code 0x0000) transfers the control back to the dBUG, by terminating the user code. The register context are preserved. Assembly example: move.l #$0000,d0 trap #15 Select the function Make the call, exit to dBUG. C example: void board_exit_to_dbug (void) { asm (“ move.l #0x0000,d0”); asm (“ trap #15”); /* select the function */ /* exit and transfer to dBUG */ 2-46 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 3 HARDWARE DESCRIPTION AND RECONFIGURATION This chapter provides a functional description of the M5206EC3 board hardware (the schematics are located in Appendix C). In this manual, an active low signal is indicated by a dash ("-") preceding the signal name. 3.1 PROCESSOR AND SUPPORT LOGIC Freescale Semiconductor, Inc... This part of the chapter discusses the ColdFire processor and general supporting logic on the M5206EC3 board. 3.1.1 Processor Refer to Section 1.2 for a detailed description of the MCF5206e processor. The MCF5206e has an IEEE JTAG-compatible port and BDM port. These signals are available at port J5. The processor also has the logic to generate as many as eight chip selects (-CS0 to -CS7) and supports ADRAM. The processor defaults to the BDM debug mode. 3.1.2 Reset Logic The reset logic provides system initialization under two modes (under system power-up and when the RESET switch, S1 [red switch], is active). The power-on generates the master RESET by asserting the -RSTI and –HIZ that reset the total system. The RESET switch generates normal reset that resets the entire processor except for the DRAM controller. U11 and U12 produce active-low power-on RESET signals that feed the LSI2032V (U10) along with the push-button RESET. The U4 device generates the system reset (-RESET), FLASH and Ethernet RESET signals. DBUG configures internal resources during the initialization by invalidating and disabling the instruction cache. The Vector Base Register, VBR, points to the Flash. However, a copy of the exception table is made at address $00000000 in DRAM. To take over an exception vector, you must place the address of the exception handler in the appropriate vector in the vector table located at $00000000, and then point the VBR to $00000000. The software watchdog timer is disabled and internal timers are placed in a stop condition. Interrupt controller registers are initialized with unique interrupt level/priority pairs. The parallel I/O port is configured for input. 3.1.3 -HIZ Signal The –HIZ signal is actively driven by the LSI2032V (U10). This signal is available for monitoring on LA1 and J4. However, you should not drive this signal. If you need to drive –HIZ, it should be done through the –HIZ_INLOW signal that is available on J2 pin 26. The –HIZ_INLOW signal feeds the U10 that drives the –HIZ signal to the processor. 3-47 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... 3.1.4 Clock Circuitry The M5206EC3 uses a 54 MHz oscillator (U4) to provide the clock to the CLK pin of the processor. In addition to U4, a 20-MHz oscillator (U18) feeds into the Ethernet chip. U4 also drives the LSI2032 internal clock requirements. The 20-MHz oscillator is not used by the internal logic of the LSI2032 although it is connected in the schematic. 3.1.5 Watchdog Timer (Bus Monitor) The processor initiates a bus cycle that provides the necessary information for the bus cycle (e.g. address, data, control signals, etc.) and asserting the -CS or -RAS low. Then, the processor waits for an acknowledgment (-TA signal) from the addressed device before it can complete the bus cycle. It is possible (due to incorrect programming) that the processor can try to access part of the address space that physically does not exist. In this case, the bus cycle will continue forever because there is no memory or I/O device to provide an acknowledgment signal, leaving the processor in an infinite wait state. The MCF5206e has the necessary logic built into the chip to watch the duration of the bus cycle. If the cycle is not terminated within the preprogrammed duration, the logic will internally assert a transfer-error signal. In response, the processor will terminate the bus cycle and an access fault exception (trap) will occur. The duration of the watchdog is selected by BMT0-1 bits in System Protection Register. The dBUG initializes this register with the value 00, which provides for 1024 system clock time-out. 3.1.6 Interrupt Sources The ColdFire Family of processors can receive interrupts for seven levels of interrupt priorities. When the processor receives an interrupt that has higher priority than the current interrupt mask (in status register), it will perform an interrupt-acknowledge cycle at the end of the current instruction cycle. This interrupt-acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the device should provide the proper vector number to indicate where the service routine for this interrupt level is located. If the source of the interrupt can’t provide a vector, its interrupt should be set up as autovector interrupt, which directs the processor to a predefined entry into the exception table (refer to the MCF5206e User's Manual). The processor goes to a service routine via the exception table. This table is in the Flash and the VBR points to it. A copy of this table is made in the RAM starting at $00000000. To set an exception vector, place the address of the exception handler in the appropriate vector in the vector table located at $00000000, and then point the VBR to $00000000. The MCF5206e has three external interrupt request lines. You can program the external interrupt request pins to a interrupt priority-level signals (-IPL[2:0]) or predefined interrupt request pins (IRQ7, -IRQ4, -IRQ1). The M5206EC3 configures these lines as predefined interrupt request pins. The only interrupt signal used on the M5206EC3 is –IRQ4 and -IRQ7 for the Ethernet. By changing the external interrupt request pins to a interrupt priority-level signal, the Ethernet will no longer function. There are also six internal interrupt requests from Timer1, Timer2, software watchdog timer, UART1, UART2, and MBUS. You can program each external and internal for any priority level. In case of similar priority level, a second relative priority between 0 to 3 will be assigned. 3-48 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. The software watchdog is programmed for Level 7, priority 2, and uninitialized vector. The UART1 is programmed for Level 3, priority 2, and autovector. The UART2 is programmed for Level 3, priority 1, and autovector. The M-Bus is at Level 3, priority 0, and autovector. The timers are at Level 5 with Timer 1 with priority 3 and Timer 2 with priority 2 and both for autovector. Freescale Semiconductor, Inc... The M5206EC3 uses -IRQ7 to support the ABORT function using the ABORT switch S1 (red switch). This switch forces a nonmaskable interrupt (level 7, priority 3) if your program execution should be aborted without issuing a RESET (refer to Chapter 2 for more information on ABORT). Because the ABORT switch can’t generate a vector in response to level 7 interrupt acknowledge from the processor, the debugger programs this request for autovector mode. Additional circuitry prevents debouncing of the switch, which causes the ABORT signal to assert for a minimum of 30µ seconds. The -IRQ1 line of the MCF5206e is not used on this board. However, the -IRQ1 is programmed for Level 1 with priority 1 and autovector. You can use this line for external interrupt request. Refer to MCF5206e User’s Manual for more information about the interrupt controller. 3.1.7 Internal SRAM The MCF5206e has 8 KBytes of internal memory. This memory, which is mapped to 0x00400000, is not used by the dBUG but is available to users. 3.1.8 MCF5206e Registers and Memory Map The memory and I/O resources of the M5206EC3 are divided into three groups, MCF5206e internal, external resources, and the Ethernet controller. All the I/O registers are memory mapped. The MCF5206e has built-in logic and as many as eight chip-select pins (-CS0 to -CS7) that enable external memory and I/O devices. In addition, two -RAS lines are available for DRAMs and registers to specify the address range, type of access, and the method of -TA generation for each chip-select and -RAS pins. The dBUG programs these registers to map the external memory and I/O devices. The M5206EC3 uses chip-select zero (-CS0) to enable the Flash ROMs (refer to Section 3.3). The M5206EC3 uses -RAS1, -RAS2, -CAS0, -CAS1, -CAS2, and -CAS3 to enable the ADRAM SIMM module (refer to Section 3.2), -CS2 for SRAM (not populated), and -CS3 for Ethernet bus I/O space. The chip-select mechanism of the MCF5206e allows the memory mapping to be defined based on the memory space required (user/supervisor, program/data spaces). The MBAR register maps all MCF5206e internal registers, configuration registers, parallel I/O port registers, UART registers, and system control registers at any 1 KByte boundary. The dBUG maps MBAR to 0x10000000. For a complete map of these registers, refer to the MCF5206e User's Manual. The M5206EC3 board can have as much as 32 MBytes of 3.3V ADRAM installed. Refer to Section 3.2 for a discussion of RAM. The dBUG is programmed in two 29LV004B Flash ROMs that only occupy 1 MBytes of the address space. ROM monitor uses the first 128 KBytes. The following six 128 KByte sectors are available to users. Refer to section 3.3. 3-49 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. The Ethernet bus interface maps all the I/O space of the Ethernet bus to the MCF5206e memory at address $40000000. Refer to section 3.6. Table 4. ROM Monitor Default M5206EC3 Memory Map ADDRESS RANGE $00000000-$003FFFFF $00400000-$00401FFF $10000000-$100003FF $30000000-$3007FFFF1 SIGNAL and DEVICE -RAS1, -RAS2, 4 MBytes of ADRAMs Internal SRAM (8 KBytes) Internal Module registers -CS2, External SRAM (512 KBytes) Freescale Semiconductor, Inc... $40000000-$4000FFFFF -CS3, 1M Byte Ethernet Bus area $FFE00000-$FFEFFFFF -CS0, 1 MBytes of Flash ROM 1. Not installed. Level 2 cache footprint accepts Motorola’s MCM69F737TQ chip and any other SRAM with the same electrical specifications and package. All the unused area of the memory map is available to users. 3.1.9 Reset Vector Mapping After reset, the processor attempts to get the initial stack pointer and initial program counter values from locations $000000-$000007 (the first eight bytes of memory space). This operation requires the board to have a nonvolatile memory device in this range with proper information. However, in some systems, it is preferable to have RAM starting at address $00000000. In the MCF5206e, the -CS0 responds to any accesses after reset until the CSMR0 is written. Because CS0 is connected to the Flash ROMs, they appear to be at address $00000000, which provides the initial stack pointer and program counter (the first eight bytes of the Flash ROM). The initialization routine, however, programs the chip-select logic and locates the Flash ROMs to start at $FFE00000 and the DRAMs to start at $00000000. 3.1.10 -TA Generation The processor starts a bus cycle by providing the necessary information (address, R/-W, etc.) and asserting the -TS. The processor then waits for an acknowledgment (-TA) by the addressed device before it can complete the bus cycle. This -TA is used not only to indicate the presence of a device, it also allows devices with different access time to properly communicate with the processor . The MCF5206e, as part of the chip-select logic, has a built-in mechanism to generate the -TA for all external devices that do not have the capability to generate the -TA on their own. The Flash ROMs and DRAMs can not generate the -TA. Their chip-select logic is programmed by the ROM monitor to generate the -TA internally after a preprogrammed number of wait states. In order to support the future expansion of the board, the -TA input of the processor is also connected to the Processor Expansion Bus, J3, which allows the expansion boards to assert this line to indicate its -TA to the processor. On the expansion boards, however, this signal should be generated through an open collector buffer with no pullup resistor (a pullup resistor is included on the board). All the -TAs from the expansion boards should be connected to this line. 3.1.11 Wait State Generator The Flash ROMs and ADRAM SIMM on the board may require some adjustments on the cycle time of the processor to make them compatible with processor speed. To extend the CPU bus cycles for the slower devices, you can program the chip-select logic of the MCF5206e to generate the -TA after a given number of wait states. Refer to Sections 3.2 and 3.3 for information about wait state requirements of ADRAMs and Flash ROMs, respectively. 3-50 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 3.2 ADRAM SIMM The M5206EC3 has one 168-pin SIMM socket (U23) for ADRAM SIMM at 3.3 V. This socket supports DRAM SIMMs of 250Kx32, 1Mx32, 2Mx32, 4Mx32, and 8Mx32. No special configurations are needed. The dBUG will detect the total memory installed on power-up. The SIMM speed should be 60ns. (Note: NOT SV ADRAM SIMM). 3.3 FLASH ROM Freescale Semiconductor, Inc... There are two 512 KByte Flash ROMs on the M5206EC3: U13 (high, even byte), and U15 (low, odd byte). The board is shipped with two 29LV004, 512 KByte FLASH ROMs for a total of 1 MBytes. The first 128 KBytes and last 128 KBytes are reserved by the ROM monitor firmware. 768 KBytes are available to users. The chip-select signal generated by the MCF5206e (-CS0) enables both chips. You can program the MCF5206e chip-select logic to generate the -TA for -CS0 signal after a certain number of wait states. The dBUG programs this parameter to three wait states. 3.3.1 JP2 Jumper and User’s Program When the jumper is set between pins 1 and 2, the behavior is normal. When the jumper is set between pins 2 and 3, the board boots from the second half of Flash virtual address of (0x80000) physical address of (0xFFE80000). Procedure: 1. Compile and link as though the code was to be placed at the base of the Flash, but set up so that it will download to the ADRAM starting at address 0x80000. You need to refer to the compiler for this, as the procedure will depend on the compiler used (in Diab Data, a shadow in the linker file is used). 2. Set up the jumper for Normal operation, pin1 connected to pin 2. 3. Download to ADRAM (if using serial or Ethernet, start ROM monitor first. If using BDM via wiggler, download first, then start ROM monitor by pointing PC to 0xffe00400 and run.) 4. In ROM Monitor, run u“ puser”command. 5. Move the jumper to pins 2 and 3 and press r“eset”to execute the code in user space. 3.4 SERIAL COMMUNICATION CHANNELS The M5206EC3 offers a number of serial communications that are discussed in this section. 3.4.1 MCF5206e Two UARTs The MCF5206e has two built-in UARTs, each with its own software-programmable baud-rate generators. Only one channel serves as the ROM monitor-to-terminal output and the other is available to users. The ROM monitor, however, programs the interrupt level for UART1 to Level 3, priority 2, and autovector mode of operation. The interrupt level for UART2 is programmed 3-51 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. to Level 3, priority 1, and autovector mode of operation. The signals of these channels are available on port LA1 and J2. The signals of UART1 and UART2 are also passed through the RS-232 driver/receiver and are available on DB-9 connectors P1 and P2. Refer to the MCF5206e User’s Manual for programming and the register map. Freescale Semiconductor, Inc... 3.4.2 Motorola Bus (M-Bus) Module The MCF5206e has a built-in M-Bus module that allows interchip bus interface for a number of I/O devices. It is compatible with industry-standard I2C Bus. The M5206EC3 does not use this module and it is available to users. The two M-Bus signals are SDA and SCL that are available at the LA1 and J2 connector. These signals are open-collector signals. However, they have pullup resistors on the M5206EC3. These signals are connected to the ADRAM SIMM module I2C interface but not used by the debugger. The interrupt control register for M-Bus is set for Level 3, priority 0, and autovector. 3.5 PARALLEL I/O PORT The MCF5206e has one 8-bit parallel port. All the pins have dual functions and can be configured as I/O or their alternate function via the Pin Assignment Register. All pins are configured as I/O pins by the ROM monitor. 3.6 ONBOARD ETHERNET LOGIC The M5206EC3 includes the necessary logic, drivers, and the NE2000-compatible Ethernet chip to allow 10 Mbit transfer rate on a network. The Ethernet space addresses are located starting at 0x40000000. The interface base address is 0x300 and uses the ColdFire IRQ4. Thus, the address of the chip is 0x40000300. Note that all registers should be addressed as WORD (even though the registers are bytes) and that the even address registers are addressed as they are (no change); the read word will have the byte of the data in the lower byte of the word. For odd-addressed bytes, the address is mapped to 0x400083xx-1. Note that odd bytes are addressed as even addresses but increased by 0x8000. Still the read byte will be in the lower byte of the read word. Below is an example of the data structure used to define the registers. For the description of the registers, refer to the Data Sheet for Davicom DM9008, a copy of this document ion is available on the ColdFire web site at http://www.mot.com/ColdFire. typedef struct { NATURAL16 CR; union { struct { /* Even registers */ NATURAL16 CLDA1; /* NATURAL16 TSR; NATURAL16 FIFO; NATURAL16 CRDA0; /* NATURAL16 RBCR0; /* NATURAL16 RSR; NATURAL16 CNTR1; /* CLDA1 (rd) PSTOP (wr) */ /* TSR (rd) TPSR (wr) */ /* FIFO (rd) TBCR1 (wr) */ CRDA0 (rd) RSAR0 (wr) */ Remote Byte Count 0 (wr) */ /* RSR (rd) RCR (wr) */ CNTR1 (rd) DCR (wr) */ 3-52 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. NATURAL16 DATAPORT; NATURAL16 reserved[(0x10000-0x0012)/2]; /* Odd registers */ NATURAL16 CLDA0; /* NATURAL16 BNRY; NATURAL16 NCR; NATURAL16 ISR; NATURAL16 CRDA1; /* NATURAL16 RBCR1; /* NATURAL16 CNTR0; /* NATURAL16 CNTR2; /* } page0; struct { /* Even registers */ NATURAL16 PAR1; NATURAL16 PAR3; NATURAL16 PAR5; NATURAL16 MAR0; NATURAL16 MAR2; NATURAL16 MAR4; NATURAL16 MAR6; NATURAL16 CLDA0 (rd) PSTART (wr) */ /* Boundary pointer (rd wr) */ /* NCR (rd) TBCR0 (wr) */ /* Interrupt Status Register (rd wr) */ CRDA1 (rd) RSAR1 (wr) */ Remote Byte Count 1 (wr) */ CNTR0 (rd) TCR (wr) */ CNTR2 (rd) IMR (wr) */ /* /* /* /* /* /* /* Physical Address Byte 1 */ Physical Address Byte 3 */ Physical Address Byte 5 */ Multicast Address Byte 0 */ Multicast Address Byte 2 */ Multicast Address Byte 4 */ Multicast Address Byte 6 */ reserved[(0x10000-0x0010)/2]; /* Odd registers */ NATURAL16 PAR0; /* Physical Address Byte 0 */ NATURAL16 PAR2; /* Physical Address Byte 2 */ NATURAL16 PAR4; /* Physical Address Byte 4 */ NATURAL16 CURR; /* Current Page Register (rd wr) */ NATURAL16 MAR1; /* Multicast Address Byte 1 */ NATURAL16 MAR3; /* Multicast Address Byte 3 */ NATURAL16 MAR5; /* Multicast Address Byte 5 */ NATURAL16 MAR7; /* Multicast Address Byte 7 */ } page1; struct { /* Even registers */ NATURAL16 PSTOP; /* PSTOP (rd) CLDA1 (wr) */ NATURAL16 TPSR; /* Transmit Page Start Address (rd) */ NATURAL16 ACU; /* Address Counter Upper */ NATURAL16 reserved0; NATURAL16 reserved2; NATURAL16 RCR; /* Receive Configuration Register (rd) */ NATURAL16 DCR; NATURAL16 reserved[(0x10000-0x0010)/2]; /* Odd registers */ NATURAL16 PSTART; NATURAL16 RNPP; NATURAL16 LNPP; NATURAL16 ACL; NATURAL16 reserved1; NATURAL16 reserved3; NATURAL16 TCR; /* Data Configuration Register (rd) */ /* /* /* /* PSTART (rd) CLDA0 (wr) */ Remote Next Packet Pointer */ Local Next Packet Pointer */ Address Counter Lower */ /* Transmit Configuration Register (rd) */ NATURAL16 } page2; } regs; } NS8390; IMR; /* Interrupt Mask Register (rd) */ The main purpose for this setup is to allow the use of the Ethernet card (NE2000-compatible) to facilitate network download. Refer to Chapter 2 for the network download command (DN). The dBUG driver is 100 percent NE2000-compatible. The Ethernet Bus interrupt request line is hardwired to the ColdFire IRQ4. 3-53 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. The onboard ROM monitor lets you download files from a network to memory in different formats. The current formats supported are S-Record, COFF, ELF, or Image. 3.7 CONNECTORS AND THE EXPANSION BUS Freescale Semiconductor, Inc... There are 10 connectors on the M5206EC3 that connect the board to external I/O devices and or expansion boards. This section provides a brief discussion and the pin assignments of the connectors. 3.7.1 The Terminal Connector P1 The signals on UART1 that run through the RS-232 driver/receivers drive the terminal. The M5206EC3 uses a 9-pin D-sub female connector P1 for connecting the board to a terminal or a PC with terminal emulation software. The available signals are a working subset of the RS-232C standard. Table 5, the P1 (Terminal) Connector pin assignment, shows the pin assignment. Table 5. P1 (Terminal) Connector Pin Assignment PIN NO. 1 2 3 4 5 6 7 8 9 DIRECTION Output Output Input Input Output Input Output SIGNAL NAME Data Carrier Detect (shorted to 4 & 6) Receive data Transmit data Data Terminal Ready (shorted to 1 & 6) Signal Ground Data Set Ready (shorted to 1 & 4) Request to Send Clear to Send Not Used 3.7.2 The Auxiliary Serial Communication Connector P2 The MCF5206e has two built-in UARTs. One channel on port P2, which is not used by the M5206EC3 ROM monitor, is available to users. The available signals form a working subset of the RS-232C standard. Table 6, the P2 Connector Pin Assignment, shows the pin assignment for P2. Table 6. P2 Connector Pin Assignment PIN NO. 1 2 3 4 5 6 7 8 9 DIRECTION Output Output Input Input Output Input Output SIGNAL NAME Data Carrier Detect (shorted to 4 & 6) Receive data Transmit data Data Terminal Ready (shorted to 1 & 6) Signal Ground Data Set Ready (shorted to 1 & 4) Request to Send Clear to Send Not Used 3.7.3 Logical Analyzer Connectors LA1-4 and Processor Expansion Bus J2, J3, and J4 All the processor signals are available on four mictor connectors (LA1-4). You can refer to the data sheets for the major parts and the schematic at the end of this manual to get an accurate 3-54 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. loading capability. Subsets of the signals are available on J2, J3, and J4 for easier access. Tables 7 through 13 show the pin assignment for J2, J3, J4, LA1, LA2, LA3, and LA4, respectively. Freescale Semiconductor, Inc... Table 7. J2 Connector Pin Assignment PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 SIGNAL NAME -CS0 -CS1 -CS2 -CS3 -IRQ4 -BR -BD -BG SDA SCL -IRQ7 +5V GND +5V PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 SIGNAL NAME -CTS1 TXD1 RXD1 -RTS1 -CTS2 -RTS2 RXD2 TXD2 TIN0 TIN1 TOUT0 TOUT1 HIZ_INLOW +5V 3-55 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 8. J3 Connector Pin Assignment PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 SIGNAL NAME A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 54 MHz CLK GND PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 SIGNAL NAME D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 TT0 TT1 ATM SIZ0 SIZ1 R/-W -TS -TA -TEA -ATA -RSTI -IRQ1 +5V GND 3-56 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 9. J4 Connector Pin Assignment PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 SIGNAL NAME TCLK DSCLK DSDI DSDO BKPT +5V GND PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 -HIZ MTMOD -RAS0 -RAS1 -DRAMW PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 SIGNAL NAME D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 -CAS0 -CAS1 -CAS2 -CAS3 Table 10. LA1 Connector Pin Assignment PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 SIGNAL NAME NC NC PP5 PP7 SDA TOUT1 TIN0 TXD1 -CTS1 RXD2 NC NC NC -TRST/DSCLK TDO/DSO TDI/DSI MTMOD -RTS2 NC GND GND GND PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 SIGNAL NAME NC PP4 PP6 SCL TOUT0 TIN1 TXD1 -RTS1 TXD2 NC NC NC NC TCLK -HIZ TMS/-BKPT -CTS2 NC NC GND GND 3-57 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 11. LA2 Connector Pin Assignment PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 SIGNAL NAME NC 54 MHz CLK A26 A24 A22 A20 A18 A16 A14 A12 PP2 PP0 A1 A3 A5 A7 A9 A11 NC GND GND GND PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 SIGNAL NAME NC A27 A25 A23 A21 A19 A17 A15 A13 PP3 PP1 A0 A2 A4 A6 A8 A10 20 MHz CLK NC GND GND Table 12. LA3 Connector Pin Assignment PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 SIGNAL NAME NC NC -CAS3 -CAS1 -RAS1 -BG -BR -IRQ4 -ATA -TS NC NC -CS1 -CS3 TT1 SIZ0 R/-W -TEA NC GND GND GND PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 SIGNAL NAME NC -DRAW -CAS2 -CAS0 -RAS0 -BD -IRQ1 -IRQ7 -RSTI NC NC -CS0 -CS2 TT0 ATM SIZ1 -TA NC NC GND GND 3-58 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Table 13. LA4 Connector Pin Assignment PIN NO. SIGNAL NAME PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 NC NC D1 D3 D5 D7 D9 D11 D13 D15 D30 D28 D26 D24 D22 D20 D18 D16 NC GND GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 SIGNAL NAME NC D0 D2 D4 D6 D8 D10 D12 D14 D31 D29 D27 D25 D23 D21 D19 D17 NC NC GND GND 3-59 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 3.7.4 Debug Connector J5 The MCF5206e has a background debug port, real-time trace support, and real-time debug support available at connector J5. Table 14 (The J5 Connector Pin Assignment) shows the pin assignment. Freescale Semiconductor, Inc... Table 14. J5 Connector Pin Assignment PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 SIGNAL NAME No Connect -BKPT Ground DSCLK Ground No Connect -RESET DSI +3.3 Volts DSO Ground PST3 PST2 PST1 PST0 DDAT3 DDAT2 DDAT1 DDAT0 Ground 10K pull down No Connect Ground 54 MHz CLK 3.3 Volts -TA 3-60 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Appendix A CONFIGURING dBUG FOR NETWORK DOWNLOADS The dBUG module can perform downloads over an Ethernet network using the Trivial File Transfer Protocol (TFTP). Before using this feature, several parameters are required for network downloads to occur. This information and the steps for configuring dBUG are described below. A.1 Required Network Parameters Freescale Semiconductor, Inc... For performing network downloads, dBUG requires six parameters: four that are networkrelated; two that are download-related. These parameters are listed below with the dBUG designation following in parenthesis. All computers connected to an Ethernet network running the IP protocol need three networkspecific parameters. These parameters are: • Internet Protocol, IP, address for the computer (client IP) • IP address of the Gateway for non-local traffic (gateway IP) • Network netmask for flagging traffic as local or non-local (netmask) In addition, the dBUG network download command requires the following three parameters: • IP address of the TFTP server (server IP) • Name of the file to download (filename) • Type of the file to download (file type of S-record, COFF, ELF, or Image) Your local system administrator can assign a unique IP address for the board and also provide you with the IP addresses of the gateway, netmask, and TFTP server. Fill out the lines below with this information. Client IP: Server IP: Gateway: Netmask: ___.___.___.___ ___.___.___.___ ___.___.___.___ ___.___.___.___ (IP address of the board) (IP address of the TFTP server) (IP address of the gateway) (Network netmask) 1 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. A.2 Configuring dBUG Network Parameters Once the network parameters have been obtained, you must configure the ROM monitor. The following commands are used to configure the network parameters. set client <client IP> set server <server IP> set gateway <gateway IP> set netmask <netmask> set Macaddr <macaddr> Freescale Semiconductor, Inc... For example, the TFTP server is named s“antafe” and has IP address 123.45.67.1. The board is assigned the IP address of 123.45.68.15. The gateway IP address is 123.45.68.250, and the netmask is 255.255.255.0. The commands to dBUG are as follows: set client 123.45.68.15 set server 123.45.67.1 set gateway 123.45.68.250 set netmask 255.255.255.0 set Macaddr 00:00:00:00:00:00 The last step is to inform dBUG of the name and type of the file to download. Prior to giving the name of the file, keep in mind the following: 1. Most, if not all, TFTP servers will permit access only to files starting at a particular subdirectory. (This is a security feature that prevents reading of arbitrary files by unknown persons.) For example, SunOS uses the directory /tftp_boot as the default TFTP directory. When specifying a filename to a SunOS TFTP server, all filenames are relative to /tftp_boot. As a result, you normally will be required to copy the file to download into the directory the TFTP server uses. 2. A default filename for network downloads is maintained by dBUG. To change the default filename, use the command: set filename <filename> 3. When using the Ethernet network for download, S-record, COFF, ELF, or Image files can be downloaded. A default file type for network downloads is maintained by dBUG as well. To change the default file type, use the command: set filetype <srecord|coff|elf|image> 4. Continuing with the above example, the compiler produces an executable COFF file, a“.out”. This file is copied to the /tftp_boot directory on the server with the command: rcp a.out santafe:/tftp_boot/a.out 5. Change the default filename and file type with the commands: 2 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. set filename a.out set filetype coff 6. Finally, perform the network download with the d“ n”command. The network download process uses the configured IP addresses and the default filename and file type for initiating a TFTP download from the TFTP server. A.3 Troubleshooting Network Problems Freescale Semiconductor, Inc... Most problems related to network downloads are a direct result of improper configuration. Verify that all IP addresses configured into dBUG are correct (use the s“how”command). Using an IP address already assigned to another machine will cause the dBUG network download to fail, and probably create other severe network problems. Make certain the client IP address is unique for the board. Check for proper insertion or connection of the network cable. Is the status LED lit indicating that network traffic is present? Check for proper configuration and operation of the TFTP server. Most Unix workstations can execute a command named t“ftp”that can connect to the TFTP server as well. Is the default TFTP root directory present and readable? The “ICMP_DESTINATION_UNREACHABLE” or similar ICMP message signifies a serious error has occurred. Reset the board, and wait one minute for the TFTP server to time out, and terminate any open connections. Verify that the IP addresses for the server and gateway are correct. 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Appendix B FPLA CODE module isa2 title 'isa controller' "Feb 26 '98 version v1 of the 5206e "isa2 device 'ispLSI'; ;"*****************************************************" ;"This abel file contains the code for a NE2000 compatible ethernet" ;"for the 55206e Coldfire processor as well as reset and IRQ7 (abort)" ;"It was targeted to Lattice ispLSI 2032 fpga " ;"CS: B3D3 " ;"*****************************************************" ;"*****************************************************" ;"Declaration Section " ;"*****************************************************" ;" constants" C,P,X,Z,H,L = .C.,.P.,.X.,.Z.,1,0; ;"*****************************************************" DLYIOCHRDY0 node ISTYPE 'reg_d,buffer'; DLYIOCHRDY,ENDIT,END16,END8 node; STARTISA node ISTYPE 'reg_d,buffer'; SBHE,IOR,IOW,ISAOE node; DA,DLYDA node ISTYPE 'reg_d,buffer'; ABORTML,DAOE,CLK16MHZ,CLK8MHZ node ISTYPE 'reg_d,buffer'; CLK2MHZ RSTMH BCLK0 BCLK1 BCLK2 node ISTYPE 'reg_d,buffer'; node; node ISTYPE 'reg_d,buffer'; node ISTYPE 'reg_d,buffer'; node ISTYPE 'reg_d,buffer'; DSL, ISASWAPL, SBHEL, ISAOEL, DTACKL, ISASELL node; ABORTOL RST_L DB_CS_L A0IN IOCHRDY IOCS16L SIZ1 XCLK0 IOWL RD CLK4MHZ BALE A0 CS3_L HIZ_INLOW PORIN_L pin 3 ISTYPE 'reg_d, buffer'; pin 4; "Output - to ColdFire reset pin 5; "Output - Data buffer enable for ethernet pin 6; "INPUT - A0 received from CF through buffers pin 7; "Input - asserted by ethernet pin 9; "Input - asserted by ethernet pin 10; pin 11; "Input - global clock pin 15; "Input - write signal from ethernet pin 16; "INPUT - R/-W from the ColdFire pin 17 ISTYPE 'reg_d,buffer'; pin 18; "Output - address latch enable pin 19; "OUTPUT - A0 sent to the ethernet pin 22; "Input - From ColdFire pin 25; "Input - From Header to allow a HIZ pin 26; "Input - Suppy Voltage Supervisor EIRQ IRQ4_L ETHER_RST ABORTIL Abort swith HIZ_L IORL OE_FLASH_L A16 TAL BDM_RST SIZ0 "BDM_RST_L pin pin pin pin XCLK1 pin 35; 28; 29; 30; 31; "Input "Output "Input "INPUT pin pin pin pin pin 32; 37; 38; 39; 40; pin 41; pin 43; pin 44; - Ethernet IRQ 3 IRQ 3 into the ColdFire Hard Reset switch abort signal received from the "Output - to ColdFire *HIZ "Input - read signal from ethernet "Output - Flash output enable "Input / Output - Transfer acknowledge "Input - Reset from the BDM Input - BDM reset input "Clock - 20MHz 5 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. ; "********************************" ; " Lattice attributes " ; "********************************" pLSI property 'CLK CLK54 CLK0 '; pLSI property 'CLK XCLK0 CLK1 '; pLSI property 'CLK CLK8MHZ SLOWCLK '; pLSI property 'ISP ON'; pLSI property 'PULLUP ON'; pLSI property 'Y1_AS_RESET OFF'; Freescale Semiconductor, Inc... ; "--------------------------------" ; " Output inverter macro " ; "--------------------------------" OB21 MACRO (XO0, A0) { ?XO0 = !?A0; }; ; "--------------------------------" ; " Tristate Output inverter macro " ; "--------------------------------" OT21 MACRO (XO0, A0, OE) { ?XO0.OE = ?OE; ?XO0 = !?A0; }; CBU43 MACRO (Q0,Q1,Q2,CLK,EN,CS) { [?Q0..?Q2].clk = ?CLK; ?Q0.D = ?Q0.Q & !?CS $ ?EN & !?CS ; ?Q1.D = ?Q1.Q & !?CS $ ( ?Q0.Q & ?EN & !?CS ); ?Q2.D = ?Q2.Q & !?CS $ ( ?Q0.Q & ?Q1.Q & ?EN & !?CS ); }; equations ;"###########################################" ;"Bidirectional circuit equations" ;"###########################################" OT21 (TAL, DA, DAOE) OB21 (IORL, IOR) OB21 (IOWL, IOW) "new for the M5206e OE_FLASH_L = !RD; "Same as the M5206e IRQ4_L = !EIRQ # !PORIN_L; "used to enable the data buffers to the ethernet !DB_CS_L = !ETHER_RST & !CS3_L; ABORTML := ABORTIL ; ABORTML.clk = CLK4MHZ ; ABORTOL := ABORTML ; ABORTOL.clk = CLK4MHZ ; "Ethernet reset ETHER_RST = !PORIN_L # !BDM_RST; 6 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. "CPU reset !RST_L = !PORIN_L # !BDM_RST; !HIZ_L = !RST_L # !HIZ_INLOW; " # !BDM_RST; DAOE := !CS3_L # DA; DAOE.clk = XCLK0 ; A0 = SBHE = !SIZ1 & SIZ0 & !A0IN # A16 ; STARTISA & !SIZ1 & SIZ0 & !A0IN # STARTISA & SIZ1 & !SIZ0 & !A0IN # STARTISA & !SIZ1 & !SIZ0 & !A0IN ; CLK16MHZ := !CLK16MHZ ; CLK16MHZ.clk = XCLK0 ; Freescale Semiconductor, Inc... CLK8MHZ := CLK8MHZ & !CLK16MHZ # !CLK8MHZ & CLK16MHZ ; CLK8MHZ.clk = XCLK0 ; CLK4MHZ := CLK4MHZ $ ( CLK16MHZ & CLK8MHZ ); CLK4MHZ.clk = XCLK0 ; CLK2MHZ := CLK2MHZ $ ( CLK4MHZ & CLK16MHZ & CLK8MHZ ); CLK2MHZ.clk = XCLK0 ; DA := !CS3_L & END16 & ENDIT & !IOCS16L & RD & !CLK4MHZ & SBHE # !CS3_L & END8 & ENDIT & RD & !CLK4MHZ # DLYDA & !CS3_L # DA & !CS3_L; DA.clk=XCLK0; DLYDA :=!CS3_L & END16 & ENDIT & !IOCS16L & !RD & !CLK4MHZ & SBHE # !CS3_L & END8 & ENDIT & IOCS16L & !RD & !CLK4MHZ # !CS3_L & END8 & ENDIT & !SBHE & !RD & !CLK4MHZ ; DLYDA.clk=XCLK0; STARTISA := !CS3_L & !ENDIT ; STARTISA.clk = CLK4MHZ ; CBU43 (BCLK0,BCLK1,BCLK2,CLK4MHZ,STARTISA,!STARTISA) BALE = STARTISA & !CLK4MHZ & !BCLK2 & !BCLK1 & !BCLK0 & !IOR & !IOW ; IOR = STARTISA & !BCLK2 & !BCLK1 & BCLK0 & !CLK4MHZ & RD # IOR & !CS3_L ; IOW = STARTISA & !BCLK2 & !BCLK1 & BCLK0 & !CLK4MHZ & !RD # IOW & STARTISA ; END16 = !BCLK2 & BCLK1 & !BCLK0 & !CLK4MHZ# END16 & STARTISA ; END8 = BCLK2 & !BCLK1 & BCLK0 & !CLK4MHZ # END8 & STARTISA ; ENDIT = STARTISA# END8 END8 END16 & !IOCS16L & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & SBHE & & IOCS16L & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & STARTISA # & !SBHE & IOCHRDY & DLYIOCHRDY0 & DLYIOCHRDY & STARTISA ; DLYIOCHRDY0:= IOCHRDY; DLYIOCHRDY0.clk = CLK4MHZ ; 7 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DLYIOCHRDY = IOCHRDY & CLK4MHZ # Freescale Semiconductor, Inc... DLYIOCHRDY & !CLK4MHZ ; 8 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Appendix C SCHEMATICS 9 10 Tuesday, July 07, 1998 Freescale Semiconductor, Inc... SIP3 VDD 1 VDD VDD 1 VCC 9x4.7K 6 12 18 24 30 36 44 52 60 69 77 86 94 102 110 118 128 140 150 160 2 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 VCC 9x4.7K R1 R2 R3 R4 R5 R6 R7 R8 R9 VCC 9x4.7K R1 R2 R3 R4 R5 R6 R7 R8 R9 1 R1 R2 R3 R4 R5 R6 R7 R8 R9 SIP1 SIP2 VDD VCC0 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 Power Analysis JP3 59 *IRQ7 *IRQ4 *IRQ1 62 63 64 66 67 68 TMS/*BKPT TDI/DSI TDO/DSO *HIZ *TRST/DSCLK TCK 127 126 124 125 121 122 TT0 TT1 ATM SIZ0 SIZ1 R/*W *TS *TA *TEA *ATA *RAS[1:0] *CAS[3:0] *DRAMW MTMOD *CTS2 *RTS2/*RSTO RXD2 TXD2 *CTS1 *RTS1 RXD1 TXD1 TIN0 TIN1 TOUT0 TOUT1 SCL SDA 159 158 157 156 154 153 152 151 47 49 50 51 53 54 58 55 57 61 70 71 72 74 75 76 78 *RAS0 *RAS1 *CAS0 *CAS1 *CAS2 *CAS3 129 135 132 133 136 137 138 139 141 142 143 144 146 147 148 149 *IRQ7 *IRQ4 *IRQ1 *BR *BD *BG TMS/*BKPT TDI/DSI TDO/DSO *HIZ *TRST/DSCLK TCK PP0/DDATA0 PP1/DDATA1 PP2/DDATA2 PP3/DDATA3 PP4/PST0 PP5/PST1 PP6/PST2 PP7/PST3 U1 MCF5206EFT A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 TT0 TT1 ATM SIZ0 SIZ1 R/*W *TS *TA *TEA *ATA 42 *CS0 43 *CS1 45 *CS2 46 *CS3 *CS0 *CS1 *CS2 *CS3 *RAS0 *RAS1 *CAS0 *CAS1 *CAS2 *CAS3 *DRAMW MTMOD CLK *CTS2 *RTS2/*RSTO RXD2 TXD2 *CTS1 *RTS1 RXD1 TXD1 TIN0 TIN1 TOUT0 TOUT1 SDA SCL D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 120 119 117 116 115 113 112 111 109 108 107 105 104 103 101 100 99 97 96 95 93 92 91 89 88 87 85 84 83 81 80 79 A[27:0] *CS[3:0] D[31:0] D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 U4 VDD R9 1 NC VCC GND CLK 14 3 9 15 21 27 33 39 48 56 65 73 82 90 98 106 114 123 134 145 155 130 131 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 Freescale Semiconductor, Inc... *BR *BD *BG *RSTI GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 *RSTI 1 2 4 5 7 8 10 11 13 14 16 17 19 20 22 23 25 26 28 29 31 32 34 35 37 38 40 41 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24/CS4/WE3 A25/CS5/WE2 A26/CS6/WE1 A27/CS7/WE0 VDD 4.75K R10 7 4.75K 8 54MHZ CLK 54MHz R11 4.75K Tuesday, July 07, 1998 11 J2 Chip Select 0 CS0_HEADER J3 VCC VCC A[27:0] *CAS3 *CAS2 *CAS1 *CAS0 *RAS1 *RAS0 *RAS[1:0] *BG *BD *BR *IRQ1 *IRQ4 *IRQ7 *ATA *CS[3:0] 1 NC1 2 NC2 37 NC3 38 NC4 *RSTI *TS *TEA *TA R/*W SIZ1 SIZ0 ATM TT1 TT0 *CS3 *CS2 *CS1 *CS0 VCC 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 Mictor 3 36 CLK 1 CLK 2 CLK 1 CLK 2 LA3 *DRAMW *CAS[3:0] LA4 D[31:0] 1 NC1 2 NC2 37 NC3 38 NC4 J4 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 J5 BDM_RESET R23 VDD 10K 1 3 5 7 9 11 13 15 17 19 21 23 25 RSV0 GND0 GND1 *RESETI VCC GDN2 PST2 PST0 DDATA2 DATA0 RSV1 GND3 VDD BKPT DSCLK RSV3 DSDI DSDO PST3 PST1 DDATA3 DDATA1 GND4 RSV2 CLK_CPU *TA 2 4 6 8 10 12 14 16 18 20 22 24 26 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEADER 30X2 GND1 GND2 GND3 GND4 GND5 Mictor 3 36 3 36 PP0 PP1 PP2 PP3 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 39 40 41 42 43 Mictor 1 NC1 2 NC2 37 NC3 38 NC4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND1 GND2 GND3 GND4 GND5 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 39 40 41 42 43 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 LA2 CLK 1 CLK 2 LA1 GND1 GND2 GND3 GND4 GND5 PP4 PP5 PP6 PP7 SCL SDA TOUT0 TOUT1 TIN1 TIN0 TXD1 RXD1 *RTS1 *CTS1 TXD2 RXD2 *RTS2 *CTS2 MTMOD TMS/*BKPT TDI/DSI *HIZ TDO/DSO TCLK *TRST/DSCLK 20MHZ CLK 39 40 41 42 43 54MHZ CLK Freescale Semiconductor, Inc... PP[7:0] 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 3 36 2x14 Header 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 Mictor HEADER 20X2 BDM connector 12 Tuesday, July 07, 1998 CLK 1 CLK 2 VCC TP1 1 *CS0 *CS1 *CS2 *CS3 1 NC1 2 NC2 37 NC3 38 NC4 GND1 GND2 GND3 GND4 GND5 HIZ_INLOW 1 3 5 7 9 11 13 15 17 19 21 23 25 27 39 40 41 42 43 2 4 6 8 10 12 14 16 18 20 22 24 26 28 A[27:0] B_D[31:16] D[31:0] *DRAMW *RAS0 *RAS1 2 4 6 8 *CAS3 *CAS2 *CAS1 *CAS0 17 15 13 11 *CAS[3:0] VDD 20 12 13 14 15 16 17 18 28 31 32 19 44 45 34 33 40 43 41 42 47 VCC VCC VCC R48 270 R47 270 R42 270 R43 270 R44 270 R45 270 R46 270 10 30 59 1 39 72 67 68 69 70 71 66 48 46 36 A0 A1 A2 A3 A4 A5 A6 A7 A8 NC/A9 NC/NC/A10 *RAS0 *RAS1 *RAS2 *RAS3 *CAS0 *CAS1 *CAS2 *CAS3 *WE VCC0 VCC1 VCC2 1 to 32Meg, 72 pin simm socket A9 A10 A11 A12 A13 A14 A15 A17 A19 A21 A23 VSS0 VSS1 VSS2 PD1 PD2 PD3 PD4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 NC1 NC2 NC3 NC4 NC5 2 4 6 8 20 22 24 26 49 51 53 55 57 61 63 65 3 5 7 9 21 23 25 27 50 52 54 56 58 60 62 64 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 *BD_CS R/*W VDD 48 25 1 24 7 18 42 31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 OE1 OE2 DIR1 DIR2 VCC0 VCC1 VCC2 VCC3 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 11 29 35 37 38 NC6 NC7 NC8 NC9 NC10 U23 1D0 1D1 1D2 1D3 2D0 2D1 2D2 2D3 VDD MC74LCX244DT *RAS[1:0] Freescale Semiconductor, Inc... U7 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 MC74LCX16245DT U6 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 1O0 1O1 1O2 1O3 2O0 2O1 2O2 2O3 1OE 2OE GND 18 16 14 12 3 5 7 9 1 19 10 13 Tuesday, July 07, 1998 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 4 10 15 21 28 34 39 45 B_D16 B_D17 B_D18 B_D19 B_D20 B_D21 B_D22 B_D23 B_D24 B_D25 B_D26 B_D27 B_D28 B_D29 B_D30 B_D31 D[31:0] A[27:0] U13 JP1 4.75K BCLK 3 J3 2 J2 1 J1 JP2 FLASH 22 24 9 U14 37 36 R25 R26 4.75K 4.75K 32 33 34 35 44 45 46 47 48 49 50 81 82 99 100 84 83 85 89 86 87 88 31 98 97 92 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 MCM69F737TQ11 *ADSP *ADV *ADSC QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 QA8 QB9 QB10 QB11 QB12 QB13 QB14 QB15 QB16 QB17 QC18 QC19 QC20 QC21 QC22 QC23 QC24 QC25 QC26 K *G *SW *SGW *SBA *SBB *SBC *SBD *LBO *SE1 *SE2 *SE3 35 34 33 32 28 27 26 25 30 VCC0 31 VCC1 11 NC0 29 NC1 37 NC2 38 NC3 *CE *OE GND0 GND1 23 39 *WE *RESET *RY_BY 12 14 16 38 39 42 43 64 66 10 93 94 95 96 *CS2 3 1x3 QD27 QD28 QD29 QD30 QD31 QD32 QD33 QD34 QD35 51 52 53 56 57 58 59 62 63 68 69 72 73 74 75 78 79 80 1 2 3 6 7 8 9 12 13 U15 13 40 1 2 3 4 5 6 36 7 8 14 15 16 17 18 19 20 21 22 24 9 10 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 AM29LV004T-100EI R24 J3 *CS0_Header 2 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 SYS_RESET J2 4.7K 1 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDD0 VDD1 VDD2 VDD3 *OE_FLASH J1 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 35 34 33 32 28 27 26 25 30 VCC0 31 VCC1 11 NC0 29 NC1 37 NC2 38 NC3 *CE *OE GND0 GND1 23 39 *WE *RESET *RY_BY 12 18 19 22 23 24 25 28 29 30 5 10 17 21 26 40 55 60 67 71 76 90 4 11 20 27 54 61 70 77 15 41 65 91 *CS0 Freescale Semiconductor, Inc... R39 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 AM29LV004T-100EI 13 40 1 2 3 4 5 6 36 7 8 14 15 16 17 18 19 20 21 Tuesday, July 07, 1998 14 VCC R28 4.75K U16 A[27:0] VCC R32 R33 4.75K 4.75K Freescale Semiconductor, Inc... B_D[31:16] 4.75K SA0 96 97 98 99 3 4 5 7 9 11 12 13 A1 A2 A3 A4 A5 A6 A7 A8 A9 15 16 17 18 20 22 R34 VCC R38 26 27 28 29 30 31 32 33 88 87 86 85 84 83 82 81 B_D16 B_D17 B_D18 B_D19 B_D20 B_D21 B_D22 B_D23 B_D24 B_D25 B_D26 B_D27 B_D28 B_D29 B_D30 B_D31 BALE 2 PALCLK 14 *IOR *IOW 19 21 4.75K 23 SYS_RESET 35 24 89 90 L1 36 47 48 FERRITE_BEAD C14 .01uF C15 10uF 43 44 51 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 MSD0_EEDI MSD1_EEDO MSD2_EECK MSD3 MSD4 MSD5_BNCSW MSD6_SLOT MSD7 BALE SYSCLK *IOR *IOW *SMEMR RST *AEN *MEMW *MEMR AVDD0 AVDD1 AVDD2 AGND0 AGND1 AGND2 U17 1 2 3 4 64 65 66 67 68 69 70 71 8 VCC 7 NC 6 ORG 5 GND CS SK DI DO AT93C46-10SC-2.7 R29 4.75K 79 EECS 80 *BPCS PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 IRQ11 IRQ12 IRQ15 *IO16 *IOCHRDY X1 X2 SA14 SA15 SA16 SA17 SA18 SA19 VCC BNCEN TX+ TXRX+ RXCD+ CD- 63 62 61 60 59 58 57 56 6 8 10 34 94 93 92 91 ETHER_IRQ3 95 *IO16 25 *IOCHRDY 78 77 20MHZ_CLK 54 R30 4.75K 38 37 40 39 42 41 R31 22 U18 1 7 NC VCC GND CLK 14 VCC 8 20MHz 50 TPTX+ 49 TPTX46 TPRX+ 45 TPRXLILED 55 TPTX+ 2 3 R35 D11 270 1 VCC0 53 VCC1 72 VCC2 GND0 GND1 GND2 GND3 GND4 NC 1 6 VCC LED 7 8 73 74 75 52 100 76 C12 .1uF TXB+ NC1 TXD- TXB- TPRX+ RXB+ GRN2 NC2 TPRX- RXB- 16 P5 1 2 3 4 5 6 7 8 15 14 11 10 Gray Brown Yellow Green Red Black Orange Blue RJ 45 8P 9 C13 .1uF R36 R37 50 50 C16 .01uF DM9008F Tuesday, July 07, 1998 15 of PP4 PP5 PP6 PP7 17 15 13 11 VDD 20 1D0 1D1 1D2 1D3 2D0 2D1 2D2 2D3 VDD Freescale Semiconductor, Inc... PP[7:0] 2 4 6 8 MC74LCX244DT U24 PP0 PP1 PP2 PP3 18 1O0 16 1O1 14 1O2 12 1O3 3 2O0 5 2O1 7 2O2 9 2O3 1 1OE 19 2OE 10 GND TXD1 RXD1 15 16 *RTS1 *CTS1 13 14 11 12 1 3 VCC R1 R2 R3 R4 R5 R6 R7 R8 270 270 270 270 270 270 270 270 D1 D2 D3 D4 D5 D6 D7 D8 LED LED LED LED LED LED LED LED 19 17 TXD2 RXD2 14 15 *RTS2 *CTS2 12 13 10 11 16 1 DO1 6 TX1 5 RX1 DI2 DO2 8 TX2 7 RX2 DI3 DO3 10 TX3 9 RX3 C2+ C2- 20 C1+ 18 C1- VCC VDD 4 VSS 2 GND DO1 3 TX1 2 RX1 DI2 DO2 5 TX2 4 RX2 DI3 DO3 7 TX3 6 RX3 VCC VDD 8 VSS 9 GND 5 9 4 8 3 7 2 6 1 5 9 4 8 3 7 2 6 1 Tuesday, July 07, 1998 16 VDD R13 270 VCC U10 R14 4.75K U11 1 CONTROL U12 VDD SENSE S1 2 3 Hard Reset Freescale Semiconductor, Inc... 1 D9 7 *RESIN CT GND *RESET REF 3.3V VCC SENSE 2 3 RESET 4 8 6 *RESIN CT 4 GND 8 7 R15 *RESET 6 HIZ_INLOW TLC7733ID TLC7705ID C8 .1uF *CS3 5 Ether_RESET ETHER_IRQ3 *IRQ4 SYS_RESET D10 C7 .1uF 15 16 17 18 19 20 21 22 25 26 27 28 29 30 31 32 270 RESET 5 *IOW R/*W PALCLK BALE SA0 5V C9 .1uF *HIZ R16 270 24 14 13 36 33 54MHZ CLK 11 35 20MHZ_CLK 2 I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 I/O_8 I/O_9 I/O_10 I/O_11 I/O_12 I/O_13 I/O_14 I/O_15 I/O_31 I/O_30 I/O_29 I/O_28 I/O_27 I/O_26 I/O_25 I/O_24 I/O_23 I/O_22 I/O_21 I/O_20 I/O_19 I/O_18 I/O_17 I/O_16 10 09 08 07 06 05 04 03 44 43 42 41 40 39 38 37 SIZ1 *IO16 *IOCHRDY A0 *BD_CS *RSTI SIZ0 BDM_RESET *TA A16 *OE_FLASH *IOR *IN_1_TDO *IN_0_TDI *IPSEN 12 VCC0 34 VCC1 *MODE VDD Y 2_SCLK Y0 *Y1_RESET 1 GND0 23 GND1 GOE VDD ispLSI2032V-100LJ44 VCC J1 R41 4.75K 1 2 3 4 5 6 7 8 U25 1 CONTROL VDD SENSE S2 2 3 IRQ7 *RESIN CT RESET 4 GND *RESET 8 7 6 R17 4.75K ispHeader 5 *IRQ7 C11 R18 4.75K R19 4.75K R20 4.75K R22 4.75K .01uF TLC7733ID C77 .001uF VDD B Tuesday, July 07, 1998 17 8 of 9 VDD C17 1000pF C18 1000pF C19 1000pF C20 1000pF C21 1000pF C22 1000pF VDD C26 1000pF C27 1000pF C28 1000pF C29 1000pF C30 1000pF C31 1000pF C32 1000pF C33 1000pF C34 1000pF C73 .01uF C74 .01uF C75 .01uF C35 1000pF C36 1000pF C39 .01uF C52 .01uF C53 .01uF C40 .01uF BUFFERS C43 .01uF C44 .01uF C45 .01uF C46 .01uF C47 .01uF C48 .01uF C49 .01uF C50 .01uF C72 .01uF VDD C54 .01uF C55 .01uF C56 .01uF C57 .01uF C58 .01uF C59 .01uF C60 .01uF C61 .01uF C62 .01uF SVS 5V & 3V VDD C63 .01uF C64 .01uF C76 .01uF ispLSI_2032LV C41 .01uF C42 .01uF VDD 8 Bit Buffers NOTE: .01uF caps are NPO material & the 1000pF caps are NPO material C78 .01uF C79 .01uF C80 1000pF U21 3 VIN VOUT 2 VDD GND C51 .01uF C38 .01uF LT1086CT3.3 1 SRAM C25 1000pF + C66 10uF TANT. U22 3 VIN VOUT 2 VCC GND VDD C24 1000pF VDD C37 .01uF Freescale Semiconductor, Inc... FLASH C23 1000pF dual wire connector LT1086CT5.0 1 CPU D12 1N5400CT 3 2 1 Mouser Electronics 800-346-6873 Part No.163-5004 Title Size B 18 Date: Docum ent Number Tuesday, July 07, 1998 Rev Sheet 9 of 9 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... Appendix D MC5206EC3 BILL OF MATERIALS ITEM ASSY 1 5 PART NO. 10uF 16V 2 9 3 MFG VENDOR/ PART NO. DIG/PCE3031CT-ND DESC. .1uF VENKEL/C0805X7R500104KNE .1uF 38 .01uF VENKEL/C0805x7R500103KNE .01uF 4 22 1000pF VENKEL/C0805COG500102JNE 1000pF 5 4 10uF TANT. VENKEL/TA016TCM106KBR 10uF TANT 6 7 10 11 12 13 14 15 1 11 2 1 1 1 1 1 CM Berg Berg Berg Berg Berg Berg DIG/PCE2048CT-ND NEW/09THSMG-T400 DIG/S1011-03-ND DIG/S1011-13-ND DIG/S2011-13-ND DIG/S2011-30-ND DIG/S2011-20-ND DIG/S2011-13-ND 16 4 200 uF 90T HSMG-T400 1X3 ispHeader 1x 8 2 x 13 Header Header 30 x 2 Header 20 x 2 BDM connector 13 x 2 767054-1 AMP TIME/767054-1 17 1 BLM31A700SPT NEWARK/BLM31A700SPT 18 2 748875-1 Murata Erie AMP 200 uF LED, GRN 1X3 ispHeader 2 X 13 header Header 30 x 2 Header 20 x 2 BDM connector Mictor 767054-1 Ferrite_Bead 19 1 2SV-02 Augut NEWARK/46F897 20 1 RAPC722 SWC NEWARK/93F7715 21 12 270 VENKEL/CR0805-10W-271JT 22 21 4.75K VENKEL/CR0805-10W4751FT 4.75K 23 7 22 ohm VENKEL/CF1206-8W-220JT 24 25 26 27 1 1 2 3 10K 22 50 805 5% .1W 0 X 4.7K VENKEL/CR0805-10W-103JT VENKEL/CR0805-10W-220JT VENKEL/CR0805-10W-470JT DIG/4310R-1-472-ND 28 1 Hard Reset KS11R23CQD 220 ohm 1206 10K 22 50 RPAK, 4.7K, 10-pin 9RES Hard ResetKS11R23CQ D C&K NEWARK/66F1579 ARROW/KS11R23CQD 19 For More Information On This Product, Go to: www.freescale.com 10uF Conn, 9, D, Female, RA Conn, 2-pin pwr Power conn 3-pin 270 REF. DES. C1 - C4; C15 C5 - C9; C12, C13, C67, C70 C11, C14, C16, C37C64; C72 C76; C78,C79 C17 C36; C77, C80 C65, C66, C68, C69 C71 D1 - D11 JP1, JP2 J1 J2 J3 J4 J5 LA1 - LA4 L1 P1, P2 P3 P4 R1-R8; R13, R15, R16, R35 R9 - R11; R14, R17 - R20; R22, R24 - R30; R32 R34; R38, R41 R42 - R48 R23 R31 R36, R37 SIP1-SIP3 S1 Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. 29 1 IRQ7 KS11R22CQD 30 1 31 1 Chip-Select 0 1 x 1 CONN MC145407DW Motorola NEWARK/MC145407DW 32 1 MC145406DW Motorola NEW/08T MC145406DW 33 34 1 1 Motorola PLET 36 1 Motorola BRAD OMNIPRO/P1100-HC-53 125 MHz NEW/83F4287 37 1 MCF5206EFT P1100-HCV 54 MHz MC74LCX16245D T 822019-4 AMP MOUSER/571-8220194 38 1 Lattice INSIGHT ELECTRONICS 39 2 TI LINTECH/TLC7733ID 40 1 TI LINTECH/TLC7705ID 41 2 AMD 42 1 Motorola ARROW/AM29LV004T100EC BRAD/NO POP 43 44 1 1 Davicom Atmel DAVICOM/DM9008F/B BRAD/NO POP 45 1 PLET 46 47 48 49 50 1 1 1 1 2 ispLSI2032LV100LJ ispLSI2032LV110LJ ispLSI2032V110LJ ispLSI2032V100LJ TL7733ID or TL7733IP TL7705ID or TI7705IP AM29LV004T100EI MCM69F737TQ1 1 DM9008F AT93C46-10SC2.7 P1100-HVC 20 MHz FD22-101G 555153-1 LT1086CT3.3 LT1086CT5.0 IC197-4004-2000 YAM OMNIPRO/P1100-HC2000MHz ERIC/FD22-101G MOUSER/571-5551641 DIG/LT1086CM-3.3-ND DIG/LT1086CT-5-ND ERIC/IC197-4004-2000 51 52 1 1 1N5400 822275-1 AMP DIG/1N5400CT-ND DIG/A2142-ND 53 1 54 1 1MX32 3.3V EDO 60ns .001UF 805 57 1 58 3 59 1 60 61 1 1 62 5 2 PIN CONNECTOR, 1X2 SHORT JUMPER UNPLATED PAN PACIFIC SERIAL CABLE 4-40 HEX NUTS 4-40 X 1/4 SCREWS TAPERED SQ. WHITE PAD C&K ARROW/KS11R22CQD DIG/S1011-01-ND Halo EL AMP SMART MOD. BRAD/SM532013091X656 VENDEL/C0805-COG500102JNE DIG/S1011-02-ND DIG/929950-00-ND PAN PACIFIC DIG DIG S-9MF-6 DIG/H216-ND DIG/H142-ND DIG DIG/SJ5518-9-ND 20 For More Information On This Product, Go to: www.freescale.com IRQ7 KS11R23CQ D Chip Select 0 MC145407D W MC145406D W MCF5206EFT XTAL, 54 MHz MC72LCS162 45DT SKT, SIMM, 72-pin ispLSI2032LV -100LJ ispLSI2032LV -110LJ ispLSI2032V110LJ ispLSI2032V100LJ TL7733ID OR TL7733IP TL7705ID or TI7705IP AM29LV004T100EI MCM69F737T Q11 DM9008F AT93C4610SC-2.7 XTAL, 20MHz FD22-101 RJ 45 8P LT1086CM3.3 LT1086CT5.0 SKT, TSOP44 IN5400 SKT, PLCC44 SIMM S2 TP1 U3 U2 U1 U4 U6 XU7 U10 U11, U25 U12 U13, U15 U14 U16 U17 U18 U19 P5 U21 U22 XU13, XU15 D12 XU10 U7 C77 JP3