LP3943 RGB/White/Blue 16-LED Fun Light Driver General Description Features LP3943 is an integrated device capable of independently driving 16 LEDs. This device also contains an internal precision oscillator that provides all the necessary timing required for driving each LED. Two prescaler registers along with two PWM registers provide a versatile duty cycle control. The LP3943 contains the ability to dim LEDs in SMBUS/ I2C applications where it is required to cut down on bus traffic. n n n n Traditionally, to dim LEDs using a serial shift register such as 74LS594/5 would require a large amount of traffic to be on the serial bus. LP3943 instead requires only the setup of the frequency and duty cycle for each output pin. From then on, only a single command from the host is required to turn each individual open drain output ON, OFF, or to cycle a programmed frequency and duty cycle. Maximum output sink current is 25 mA per pin and 200 mA per package. Any ports not used for controlling the LEDs can be used for general purpose input/output expansion. Internal power-on reset Active low reset Internal precision oscillator Variable dim rates (from 6.25 ms to 1.6s; 160 Hz–0.625 Hz) Key Specifications n 16 LED driver (multiple programmable states — on, off, input, and dimming at a specified rate) n 16 Open drain outputs capable of driving up to 25 mA per LED Applications n n n n n n Customized flashing LED lights for cellular phones Portable Applications Digital Cameras Indicator Lamps General purpose I/O expander Toys Typical Application Circuit 20079601 © 2003 National Semiconductor Corporation DS200796 www.national.com LP3943 RGB/White/Blue 16-LED Fun Light Driver November 2003 LP3943 LP3943 Pin Out 20079602 (Top View) See NS Package Number SQA24C LP3943 Pin Description Pin # Name Description 1 LED0 Output of LED0 Driver 2 LED1 Output of LED1 Driver 3 LED2 Output of LED2 Driver 4 LED3 Output of LED3 Driver 5 LED4 Output of LED4 Driver 6 LED5 Output of LED5 Driver 7 LED6 Output of LED6 Driver 8 LED7 Output of LED7 Driver 9 GND Ground 10 LED8 Output of LED8 Driver 11 LED9 Output of LED9 Driver 12 LED10 Output of LED10 Driver 13 LED11 Output of LED11 Driver 14 LED12 Output of LED12 Driver 15 LED13 Output of LED13 Driver 16 LED14 Output of LED14 Driver 17 LED15 Output of LED15 Driver 18 RST Active Low Reset Input 19 SCL Clock Line for I2C Interface 20 SDA Serial Data Line for I2C Interface 21 VDD Power Supply 22 A0 Address Input 0 23 A1 Address Input 1 24 A2 Address Input 2 Ordering Information LP3943, Supplied as 1000 Units, Tape and LP3943, Supplied as 4500 Units, Tape Reel and Reel Package Marking LP3943ISQ LP3943 www.national.com LP3943ISQX 2 LP3943 Architectural Block Diagram 20079603 For Explanation of LP3943 Operation, Please Refer to “Theory of Operation” in Application Notes. 3 www.national.com LP3943 Absolute Maximum Ratings ESD (Note 4) (Notes 2, 1) Human Body Model 2 kV If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Machine Model 200V Charge Device Model 1 kV Operating Ratings (Notes 1, 2) −0.5V to 6V VDD 6V A0, A1, A2, SCL, SDA, RST (Collectively called digital pins) Voltage on LED pins 150˚C Storage Temperature −65˚C to 150˚C 2.3V to 5.5V Junction Temperature VSS−0.5V to 6V Junction Temperature Power Dissipation (Note 3) VDD −40˚C to +125˚C Operating Ambient Temperature −40˚C to +85˚C Thermal Resistance (θJA) LLP24 (Note 3) 400 mW 37˚C/W Electrical Characteristics Unless otherwise noted, VDD = 5.5V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40˚C to +125˚C. (Note 5) Symbol Parameter Conditions Typical Limit Min Units Max POWER SUPPLY VDD Supply Voltage IQ Supply Current 5 2.3 5.5 No Load 350 550 Standby 2.0 5 ∆IQ Additional Standby Current VPOR Power-On Reset Voltage 1.8 tw Reset Pulse Width 10 VDD = 5.5V, every LED pin at 4.3V 2 1.96 V µA mA V ns LED VIL LOW Level Input Voltage −0.5 0.8 V VIH HIGH Level Input Voltage 2.0 5.5 V IOL Low Level Output Current (Note 6) VOL = 0.4V, VDD = 2.3V 9 VOL = 0.4V, VDD = 3.0V 12 VOL = 0.4V, VDD = 5.0V 15 VOL = 0.7V, VDD = 2.3V 15 VOL = 0.7V, VDD = 3.0V 20 VOL = 0.7V, VDD = 5.0V 25 −1 ILEAK Input Leakage Current VDD = 3.6, VIN = 0V or VDD CI/O Input/Output Capacitance (Note 7) 2.6 mA 1 µA 5 pF ALL DIGITAL PINS (EXCEPT SCL AND SDA PINS) VIL LOW Level Input Voltage −0.5 0.8 V VIH HIGH Level Input Voltage 2.0 5.5 V ILEAK Input Leakage Current CIN Input Capacitance −1 VIN = 0V (Note 7) 2.3 1 µA 5 pF V I2C INTERFACE (SCL AND SDA PINS) VIL LOW Level Input Voltage -0.5 0.3VDD VIH HIGH Level Input Voltage 0.7VDD 5.5 V VOL LOW Level Output Voltage 0 0.2VDD V IOL LOW Level Output Current VOL = 0.4V FCLK Clock Frequency (Note 7) tHOLD Hold Time Repeated START Condition (Note 7) tCLK-LP CLK Low Period (Note 7) www.national.com 6.5 3 mA 400 4 kHz 0.6 µs 1.3 µs (Continued) Unless otherwise noted, VDD = 5.5V. Typical values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TJ = −40˚C to +125˚C. (Note 5) Symbol Parameter Conditions Typical Limit Min Max Units I2C INTERFACE (SCL AND SDA PINS) tCLK-HP CLK High Period (Note 7) tSU Set-Up Time Repeated START Condition (Note 7) 0.6 µs 0.6 µs tDATA-HOLD Data Hold Time (Note 7) 300 ns tDATA-SU Data Set-Up Time (Note 7) 100 ns tSU Set-Up Time for STOP Condition (Note 7) 0.6 µs tTRANS Maximum Pulse Width of Spikes that Must Be Suppressed by the Input Filter of Both DATA & CLK Signals (Note 7) 50 ns Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The part cannot dissipate more than 400mW. Note 4: The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is 0Ω in series with 100 pF. Note 5: Limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25˚C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 6: Each LED pin should not exceed 25 mA and each octal (LED0–LED7; LED8–LED15) should not exceed 100 mA. The package should not exceed a total of 200 mA. Note 7: Guaranteed by design. Typical Performance Characteristics Frequency vs. Temp (TA = −40˚C to +85˚C), VDD = 2.3V to 3.0V 20079617 5 www.national.com LP3943 Electrical Characteristics LP3943 Application Notes pins not used to drive LED can be used for General Purpose Parallel Input/Output (GPIO) expansion. THEORY OF OPERATION The LP3943 is equipped with Power-On Reset that holds the chip in a reset state until VDD reaches VPOR during power up. Once VPOR is achieved, the LP3943 comes out of reset and initializes itself to the default state. The LP3943 takes incoming data from the baseband controller and feeds them into several registers that control the frequency and the duty cycle of the LEDs. Two prescaler registers and two PWM registers provide two individual rates to dim or blink the LEDs (for more information on these registers, refer to Table 1. LP3943 REGISTER TABLE). Each LED can be programmed in one of four states — on, off, DIM0 rate or DIM1 rate. Two read-only registers provide status on all 16 LEDs. The LP3943 can be used to drive RGB LEDs and/or single-color LEDs to create a colorful, entertaining, and informative setting. Alternatively, it can also drive RGB LED as a flashlight. This is particularly suitable for accessory functions in cellular phones and toys. Any LED To bring the LP3943 into reset, hold the RST pin LOW for a period of TW. This will put the chip into its default state. The LP3943 can only be programmed after RST signal is HIGH again. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. 20079606 FIGURE 1. I2C Data Validity I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 20079607 FIGURE 2. I2C START and STOP Conditions After the START condition, a chip address is sent by the I2C master. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP3943 hardwires bits 7 to 4 and leaves bits 3 to 1 selectable, as shown in Figure 3. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The LP3943 supports only a WRITE during chip addressing. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. TRANSFERRING DATA Every byte put on the SDA line must be eight bits long with the most significant bit (MSB) being transferred first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. www.national.com 6 LP3943 Application Notes (Continued) 20079608 FIGURE 3. Chip Address Byte 20079609 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled LOW by either master or slave) rs = repeated start xx = 60 to 67 FIGURE 4. LP3943 Register Write However, if a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in Figure 5. 20079610 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled LOW by either master or slave) rs = repeated start xx = 60 to 67 FIGURE 5. LP3943 Register Read 7 www.national.com LP3943 Application Notes order. The auto increment bit is inside the register address byte, as shown in Figure 6. Auto increment is enabled when this bit is programmed to “1” and disabled when it is programmed to “0”. Bits 5, 6 and 7 in the register address byte should always be zero. (Continued) AUTO INCREMENT Auto increment is a special feature supported by the LP3943 to eliminate repeated chip and register addressing when data are to be written to or read from registers in sequential 20079611 FIGURE 6. Register Address Byte In the READ mode, when auto increment is enabled, I2C master could receive any number of bytes from LP3943 without selecting chip address and register address again. Every time the I2C master reads a register, the LP3943 will increment the register address and the next data register will be read. When I2C master reaches the last register (09H), the register address will roll over to 00H. In the WRITE mode, when auto increment is enabled, the LP3943 will increment the register address every time I2C master writes to register. When the last register (09H register) is reached, the register address will roll over to 02H, not 00H, because the first two registers in LP3943 are read-only registers. It is possible to write to the first two registers independently, and the LP3943 will acknowledge, but the data will be ignored. If auto increment is disabled, and the I2C master does not change register address, it will continue to write data into the same register. 20079612 FIGURE 7. Programming with Auto Increment Disabled (in WRITE Mode) 20079613 FIGURE 8. Programming with Auto Increment Enabled (in WRITE Mode) www.national.com 8 LP3943 Application Notes (Continued) TABLE 1. LP3943 REGISTER TABLE Address (Hex) Register Name Read/Write Register Function 0x00 Input 1 Read Only LED0–7 Input Register 0x01 Input 2 Read Only LED8–15 Input Register 0x02 PSC0 R/W Frequency Prescaler 0 0x03 PWM0 R/W PWM Register 0 0x04 PSC1 R/W Frequency Prescaler 1 0x05 PWM1 R/W PWM Register 1 0x06 LS0 R/W LED0–3 Selector 0x07 LS1 R/W LED4–7 Selector 0x08 LS2 R/W LED8–11 Selector 0x09 LS3 R/W LED12–15 Selector BINARY FOMAT FOR INPUT REGISTERS (READ ONLY) — ADDRESS 0x00 and 0x01 Address 0x00 Bit # 7 6 5 4 3 2 1 0 Default value X X X X X X X X LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0 X = don’t care Address 0x01 Bit # 7 6 5 4 3 2 1 0 Default value X X X X X X X X LED15 LED14 LED13 LED12 LED11 LED10 LED9 LED8 X = don’t care BINARY FORMAT FOR FREQUENCY PRESCALER AND PWM REGISTERS — ADDRESS 0x02 to 0x05 Address 0x02 (PSC0) Bit # 7 6 5 4 3 2 1 0 Default value 0 0 0 0 0 0 0 0 PSC0 register is used to program the period of DIM0. DIM0 = (PSC0+1)/160 The maximum period is 1.6s when PSC0 = 255. Address 0x03 (PWM0) Bit # 7 6 5 4 3 2 1 0 Default value 1 0 0 0 0 0 0 0 PWM0 register determines the duty cycle of DIM0. The LED outputs are LOW (LED on) when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If PWM0 is programmed with 0x00, LED output is always HIGH (LED off). The duty cycle of DIM0 is: PWM0/256 Default value is 50% duty cycle. Address 0x04 (PSC1) Bit # 7 6 5 4 3 2 1 0 Default value 0 0 0 0 0 0 0 0 PSC1 register is used to program the period of DIM1. DIM1 = (PSC1 + 1)/160 The maximum period is 1.6s when PSC1 = 255. 9 www.national.com LP3943 Application Notes (Continued) Address 0x05 (PWM1) Bit # 7 6 5 4 3 2 1 0 Default value 1 0 0 0 0 0 0 0 PWM1 register determines the duty cycle of DIM1. The LED outputs are LOW (LED on) when the count is less than the value in PWM1 and HIGH (LED off) when it is greater. If PWM1 is programmed with 0x00, LED output is always HIGH (LED off). The duty cycle of DIM1 is: PWM1/256 Default value is 50% duty cycle. BINARY FORMAT FOR SELECTOR REGISTERS — ADDRESS 0x06 to 0x09 Address 0x06 (LS0) Bit # 7 Default value 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 B1 B0 B1 B0 B1 B0 B1 B0 LED3 LED2 LED1 LED0 Address 0x07 (LS1) Bit # 7 6 5 4 3 2 1 Default value 0 0 0 0 0 0 0 0 B1 B0 B1 B0 B1 B0 B1 B0 LED7 LED6 LED5 0 LED4 Address 0x08 (LS2) Bit # 7 6 5 4 3 2 1 Default value 0 0 0 0 0 0 0 0 B1 B0 B1 B0 B1 B0 B1 B0 LED11 LED10 LED9 0 LED8 Address 0x09 (LS3) Bit # 7 6 5 4 3 2 1 0 Default value 0 0 0 0 0 0 0 0 B0 B1 B0 B1 B0 B1 B1 LED15 LED14 LED13 LED States With Respect To Values in "B1" and "B0" www.national.com B1 B0 Function 0 0 Output Hi-Z (LED off) 0 1 Output LOW (LED on) 1 0 Output dims (DIM0 rate) 1 1 Output dims (DIM1 rate) 10 B0 LED12 LP3943 Application Notes (Continued) Programming Example: Dim LEDs 0 to 7 at 1 Hz at 25% duty cycle Dim LEDs 8 to 12 at 5 Hz at 50% duty cycle Set LEDs 13, 14 and 15 off Step 1: Set PSC0 to achieve DIM0 of 1s Step 2: Set PWM0 duty cycle to 25% Step 3: Set PSC1 to achieve DIM1 of 0.2s Step 4: Set PWM1 duty cycle to 50% Step 5: Set LEDs 13, 14 and 15 off by loading the data into LS3 register Step 6: Set LEDs 0 to 7 to point to DIM0 Step 7: Set LEDs 8 to 12 to point to DIM1 Register Name Set to (Hex) 1 Step Set DIM0 = 1s 1 = (PSC0 + 1)/160 PSC0 = 159 Description PSC0 0x09F 2 Set duty cycle to 25% Duty Cycle = PWM0/256 PWM0 = 64 PWM0 0x40 3 Set DIM1 = 0.2s 0.2 = (PSC1 + 1)/160 PSC1 = 31 PSC1 0x1F 4 Set duty cycle to 50% Duty Cycle = PWM1/256 PWM1 = 128 PWM1 0x80 5 LEDs 13, 14 and 15 off Output = HIGH LS3 0x03 6 LEDs 0 to 7 Output = DIM0 LS0, LS1 LS0 = 0xAA LS1 = 0xAA 7 LEDs 8 to 12 Output = DIM1 LS2, LS3 LS2 = 0xFF LS3 = 0x03 than VDD, causing extra supply current (∆IQ). To minimize this current, consider keeping the LED pins at a voltage equal to or greater than VDD. REDUCING IQ WHEN LEDS ARE OFF In many applications, the LEDs and the LP3943 share the same VDD, as shown in Section Typical Application Circuit. When the LEDs are off, the LED pins are at a lower potential 20079614 FIGURE 9. Methods to Reduce IQ When LEDs Are Off 11 www.national.com LP3943 Application Notes (Continued) LP3943 With 5V Booster 20079615 Pub Lcl genlevel=LP3943 Driving RGB LED As A Flash 20079616 www.national.com 12 inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED 1. FOR LEAD FINISH THICKNESS AND COMPOSITION. SEE “SOLDER INFORMATION” IN THE PACKAGING SECTION OF THE NATIONAL SEMICONDUCTOR WEB PAGE (www. national.com). 2. NO JEDEC REGISTRATION AS OF MARCH 2003. Order Number LP3943ISQ or LP3943ISQX NS Package Number SQA24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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