ST1S10
3 A, 900 kHz, monolithic synchronous
step-down regulator
Features
■
Step-down current mode PWM regulator
■
Output voltage adjustable from 0.8 V
■
Input voltage from 2.5 V up to 18 V
■
2% DC output voltage tolerance
■
Synchronous rectification
■
Inhibit function
■
Synchronizable switching frequency from 400
kHz up to 1.2 MHz
■
Internal soft start
■
Dynamic short circuit protection
■
Typical efficiency: 90%
■
3 A output current capability
■
Stand-by supply current: max 6 µA over
temperature range
■
Operative junction temp: from -25°C to 125°C
DFN8 (4x4mm)
Description
Applications
■
Consumer
– STB, DVD, DVD recorders, TV, VCR, car
audio, LCD monitors
■
Networking
– XDSL, modems, DC-DC modules
■
Computer
– Optical storage, HD drivers, printers,
audio/graphic cards
■
Industrial and security
– Battery chargers, DC-DC converters, PLD,
PLA, FPGA, LED drivers
Table 1.
PowerSO-8
The ST1S10 is a high efficiency step-down PWM
current mode switching regulator capable of
providing up to 3 A of output current. The device
operates with an input supply range from 2.5 V to
18 V and provides an adjustable output voltage
from 0.8 V (VFB) to 0.85*VIN_SW [VOUT =
VFB*(1+R1/R2)]. It operates either at a 900 kHz
fixed frequency or can be synchronized to an
external clock (from 400 kHz to 1.2 MHz). The
high switching frequency allows the use of tiny
SMD external components, while the integrated
synchronous rectifier eliminates the need for a
Schottky diode. The ST1S10 provides excellent
transient response, and is fully protected against
thermal overheating, switching over-current and
output short circuit.
The ST1S10 is the ideal choice for point-of-load
regulators or LDO pre-regulation.
Device summary
Package
Part number
ST1S10
October 2007
DFN8 (4x4 mm)
PowerSO-8
ST1S10PUR
ST1S10PHR
Rev. 3
1/26
www.st.com
26
Contents
ST1S10
Contents
1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2.1
6
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3
Output capacitor (VOUT > 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4
Output capacitor (0.8 V < VOUT < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.5
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.6
Inductor (VOUT > 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.7
Inductor (0.8 V < VOUT < 2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.8
Function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.8.1
Sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.8.2
Inhibit function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.8.3
OCP (over-current protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.8.4
SCP (short circuit protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.8.5
SCP and OCP operation with high capacitive load . . . . . . . . . . . . . . . . 12
Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
ST1S10
Application circuit
1
Application circuit
Figure 1.
Typical application circuit
L1
3.3µH
12V
5V – 3A
VIN_SW
SW
C1
4.7µF
EN
ST1S10
R1
VIN_A
C2
22µF
FB
C3
R2
0.1µF
SYNC
AGND
PGND
3/26
Pin configuration
ST1S10
2
Pin configuration
Figure 2.
Pin connections (top view for PowerSO-8, bottom view for DFN8)
DFN8 (4x4)
Table 2.
PowerSO-8
Pin description
Pin n°
Symbol
1
VIN_A
2
INH (EN)
3
VFB
4
AGND
Analog ground
5
SYNC
Synchronization and frequency select. Connect SYNC to GND for 900 kHz
operation, or to an external clock from 400 kHz to 1.2 MHz. (see Sync
operation paragraph 5.8.1)
6
VIN_SW
Power input supply voltage to be tied to VIN power supply source
7
SW
8
PGND
epad
epad
4/26
Name and function
Analog input supply voltage to be tied to VIN supply source
Inhibit pin active low. Connect to VIN_A if not used
Feedback voltage for connection to external voltage divider to set the VOUT
from 0.8V up to 0.85*VIN_SW. (see output voltage selection paragraph 5.5)
Switching node to be connected to the inductor
Power ground
Exposed pad to be connected to ground
ST1S10
Maximum ratings
3
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Value
Unit
Positive power supply voltage
-0.3 to 20
V
VIN_A
Positive supply voltage
-0.3 to 20
V
VINH
Inhibit voltage
-0.3 to VIN_A
V
VSW
Output switch voltage
-0.3 to 20
V
VFB
Feedback voltage
-0.3 to 2.5
V
IFB
FB current
-1 to +1
mA
Sync
Synchronization
-0.3 to 6
V
TSTG
Storage temperature range
-40 to 150
°C
TOP
Operating junction temperature range
-25 to 125
°C
VIN_SW
Parameter
Note:
Absolute maximum ratings are the values beyond which damage to the device may occur.
Functional operation under these conditions is not implied.
Table 4.
Thermal data
Symbol
Parameter
PowerSO-8
DFN8
Unit
RthJA
Thermal resistance junction-ambient
40
40
°C/W
RthJC
Thermal resistance junction-case
12
4
°C/W
5/26
Electrical characteristics
ST1S10
4
Electrical characteristics
Table 5.
Electrical characteristics
VIN = VIN_SW = VIN_A = VINH = 12 V, VSYNC = GND, VOUT = 5 V, IOUT = 10 mA, CIN = 4.7 µF
+0.1 µF, COUT = 22 µF, L1 = 3.3 µH, TJ = -25 to 125°C (Unless otherwise specified, refer to
the typical application circuit. Typical values assume TJ = 25°C)
Symbol
Parameter
VFB
Feedback voltage
IFB
VFB pin bias current
IQ
Quiescent current
IOUT
Output current (1)
VINH
Inhibit threshold
IINH
Inhibit pin current
Test conditions
Min.
Typ.
Max.
Unit
TJ = 25°C
784
800
816
mV
TJ = -25°C to 125°C
776
800
824
mV
600
nA
1.5
2.5
mA
2
6
µA
VINH > 1.2 V, not switching
VINH < 0.4 V
VIN = 2.5 V to 18 V
VOUT = 0.8 V to 13.6 V (2)
3.0
A
Device ON
1.2
V
Device OFF
%VOUT/ΔVIN Reference line regulation
V
2
µA
2.5 V < VIN < 18 V
0.4
%VOUT/
ΔVIN
0.5
%VOUT/
ΔIOUT
%VOUT/
ΔIOUT
Reference load regulation
10 mA < IOUT < 3 A
PWM fs
PWM switching frequency
VFB = 0.7 V, Sync = GND
TJ = 25°C
DMAX
0.4
Maximum duty cycle (2)
0.7
0.9
1.1
MHz
85
90
%
RDSon-N
NMOS switch on resistance
ISW = 750 mA
0.10
Ω
RDSon-P
PMOS switch on resistance
ISW = 750 mA
0.12
Ω
5.0
A
IOUT = 100 mA to 300 mA
85
%
IOUT = 300 mA to 3 A
90
%
Thermal shut down
150
°C
Thermal shut down hysteresis
15
°C
ISWL
ν
TSHDN
THYS
Switch current limitation
Efficiency
VOUT/ΔIOUT Output transient response
100 mA < IOUT < 1 A,
tR = tF ≥ 500 ns
±5
%VO
VOUT/ΔIOUT Short circuit removal response
@IO=short (overshot)
10 mA < IOUT < short
±10
%VO
SYNC frequency capture range
VIN = 2.5 V to 18 V,
VSYNC = 0 to 5 V
0.4
SYNCWD
SYNC pulse width
VIN = 2.5 V to 18 V
250
VIL_SYNC
SYNC input threshold low
VIN = 2.5 V to 18 V
VIH_SYNC
SYNC input threshold high
VIN = 2.5 V to 18 V
FSYNC
6/26
1.2
ns
0.4
1.6
MHz
V
V
ST1S10
Electrical characteristics
Table 5.
Electrical characteristics (continued)
VIN = VIN_SW = VIN_A = VINH = 12 V, VSYNC = GND, VOUT = 5 V, IOUT = 10 mA, CIN = 4.7 µF
+0.1 µF, COUT = 22 µF, L1 = 3.3 µH, TJ = -25 to 125°C (Unless otherwise specified, refer to
the typical application circuit. Typical values assume TJ = 25°C)
Symbol
Parameter
IIL, IIH
SYNC input current
UVLO
Under voltage lock-out threshold
Test conditions
VIN = 2.5 V to 18 V,
VSYNC = 0 or 5 V
Min.
Typ.
-10
Max.
Unit
+10
µA
VIN rising
2.3
V
Hysteresis
200
mV
1. Guaranteed by design, but not tested in production.
2. See output voltage selection paragraph 5.5 for maximum duty cycle conditions.
7/26
Application information
ST1S10
5
Application information
5.1
Description
The ST1S10 is a high efficiency synchronous step-down DC-DC converter with inhibit
function. It provides up to 3 A over an input voltage range of 2.5 V to 18 V, and the output
voltage can be adjusted from 0.8 V up to 85% of the input voltage level. The synchronous
rectification removes the need for an external Schottky diode and allows higher efficiency
even at very low output voltages.
A high internal switching frequency (0.9 MHz) allows the use of tiny surface-mount
components, as well as a resistor divider to set the output voltage value. In typical
application conditions, only an inductor and 3 capacitors are required for proper operation.
The device can operate in PWM mode with a fixed frequency or synchronized to an external
frequency through the SYNC pin. The current mode PWM architecture and stable operation
with low ESR SMD ceramic capacitors results in low, predictable output ripple. No external
compensation is needed.
To maximize power conversion efficiency, the ST1S10 works in pulse skipping mode at light
load conditions and automatically switches to PWM mode when the output current
increases.
The ST1S10 is equipped with thermal shut down protection activated at 150°C (typ.).
Cycle-by-cycle short circuit protection provides protection against shorted outputs for the
application and the regulator. An internal soft start for start-up current limiting and power ON
delay of 275 µs (typ.) helps to reduce inrush current during start-up.
5.2
External components selection
5.2.1
Input capacitor
The ST1S10 features two VIN pins: VIN_SW for the power supply input voltage where the
switching peak current is drawn, and VIN_A to supply the ST1S10 internal circuitry and
drivers.
The VIN_SW input capacitor reduces the current peaks drawn from the input power supply
and reduces switching noise in the IC. A high power supply source impedance requires
larger input capacitance.
For the VIN_SW input capacitor the RMS current rating is a critical parameter that must be
higher than the RMS input current. The maximum RMS input current can be calculated
using the following equation:
2⋅ D + D
I RMS = I O ⋅ D η
η
2
2
where η is the expected system efficiency, D is the duty cycle and IO is the output DC
current. The duty cycle can be derived using the equation:
D = (VOUT + VF) / (VIN-VSW)
where VF is the voltage drop across the internal NMOS, and VSW represents the voltage
drop across the internal PDMOS. The minimum duty cycle (at VIN_max) and the maximum
8/26
ST1S10
Application information
duty cycle (at VIN_min) should be considered in order to determine the max IRMS flowing
through the input capacitor.
A minimum value of 4.7 µF for the VIN_SW and a 0.1 µF ceramic capacitor for the VIN_A are
suitable in most application conditions. A 10 µF or higher ceramic capacitor for the VIN_SW
and a 1 µF or higher for the VIN_A are recommended in cases of higher power supply source
impedance or where long wires are needed between the power supply source and the VIN
pins. The above higher input capacitor values are also recommended in cases where an
output capacitive load is present (47 µF < CLOAD < 100 µF), which could impact the
switching peak current drawn from the input capacitor during the start-up transient.
In cases of very high output capacitive loads (CLOAD > 100 µF), all input/output capacitor
values shall be modified as described in the OCP and SCP operation section 5.8.5 of this
document.
The input ceramic capacitors should have a voltage rating in the range of 1.5 times the
maximum input voltage and be located as close as possible to VIN pins.
5.3
Output capacitor (VOUT > 2.5 V)
The most important parameters for the output capacitor are the capacitance, the ESR and
the voltage rating. The capacitance and the ESR affect the control loop stability, the output
ripple voltage and transient response of the regulator.
The ripple due to the capacitance can be calculated with the following formula:
VRIPPLE(C) = (0.125 x ΔISW) / (FS x COUT)
where FS is the PWM switching frequency and ΔISW is the inductor peak-to-peak switching
current, which can be calculated as:
ΔISW = [(VIN - VOUT) / (FS x L)] x D
where D is the duty cycle.
The ripple due to the ESR is given by:
VRIPPLE(ESR) = ΔISW x ESR
The equations above can be used to define the capacitor selection range, but final values
should be verified by testing an evaluation circuit.
Lower ESR ceramic capacitors are usually recommended to reduce the output ripple
voltage. Capacitors with higher voltage ratings have lower ESR values, resulting in lower
output ripple voltage.
Also, the capacitor ESL value impacts the output ripple voltage, but ceramic capacitors
usually have very low ESL, making ripple voltages due to the ESL negligible. In order to
reduce ripple voltages due to the parasitic inductive effect, the output capacitor connection
paths should be kept as short as possible.
The ST1S10 has been designed to perform best with ceramic capacitors. Under typical
application conditions a minimum ceramic capacitor value of 22 µF is recommended on the
output, but higher values are suitable considering that the control loop has been designed to
work properly with a natural output LC frequency provided by a 3.3 µH inductor and 22 µF
output capacitor. If the high capacitive load application circuit shown in Figure 3 is used, a
47 µF (or 2 x 22 µF capacitors in parallel) could be needed as described in the OCP and
SCP operation section 5.8.5. of this document.
9/26
Application information
ST1S10
The use of ceramic capacitors with voltage ratings in the range of 1.5 times the maximum
output voltage is recommended.
5.4
Output capacitor (0.8 V < VOUT < 2.5 V)
For applications with lower output voltage levels (Vout < 2.5 V) the output capacitance and
inductor values should be selected in a way that improves the DC-DC control loop behavior.
In this output condition two cases must be considered: VIN > 8 V and VIN < 8 V.
For VIN < 8 V the use of 2 x 22 µF capacitors in parallel to the output is recommended, as
shown in Figure 4.
For VIN > 8 V, a 100 µF electrolytic capacitor with ESR < 0.1 Ω should be added in parallel to
the 2 x 22 µF output capacitors as shown in Figure 5.
5.5
Output voltage selection
The output voltage can be adjusted from 0.8 V up to 85% of the input voltage level by
connecting a resistor divider (see R1 and R2 in the typical application circuit) between the
output and the VFB pin. A resistor divider with R2 in the range of 20 kΩ is a suitable
compromise in terms of current consumption. Once the R2 value is selected, R1 can be
calculated using the following equation:
R1 = R2 x (VOUT - VFB) / VFB
where VFB = 0.8 V (typ.).
Lower values are suitable as well, but will increase current consumption. Be aware that duty
cycle must be kept below 85% at all application conditions, so that:
D = (VOUT + VF) / (VIN-VSW) < 0.85
where VF is the voltage drop across the internal NMOS, and VSW represents the voltage
drop across the internal PDMOS.
Note that once the output current is fixed, higher VOUT levels increase the power dissipation
of the device leading to an increase in the operating junction temperature. It is
recommended to select a VOUT level which maintains the junction temperature below the
thermal shut-down protection threshold (150°C typ.) at the rated output current. The
following equation can be used to calculate the junction temperature (TJ):
TJ = {[VOUT x IOUT x RthJA x (1-η)] / η } +TAMB
where RthJA is the junction-to-ambient thermal resistance, η is the efficiency at the rated
IOUT current and TAMB is the ambient temperature.
To ensure safe operating conditions the application should be designed to keep TJ < 140°C.
5.6
Inductor (VOUT > 2.5 V)
The inductor value fixes the ripple current flowing through output capacitor and switching
peak current. The ripple current should be kept in the range of 20-40% of IOUT_MAX (for
example it is 0.6 - 1.2 A at IOUT = 3 A). The approximate inductor value can be obtained with
the following formula:
L = [(VIN - VOUT) / ΔISW] x TON
10/26
ST1S10
Application information
where TON is the ON time of the internal switch, given by:
TON = D/FS
The inductor should be selected with saturation current (ISAT) equal to or higher than the
inductor peak current, which can be calculated with the following equation:
IPK = IO + (ΔISW/2), ISAT ≥ IPK
The inductor peak current must be designed so that it does not exceed the switching current
limit.
5.7
Inductor (0.8 V < VOUT < 2.5 V)
For applications with lower output voltage levels (Vout < 2.5 V) the description in the previous
section is still valid but it is recommended to keep the inductor values in a range from 1µH to
2.2 µH in order to improve the DC-DC control loop behavior, and increase the output
capacitance depending on the VIN level as shown in the Figure 4 and Figure 5. In most
application conditions a 2.2 µH inductor is the best compromise between DC-DC control
loop behavior and output voltage ripple.
5.8
Function operation
5.8.1
Sync operation
The ST1S10 operates at a fixed frequency or can be synchronized to an external frequency
with the SYNC pin. The ST1S10 switches at a frequency of 900 kHz when the SYNC pin is
connected to ground, and can synchronize the switching frequency between 400 kHz to 1.2
MHz from an external clock applied to the SYNC pin. When the SYNC feature is not used,
this pin must be connected to ground with a path as short as possible to avoid any possible
noise injected in the SYNC internal circuitry.
5.8.2
Inhibit function
The inhibit pin can be used to turn OFF the regulator when pulled down, thus drastically
reducing the current consumption down to less than 6 µA. When the inhibit feature is not
used, this pin must be tied to VIN to keep the regulator output ON at all times. To ensure
proper operation, the signal source used to drive the inhibit pin must be able to swing above
and below the specified thresholds listed in the electrical characteristics section under VINH.
Any slew rate can be used to drive the inhibit pin.
5.8.3
OCP (over-current protection)
The ST1S10 DC-DC converter is equipped with a switch over-current protection. In order to
provide protection for the application and the internal power switches and bonding wires, the
device goes into a shutdown state if the switch current limit is reached and is kept in this
condition for the TOFF period (TOFF(OCP) = 135 µs typ.) and turns on again for the TON period
(TON(OCP) = 22 µs typ.) under typical application conditions. This operation is repeated cycle
by cycle. Normal operation is resumed when no over-current is detected.
11/26
Application information
5.8.4
ST1S10
SCP (short circuit protection)
In order to protect the entire application and reduce the total power dissipation during an
overload or an output short circuit condition, the device is equipped with dynamic short
circuit protection which works by internally monitoring the VFB (feedback voltage).
In the event of an overload or output short circuit, if the VOUT voltage is reduced causing the
feedback voltage (VFB) to drop below 0.3 V (typ.), the device goes into shutdown for the
TOFF time (TOFF(SCP) = 288 µs typ.) and turns on again for the TON period (TON(SCP) = 130
µs typ.). This operation is repeated cycle by cycle, and normal operation is resumed when
no overload is detected (VFB > 0.3 V typ.) for the full TON period.
This dynamic operation can greatly reduce the power dissipation in overload conditions,
while still ensuring excellent power-on startup in most conditions.
5.8.5
SCP and OCP operation with high capacitive load
Thanks to the OCP and SCP circuit, ST1S10 is strongly protected against damage from
short circuit and overload.
However, a highly capacitive load on the output may cause difficulties during start-up. This
can be resolved by using the modified application circuit shown in Figure 3, in which a
minimum of 10 µF for C1 and a 4.7 µF ceramic capacitor for C3 are used. Moreover, for
CLOAD > 100 µF, it is necessary to add the C4 capacitor in parallel to the upper voltage
divider resistor (R1) as shown in Figure 3. The recommended value for C4 is 4.7 nF.
Note that C4 may impact the control loop response and should be added only when a
capacitive load higher than 100 µF is continuously present. If the high capacitive load is
variable or not present at all times, in addition to C4 an increase in the output ceramic
capacitor C2 from 22 µF to 47 µF (or 2 x 22 µF capacitors in parallel) is recommended. Also
in this case it is suggested to further increase the input capacitors to a minimum of 10 µF for
C1 and a 4.7 µF ceramic capacitor for C3 as shown in Figure 3.
Figure 3.
Application schematic for heavy capacitive load
L1
3.3µH
12V
C4 (*)
4.7nF
VIN_SW
5V – 3A
SW
C1
10µF
EN
ST1S10
R1
VIN_A
C2(*)
R2
4.7µF
SYNC
AGND
PGND
(*) see OCP and SCP descriptions for C2 and C4 selection
12/26
22µF
FB
C3
LOAD
CLOAD
Output Load
ST1S10
Figure 4.
Application information
Application schematic for low output voltage (VOUT < 2.5 V) and 2.5 V < VIN < 8 V
L1
2.2µH
VIN<8V
0.8V<VOUT<2.5V
VIN_SW
SW
C1
10µF
EN
ST1S10
R1
VIN_A
C2
2x22µF
FB
C3
R2
0.1µF
SYNC
Figure 5.
AGND
PGND
Application schematic for low output voltage (VOUT < 2.5 V) and 8 V < VIN < 16 V
L1
2.2µH
8V<VIN<16V
0.8V<VOUT<2.5V
VIN_SW
SW
C1
10µF
EN
ST1S10
+
R1
VIN_A
C2
2x22µF
FB
C3
R2
4.7µF
SYNC
AGND
C5
100µF
Electrolytic
ESR<0.1Ohm
PGND
13/26
Layout considerations
6
ST1S10
Layout considerations
Layout is an important step in design for all switching power supplies.
High-speed operation (900 kHz) of the ST1S10 device demands careful attention to PCB
layout. Care must be taken in board layout to get device performance, otherwise the
regulator could show poor line and load regulation, stability issues as well as EMI problems.
It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths.
The input capacitor must be placed as close as possible to the IC pins as well as the
inductor and output capacitor. Use a common ground node for power ground and a different
one for control ground (AGND) to minimize the effects of ground noise. Connect these
ground nodes together underneath the device and make sure that small signal components
returning to the AGND pin and do not share the high current path of CIN and COUT.
The feedback voltage sense line (VFB) should be connected right to the output capacitor and
routed away from noisy components and traces (e.g., SW line). Its trace should be
minimized and shielded by a guard-ring connected to the ground.
Figure 6.
PCB layout suggestion
CN1=Input power supply
CN2=Enable/Disable
CN3=Input sync.
CN4=VOUT
VFB guard-ring
39mm
Input capacitor C1 must be placed
as close as possible to the IC
pins as well as the inductor L1
and output capacitor C2
Vias from thermal pad
to bottom layer
47mm
14/26
ST1S10
Figure 7.
Layout considerations
PCB layout suggestion
IOUT
Common ground node
for power ground
Power Ground
IIN
6.1
Thermal considerations
The leadframe die pad, of ST1S10, is exposed at the bottom of the package and must be
soldered directly to a properly designed thermal pad on the PCB, the addition of thermal
vias from the thermal pad to an internal ground plane will help increase power dissipation.
15/26
Diagram
ST1S10
7
Diagram
Figure 8.
Block diagram
16/26
ST1S10
8
Typical performance characteristics
Typical performance characteristics
Figure 9.
Unless otherwise specified, refer to the typical application circuit under the following
conditions: TJ = 25°C, VIN = VIN-SW = VIN-A = VINH = 12 V, VSYNC = GND, VOUT = 5 V,
IOUT = 10 mA, CIN = 4.7 µF + 0.1 µF, COUT = 22 µF, L1 = 3.3 µH
Voltage feedback vs. temperature
Figure 10. Oscillator frequency vs.
temperature
1.2
820
1.1
Frequency [MHz]
830
VFB [mV]
810
800
790
780
VIN=VINH=12V, VOUT=0.8V, IOUT=10mA
770
-25
0
25
50
75
100
0.9
0.8
0.7
0.6
-50
760
-50
1
125
VIN-A=VIN-SW=VINH=12V, VFB=0V
-25
0
25
Figure 11. Max duty cycle vs. temperature
1
88
VINH (V)
Duty Cycle [%]
125
1.2
86
84
0.8
0.6
0.4
VIN-A=VIN-SW=VINH=12V, VFB=0V
82
VIN-A=VIN-SW=2.5V, VOUT=0.8V, IOUT=10mA
0.2
0
-25
0
25
50
75
100
-50
125
-25
Figure 13. Reference line regulation vs.
temperature
Load [%VOUT /I OUT ]
1.3
0.1
0
-0.1
VIN-A=VIN-SW=VINH from 2.5 to 20V, VOUT=0.8V, IOUT=10mA
0
25
50
75
TEMPERATURE [°C]
25
50
75
100
125
Figure 14. Reference load regulation vs.
temperature
0.2
-25
0
TEMPERATURE [°C]
TEMPERATURE [°C]
Line [%(V OUT /VIN)]
100
1.4
90
-0.2
-50
75
Figure 12. Inhibit threshold vs. temperature
92
80
-50
50
TEMPERATURE [°C]
TEMPERATURE [°C]
100
125
VIN-A=VIN-SW=VINH=12V, IOUT from 10mA to 3A
1
0.7
0.4
0.1
-0.2
-0.5
-25
0
25
50
75
100
125
TEMPERATURE [°C]
17/26
Typical performance characteristics
ST1S10
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-50
Figure 16. Shutdown mode quiescent current
vs. temperature
7
6
VIN-A=VIN-SW=12V, VINH=GND, VOUT=0.8V
5
IQ (µA)
IQ (mA)
Figure 15. ON mode quiescent current vs.
temperature
4
3
2
VIN-A=VIN-SW=12V, VINH=1.2V, VOUT=0.8V
1
0
-25
0
25
50
75
100
-50
125
-25
0
320
120
270
110
220
100
170
120
70
0
25
50
75
100
-25
90
EFFICIENCY [%]
EFFICIENCY [%]
90
80
70
60
VIN-A=VIN-SW=VINH=12V, VOUT=5V, IOUT=3A
50
75
TEMPERATURE [°C]
18/26
0
25
50
75
125
Figure 20. Efficiency vs. output current
100
25
100
VIN=12V, ISW=750mA
TEMPERATURE [°C]
100
0
125
70
50
-50
125
Figure 19. Efficiency vs. temperature
-25
100
80
TEMPERATURE [°C]
50
-50
75
90
60
VIN=12V, ISW=750mA
-25
50
Figure 18. NMOS ON resistance vs.
temperature
RDSON-N[m ]
RDSON-P[m ]
Figure 17. PMOS ON resistance vs.
temperature
20
-50
25
TEMPERATURE [°C]
TEMPERATURE [°C]
80
70
60
VIN-A=VIN-SW=VINH=12V, VOUT=5V, TJ=25°C
100
125
50
0
0.5
1
1.5
2
OUTPUT CURRENT [A]
2.5
3
ST1S10
Typical performance characteristics
Figure 21. Efficiency vs. output current
Figure 22. Efficiency vs. output current
100
EFFICIENCY [%]
EFFICIENCY [%]
100
90
80
70
60
90
80
70
60
VIN-A=VIN-SW=VINH=5V, VOUT=3.3V, TJ=25°C
VIN-A=VIN-SW=VINH=16V, VOUT=12V, TJ=25°C
50
50
0
0.5
1
1.5
2
OUTPUT CURRENT [A]
2.5
3
0
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT [A]
19/26
Package mechanical data
9
ST1S10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
20/26
ST1S10
Package mechanical data
PowerSO-8 mechanical data
Dim.
mm.
Min.
Typ.
A
inch.
Max.
Min.
Typ.
1.70
A1
0.00
A2
1.25
b
0.31
c
0.17
D
4.80
D1
0.067
0.00
0.006
0.049
0.142
0.51
0.012
0.020
0.25
0.007
0.010
4.90
5.00
0.189
0193
0.197
2.24
3.10
3.20
0.088
0.122
0.126
E
5.80
6.00
6.20
0.228
0.236
0.244
E1
3.80
3.90
4.00
0.150
0.154
0.157
E2
1.55
2.41
2.51
0.061
0.095
0.099
e
0.15
Max.
1.27
0.050
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
0°
8°
0°
8°
ccc
0.10
0.004
7195016C
21/26
Package mechanical data
ST1S10
DFN8 (4x4) mechanical data
mm.
inch.
Dim.
Min.
Typ.
Max.
Min.
Typ.
Max.
A
0.80
0.90
1.00
0.031
0.035
0.039
A1
0
0.02
0.05
0
0.001
0.002
A3
0.20
0.008
b
0.23
0.30
0.38
0.009
0.012
0.015
D
3.90
4.00
4.10
0.154
0.157
0.161
D2
2.82
3.00
3.23
0.111
0.118
0.127
E
3.90
4.00
4.10
0.154
0.157
0.161
E2
2.05
2.20
2.30
0.081
0.087
0.091
e
L
0.80
0.40
0.50
0.031
0.60
0.016
0.020
0.024
7869653B
22/26
ST1S10
Package mechanical data
Tape & reel SO-8 mechanical data
mm.
inch.
Dim.
Min.
A
Typ.
Max.
Min.
330
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
Typ.
0.504
22.4
0.519
0.882
Ao
8.1
8.5
0.319
0.335
Bo
5.5
5.9
0.216
0.232
Ko
2.1
2.3
0.082
0.090
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
23/26
Package mechanical data
ST1S10
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Min.
Typ.
330
C
12.8
D
20.2
N
99
13.2
Max.
12.992
0.504
0.519
0.795
101
T
24/26
Max.
3.898
3.976
14.4
0.567
Ao
4.35
0.171
Bo
4.35
0.171
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
ST1S10
Revision history
10
Revision history
Table 6.
Document revision history
Date
Revision
Changes
28-Aug-2007
1
Initial release.
24-Sep-2007
2
Add RthJC on Table 4.
25-Oct-2007
3
Added new paragraph 6: Layout considerations.
25/26
ST1S10
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26/26