CY2DL1510, 1:10 Differential LVDS Fanout Buffer

CY2DL1510
1:10 Differential LVDS Fanout Buffer
1:10 Differential LVDS Fanout Buffer
Features
Functional Description
■
Low-voltage differential signal (LVDS) input with on-chip 100 
input termination resistor
■
Ten differential LVDS outputs
■
40 ps maximum output-to-output skew
■
600 ps maximum propagation delay
■
0.11 ps maximum additive RMS phase jitter at 156.25 MHz
(12 kHz to 20 MHz offset)
■
Up to 1.5 GHz operation
■
Synchronous clock enable function
■
32-pin thin quad flat pack (TQFP) package
■
2.5 V or 3.3 V operating voltage [1]
■
Commercial and industrial operating temperature range
The CY2DL1510 is an ultra-low noise, low-skew,
low-propagation delay 1:10 differential LVDS fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The on-chip 100  input termination
resistor reduces board component count, while the synchronous
clock enable function ensures glitch-free output transitions
during enable and disable periods. The device has a fully
differential internal architecture that is optimized to achieve
low-additive jitter and low-skew at operating frequencies of up to
1.5 GHz.
For a complete list of related documentation, click here.
Logic Block Diagram
Q0
Q0#
Q1
Q1#
VDD
Q2
Q2#
VSS
Q3
Q3#
IN
IN#
Q4
Q4#
100
Q5
Q5#
VDD
Q
100k
CLK_EN
Q6
Q6#
D
Q7
Q7#
VBB
Q8
Q8#
Q9
Q9#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-54863 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 5, 2016
CY2DL1510
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions ....................................................... 4
DC Electrical Specifications ............................................ 5
Thermal Resistance .......................................................... 5
AC Electrical Specifications ............................................ 6
Switching Waveforms ...................................................... 7
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Document Number: 001-54863 Rev. *K
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC®Solutions ....................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY2DL1510
Pinouts
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Figure 1. 32-pin TQFP pinout
24
23
22
21
20
19
18
17
VDD
25
16
VDD
Q2#
26
15
Q7
Q2
27
14
Q7#
Q1#
28
13
Q8
Q1
29
12
Q8#
Q0#
30
11
Q9
Q0
31
10
Q9#
VDD
32
9
VDD
2
3
4
5
6
7
CLK_EN
NC
NC
VBB
IN
IN#
8
VSS
1
VDD
CY2DL1510
Pin Definitions
Pin No.
Pin Name
Pin Type
1, 9, 16, 25,
32
VDD
Power
2
CLK_EN
Input
3, 4
NC
5
VBB
Description
Power supply
Synchronous clock enable. Low-voltage complementary metal oxide semiconductor
(LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When CLK_EN = Low, Q(0:9) outputs are held low and Q(0:9)# outputs are held high
No connection
Output
LVDS reference voltage output
6
IN
Input
LVDS input clock
7
IN#
Input
LVDS complementary input clock
8
VSS
Power
Ground
10, 12, 14,
17, 19, 21,
23, 26, 28, 30
Q(0:9)#
Output
LVDS complementary output clocks
11, 13, 15,
18, 20, 22,
24, 27, 29, 31
Q(0:9)
Output
LVDS output clocks
Document Number: 001-54863 Rev. *K
Page 3 of 15
CY2DL1510
Absolute Maximum Ratings
Min
Max
Unit
VDD
Parameter
Supply voltage
Description
Non-functional
Condition
–0.5
4.6
V
VIN[2]
Input voltage, relative to VSS
Non-functional
–0.5
lesser of
4.0 or
VDD + 0.4
V
VOUT[2]
DC output or I/O Voltage, relative Non-functional
to VSS
–0.5
lesser of
4.0 or
VDD + 0.4
V
TS
Storage temperature
Non-functional
–55
150
°C
ESDHBM
Electrostatic discharge (ESD)
protection (Human body model)
JEDEC STD 22-A114-B
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
Meets or exceeds JEDEC Spec
JESD78B IC latch up test
At 1/8 in.
V–0
3
Operating Conditions
Parameter
VDD
TA
tPU
Description
Supply voltage
Ambient operating temperature
Power ramp time
Condition
Min
Max
Unit
2.5 V supply
2.375
2.625
V
3.3 V supply
3.135
3.465
V
Commercial
0
70
°C
Industrial
–40
85
°C
Power-up time for VDD to reach minimum
specified voltage (power ramp must be
monotonic.)
0.05
500
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document Number: 001-54863 Rev. *K
Page 4 of 15
CY2DL1510
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
All LVDS outputs terminated with 100 load
Min
[3, 4]
Max
Unit
IDD
Operating supply current
–
125
mA
VIH1
Input high Voltage, LVDS input
clocks, IN and IN#
–
VDD + 0.3
V
VIL1
Input low voltage, LVDS input
clocks, IN and IN#
–0.3
–
V
VIH2
Input high voltage, CLK_EN
VDD = 3.3 V
2.0
VDD + 0.3
V
VIL2
Input low voltage, CLK_EN
VDD = 3.3 V
–0.3
0.8
V
VIH3
Input high voltage, CLK_EN
VDD = 2.5 V
1.7
VDD + 0.3
V
VIL3
Input low voltage, CLK_EN
VDD = 2.5 V
–0.3
0.7
V
VID[5]
Input differential amplitude
See Figure 3 on page 7
0.4
0.8
V
VICM
Input common mode voltage
See Figure 3 on page 7
0.5
VDD – 0.2
V
IIH
Input high current, All inputs
Input = VDD [6]
–
150
A
IIL
Input low current, All inputs
Input = VSS [6]
–150
–
A
VPP
LVDS differential output voltage
peak to peak, single-ended
VDD = 3.3 V or 2.5 V,
RTERM = 100  between Q and Q# pairs [3, 7]
250
470
mV
VOCM
Change in VOCM between
complementary output states
VDD = 3.3 V or 2.5 V,
RTERM = 100  between Q and Q# pairs [3, 7]
–
50
mV
VBB
Output reference voltage
0 to 150 A output current
1.125
1.375
V
RTERM
On-chip differential input
termination resistor
80
120

RP
Internal pull-up resistance,
LVCMOS logic input
CLK_EN pin
60
140
k
CIN
Input capacitance
Measured at 10 MHz per pin
–
3
pF
Thermal Resistance
Parameter [8]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
32-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
69
°C/W
14
°C/W
Notes
3. Refer to Figure 2 on page 7.
4. IDD includes current that is dissipated externally in the output termination resistors.
5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to Figure 4 on page 7.
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-54863 Rev. *K
Page 5 of 15
CY2DL1510
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Typ
Max
Unit
DC
–
1.5
GHz
FIN
Input frequency
FOUT
Output frequency
FOUT = FIN
DC
–
1.5
GHz
tPD[11]
Propagation delay input pair to
output pair
Input rise/fall time < 1.5 ns
(20% to 80%)
–
–
600
ps
tODC[12]
Output duty cycle
50% duty cycle at input
Frequency range up to 1 GHz
48
–
52
%
tSK1[13]
Output-to-output skew
Any output to any output, with same
load conditions at DUT
–
–
40
ps
tSK1 D[13]
Device-to-device output skew
Any output to any output between
two or more devices.
Devices must have the same input
and have the same output load.
–
–
150
ps
PNADD
Additive RMS phase noise
156.25 MHz input
Rise/fall time < 150 ps
(20% to 80%)
VID > 400 mV
Offset = 1 kHz
–
–
–120
dBc/
Hz
Offset = 10 kHz
–
–
–135
dBc/
Hz
Offset = 100 kHz
–
–
–135
dBc/
Hz
Offset = 1 MHz
–
–
–150
dBc/
Hz
Offset = 10 MHz
–
–
–154
dBc/
Hz
Offset = 20 MHz
–
–
–155
dBc/
Hz
tJIT[14]
Additive RMS phase jitter
(Random)
156.25 MHz,
12 kHz to 20 MHz offset;
input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
–
–
0.11
ps
tR, tF[15]
Output rise/fall time,
single-ended
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
Measured at 1 GHz
–
–
300
ps
tSOD
Time from clock edge to outputs Synchronous clock enable
disabled
(CLK_EN) switched low
–
–
700
ps
tSOE
Time from clock edge to outputs Synchronous clock enable
enabled
(CLK_EN) switched high
–
–
700
ps
Notes
9. Refer to Figure 2 on page 7.
10. Refer to Figure 4 on page 7.
11. Refer to Figure 5 on page 7.
12. Refer to Figure 6 on page 7.
13. Refer to Figure 7 on page 8.
14. Refer to Figure 8 on page 8.
15. Refer to Figure 9 on page 8.
Document Number: 001-54863 Rev. *K
Page 6 of 15
CY2DL1510
Switching Waveforms
Figure 2. LVDS Output Termination
Z = 50
BUF
Q
100
Z = 50
Q#
Figure 3. Input Differential and Common Mode Voltages
VA
IN
VICM = (VA + VB)/2
VID
IN#
VB
Figure 4. Output Differential and Common Mode Voltages
Q
VA
VOCM = (VA + VB)/2
VB
VOCM = | VOCM1 – VOCM2 |
VPP
Q#
Figure 5. Input to Any Output Pair Propagation Delay
IN
IN#
QX
QX#
tPD
Figure 6. Output Duty Cycle
QX
QX#
tPW
tPERIOD
tODC =
Document Number: 001-54863 Rev. *K
tPW
tPERIOD
Page 7 of 15
CY2DL1510
Switching Waveforms (continued)
Figure 7. Output-to-output and Device-to-device Skew
QX
QX#
Device 1
QY
QY#
tSK1
QZ
Device 2
QZ#
tSK1 D
Figure 8. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
RMS Jitter 
Area Under the Masked Phase Noise Plot
Figure 9. Output Rise/Fall Time
QX
80% 80%
VPP
20%
QX#
20%
tR
Document Number: 001-54863 Rev. *K
tF
Page 8 of 15
CY2DL1510
Switching Waveforms (continued)
Figure 10. Synchronous Clock Enable Timing
CLK_EN
IN
IN#
tSOD
tPD
tSOE
QX
QX#
Document Number: 001-54863 Rev. *K
Page 9 of 15
CY2DL1510
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2DL1510AZC
32-pin TQFP
Commercial, 0 °C to 70 °C
CY2DL1510AZCT
32-pin TQFP – Tape and Reel
Commercial, 0 °C to 70 °C
CY2DL1510AZI
32-pin TQFP
Industrial, –40 °C to 85 °C
CY2DL1510AZIT
32-pin TQFP – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2DL15 10
AZ
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: AZ = 32-pin TQFP Package
Number of differential output pairs
Base Part Number
Company ID: CY = Cypress
Document Number: 001-54863 Rev. *K
Page 10 of 15
CY2DL1510
Package Diagram
Figure 11. 32-pin TQFP (7 × 7 × 1.0 mm) A 3210 Package Outline, 51-85063
51-85063 *E
Document Number: 001-54863 Rev. *K
Page 11 of 15
CY2DL1510
Acronyms
Acronym
Document Conventions
Description
Units of Measure
ESD
Electrostatic Discharge
HBM
Human Body Model
°C
degree Celsius
JEDEC
Joint Electron Devices Engineering Council
dBc
decibels relative to the carrier
LVDS
Low-Voltage Differential Signal
GHz
gigahertz
LVCMOS
Low-Voltage Complementary Metal Oxide
Semiconductor
Hz
hertz
LVTTL
Low-Voltage Transistor-Transistor Logic
OE
Output Enable
RMS
Root Mean Square
TQFP
Thin Quad Flat Pack
Document Number: 001-54863 Rev. *K
Symbol
Unit of Measure
k
kilohm
MHz
megahertz
µA
microampere
µF
microfarad
µs
microsecond
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond

ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 12 of 15
CY2DL1510
Document History Page
Document Title: CY2DL1510, 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
Revision
ECN
Orig. of
Change
Submission
Date
**
2744225
CXQ /
PYRS
08/19/09
New data sheet.
*A
2782891
CXQ
10/09/09
Updated format of Logic Block Diagram on page 1.
Added TSOD and TSOE specs (700 ps max) to AC Specs table.
Added TSETUP and THOLD specs (300 ps min) to AC Specs table.
Changed equation for RMS jitter in Figure 8 to proportionality.
Changed package drawing from 1.4 mm thickness 51-85088 spec to
1.0 mm thickness 51-850063 spec.
Added “Synchronous Clock Enable Function” to Features on page 1.
*B
2838916
CXQ
01/05/2010
*C
2885033
CXQ
02/26/2010
Updated 32-Pin TQFP package diagram.
*D
3011766
CXQ
08/20/2010
Changed maximum additive jitter from 0.25 ps to 0.11 ps in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 5.
Changed max tPD spec from 480 ps to 600 ps.
Added note 5 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Changed RP for differential inputs from 100 k to 150 k in the Logic Block
Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the
DC Electrical Specs table.
Added VID max spec of 0.8V in the DC Electrical Specs table.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs
table.
Added “Frequency range up to 1 GHz” condition to tODC spec.
Added Acronyms and Ordering Code Definition.
*E
3017258
CXQ
08/27/2010
Corrected Output Rise/Fall time diagram.
Document Number: 001-54863 Rev. *K
Description of Change
Changed status from Advance to Preliminary.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 5.
Added tPU spec to the Operating Conditions table on page 3.
Removed VOD and VOD specs from the DC Electrical Specs table on page 4.
Added VPP and VPP specs to the AC Electrical Specs table on page 5. VPP
min = 250 mV and max = 470 mV; VPP max = 50 mV.
Added internal pullup resistance spec for CLK_EN in the DC Electrical Specs
table on page 4. Min = 60 k, Max = 140 k.
Added a measurement definition for CIN in the DC Electrical Specs table on
page 4.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to tR and tF specs in the AC Electrical specs table on page 5
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
5, 6, 7, and 9, to be consistent with EROS. Updated Figure 4 with definitions
for VPP and VPP.
Page 13 of 15
CY2DL1510
Document History Page (continued)
Document Title: CY2DL1510, 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*F
3100234
CXQ
11/18/2010
Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Moved VPP from AC spec table to DC spec table, removed VPP.
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets.
Added “Measured at 1 GHz” to tR, tF spec condition.
Removed tS and tH specs from AC specs table.
Changed to CY2DL1510AZ package code in Ordering Information.
Added to Z package code in Ordering Code Definition.
*G
3135201
CXQ
01/12/2011
Changed status from Preliminary to Final.
Updated Logic Block Diagram (Fixed typo and removed resistors from IN/IN#).
Updated Switching Waveforms:
Added Figure 10 (to describe TSOE and TSOD).
*H
3090938
CXQ
02/25/2011
Post to external web.
*I
3952187
CINM
04/02/2013
Updated Package Diagram:
spec 51-85063 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*J
4586288
CINM
12/04/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*K
5260362
TAVA
05/05/2016
Added Thermal Resistance.
Updated Package Diagram:
spec 51-85063 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
Document Number: 001-54863 Rev. *K
Page 14 of 15
CY2DL1510
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
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Document Number: 001-54863 Rev. *K
Revised May 5, 2016
Page 15 of 15