CY2CP1504
1:4 LVCMOS to LVPECL Fanout Buffer
with Selectable Clock Input
1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Features
Functional Description
■
Select one of two low-voltage complementary metal oxide
semiconductor (LVCMOS) inputs to distribute to four
low-voltage positive emitter-coupled logic (LVPECL) output
pairs
■
30-ps maximum output-to-output skew
■
480-ps maximum propagation delay
■
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
The CY2CP1504 is an ultra-low noise, low-skew,
low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The CY2CP1504 can select between
two separate LVCMOS input clocks using the IN_SEL pin. The
synchronous clock enable function ensures glitch-free output
transitions during enable and disable periods. The device has a
fully differential internal architecture that is optimized to achieve
low additive jitter and low skew at operating frequencies of up to
250 MHz.
■
Up to 250 MHz operation
For a complete list of related documentation, click here.
■
Synchronous clock enable function
■
20-Pin thin shrunk small outline package (TSSOP) package
■
2.5-V or 3.3-V operating voltage [1]
■
Commercial and industrial operating temperature range
Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56313 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY2CP1504
Contents
Pin Configurations ...........................................................3
Pin Definitions ..................................................................3
Absolute Maximum Ratings ............................................4
Operating Conditions .......................................................4
DC Electrical Specifications ............................................5
Thermal Resistance ..........................................................5
AC Electrical Specifications ............................................6
Ordering Information ........................................................9
Ordering Code Definitions ...........................................9
Package Diagram ............................................................10
Document Number: 001-56313 Rev. *J
Acronyms ........................................................................11
Document Conventions .................................................11
Units of Measure .......................................................11
Document History Page .................................................12
Sales, Solutions, and Legal Information ......................14
Worldwide Sales and Design Support .......................14
Products ....................................................................14
PSoC®Solutions ........................................................14
Cypress Developer Community .................................14
Technical Support ......................................................14
Page 2 of 14
CY2CP1504
Pin Configurations
Figure 1. 20-pin TSSOP Package pinout
Pin Definitions
Pin No.
Pin Name
Pin Type
1
VSS
Power
2
CLK_EN
Input
Synchronous clock enable. LVCMOS/low-voltage transistor-transistor logic (LVTTL).
When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high
3
IN_SEL
Input
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, input IN0 is active
When IN_SEL = High, input IN1 is active
4
IN0
Input
LVCMOS input clock. Active when IN_SEL = Low
Input
LVCMOS input clock. Active when IN_SEL = High
5, 7, 8, 9
NC
6
IN1
Description
Ground
No connection
10, 13, 18
VDD
Power
Power supply
11, 14, 16, 19
Q(0:3)#
Output
LVPECL complementary output clocks
12, 15, 17, 20
Q(0:3)
Output
LVPECL output clocks
Document Number: 001-56313 Rev. *J
Page 3 of 14
CY2CP1504
Absolute Maximum Ratings
Parameter
VDD
Description
Condition
Min
Max
Unit
Supply voltage
Nonfunctional
–0.5
4.6
V
VIN
Input voltage, relative to VSS
Nonfunctional
–0.5
lesser of
4.0 or
VDD + 0.4
V
VOUT[2]
DC output or I/O voltage, relative Nonfunctional
to VSS
–0.5
lesser of
4.0 or
VDD + 0.4
V
TS
Storage temperature
–55
150
°C
ESDHBM
Electrostatic discharge (ESD)
JEDEC STD 22-A114-B
protection (Human body model)
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
[2]
Nonfunctional
Meets or exceeds JEDEC
Spec JESD78B IC latch up test
At 1/8 in
V-0
3
Operating Conditions
Parameter
VDD
TA
tPU
Description
Supply voltage
Ambient operating temperature
Power ramp time
Condition
Min
Max
Unit
2.5 V supply
2.375
2.625
V
3.3 V supply
3.135
3.465
V
Commercial
0
70
°C
Industrial
–40
85
°C
Power-up time for VDD to reach minimum
specified voltage (power ramp must be
monotonic)
0.05
500
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56313 Rev. *J
Page 4 of 14
CY2CP1504
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Max
Unit
–
61
mA
VDD = 3.3 V
2.0
VDD + 0.3
V
Input low voltage, All inputs
VDD = 3.3 V
–0.3
0.8
V
IDD
Operating supply current
All LVPECL outputs floating (internal IDD)
VIH1
Input high voltage, All inputs
VIL1
VIH2
Input high voltage, All inputs
VDD = 2.5 V
1.7
VDD + 0.3
V
VIL2
Input low voltage, All inputs
VDD = 2.5 V
–0.3
0.7
V
IIH
Input high current, All inputs
Input = VDD[3]
–
150
A
–150
–
A
IIL
Input low current, All inputs
Input =
VSS[3]
[4]
VDD – 1.20 VDD – 0.70
V
VDD – 2.0 VDD – 1.63
V
VOH
LVPECL output high voltage
Terminated with 50 to VDD – 2.0
VOL
LVPECL output low voltage
Terminated with 50 to VDD – 2.0 [4]
RP
Internal pull-up/pull-down
resistance
CLK_EN has pull-up only
IN_SEL has pull-down only
60
165
k
CIN
Input capacitance
Measured at 10 MHz; per pin
–
3
pF
Thermal Resistance
Parameter [5]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
20-pin TSSOP Unit
80
°C/W
16
°C/W
Notes
3. Positive current flows into the input pin, negative current flows out of the input pin.
4. Refer to Figure 2 on page 7.
5. These parameters are guaranteed by design and are not tested.
Document Number: 001-56313 Rev. *J
Page 5 of 14
CY2CP1504
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85°C (Industrial))
Parameter
Description
Condition
Min
Typ
Max
Unit
FIN
Input frequency
DC
–
250
MHz
FOUT
Output frequency
FOUT = FIN
DC
–
250
MHz
VPP
LVPECL differential output
voltage peak- to-peak,
single-ended.
Terminated with 50 to
VDD – 2.0 [4]
Fout = DC to 150 MHz
600
–
–
mV
Fout = >150 MHz to 250 MHz
400
–
–
mV
tPD[6]
Propagation delay input to output Input rise/fall time < 1.5 ns
pair
(20% to 80%)
–
–
480
ps
tODC[7]
Output duty cycle
Rail-to-rail input swing, 50% input
DTCY measured at Vdd/2
45
–
55
%
tSK1[8]
Output-to-output skew
Any output to any output, with same
load conditions at DUT
–
–
30
ps
tSK1 D[8]
Device-to-device output skew
Any output to any output between
two or more devices. Devices must
have the same input and have the
same output load.
–
–
150
ps
PNADD
Additive RMS phase noise
156.25-MHz Input
Rise/fall time < 150 ps
(20% to 80%)
VID > 400 mV
Offset = 1 kHz
–
–
–120
dBc/
Hz
Offset = 10 kHz
–
–
–130
dBc/
Hz
Offset = 100 kHz
–
–
–135
dBc/
Hz
Offset = 1 MHz
–
–
–150
dBc/
Hz
Offset = 10 MHz
–
–
–150
dBc/
Hz
Offset = 20 MHz
–
–
–150
dBc/
Hz
tJIT[9]
Additive RMS phase jitter
(Random)
156.25 MHz sinewave,
12 kHz to 20 MHz offset; input
swing = 2.2V, Vbias = VDD/2
–
–
0.15
ps
tR, tF[10]
Output rise/fall time
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
–
–
300
ps
tSOD
Time from clock edge to outputs Synchronous clock enable
disabled
(CLK_EN) switched Low
–
–
700
ps
tSOE
Time from clock edge to outputs Synchronous clock enable
enabled
(CLK_EN) switched high
–
–
700
ps
Notes
6. Refer to Figure 3 on page 7.
7. Refer to Figure 4 on page 7.
8. Refer to Figure 5 on page 7.
9. Refer to Figure 6 on page 8.
10. Refer to Figure 7 on page 8.
Document Number: 001-56313 Rev. *J
Page 6 of 14
CY2CP1504
Figure 2. Output Differential Voltage
Figure 3. Input to Any Output Pair Propagation Delay
Figure 4. Output Duty Cycle
Figure 5. Output-to-Output and Device-to-Device Skew
Document Number: 001-56313 Rev. *J
Page 7 of 14
CY2CP1504
Figure 6. RMS Phase Jitter
Figure 7. Output Rise/Fall Time
Figure 8. Synchronous Clock Enable Timing
Document Number: 001-56313 Rev. *J
Page 8 of 14
CY2CP1504
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2CP1504ZXC
20-pin TSSOP
Commercial, 0 °C to 70 °C
CY2CP1504ZXCT
20-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
CY2CP1504ZXI
20-pin TSSOP
Industrial, –40 °C to 85 °C
CY2CP1504ZXIT
20-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2
C P15
04
Z
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
Z = 20-pin TSSOP
Number of differential output pairs
Base part number
Technology Code: C = CMOS
Marketing Code: 2 = Buffer
Company ID: CY = Cypress
Document Number: 001-56313 Rev. *J
Page 9 of 14
CY2CP1504
Package Diagram
Figure 9. 20-pin TSSOP (4.40 mm Body) Z20.173/ZZ20.173 Package Outline, 51-85118
51-85118 *E
Document Number: 001-56313 Rev. *J
Page 10 of 14
CY2CP1504
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
ESD
electrostatic discharge
HBM
human body model
°C
degree Celsius
JEDEC
joint electron devices engineering council
dBc
decibels relative to the carrier
LVDS
low-voltage differential signal
GHz
gigahertz
LVCMOS
low-voltage complementary metal oxide semiconductor
Hz
hertz
LVPECL
low-voltage positive emitter-coupled logic
k
kilohm
LVTTL
low-voltage transistor-transistor logic
μA
microampere
RMS
root mean square
μF
microfarad
TSSOP
thin shrunk small outline package
μs
microsecond
Document Number: 001-56313 Rev. *J
Symbol
Unit of Measure
mA
milliampere
ms
millisecond
mV
millivolt
MHz
megahertz
ns
nanosecond
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 11 of 14
CY2CP1504
Document History Page
Document Title: CY2CP1504, 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-56313
Revision
ECN
Orig. of
Change
Submission
Date
**
2782891
CXQ
10/09/09
*A
2838916
CXQ
05/01/2010
Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 5.
Added tPU spec to the Operating Conditions table on page 3.
Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA
to 61 mA.
Changed VOH in the DC Electrical Specs table on page 4: minimum from VDD
- 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V.
Removed VOD spec from the DC Electrical Specs table on page 4.
Added RP spec in the DC Electrical Specs table on page 4. Min = 60 k, Max
= 140 k.
Added a measurement definition for CIN in the DC Electrical Specs table on
page 4.
Added VPP spec to the AC Electrical Specs table on page 5. VPP min = 600
mV for DC - 150 MHz and min = 400 mV for 150 MHz to 250 MHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to tR and tF specs in the AC Electrical specs table on page 5
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
2, 3, 4, 5 and 7, to be consistent with EROS.
*B
3011766
CXQ
08/20/2010
Changed from 0.25 ps to 0.15 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 6.
Added note 2 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs
table.
Updated package diagram.
Added Acronyms and Ordering Code Definition.
*C
3017258
CXQ
08/27/2010
Corrected Output Rise/Fall time diagram.
*D
3100234
CXQ
11/18/2010
Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Changed CIN condition to “Measured at 10 MHz”.
Removed tR and tF input specs from AC specs table.
Changed tODC from 48/52% to 45/55%, changed condition to “Rail-to-rail input
swing, 50% input duty cycle measured at Vdd/2”.
Changed phase jitter condition to “156.25 MHz sinewave, 12 kHz to 20 MHz
offset; input swing = 2.2V, Vbias = VDD/2 “
Removed tS and tH specs from AC specs table.
*E
3137726
CXQ
01/13/2011
Removed “Preliminary” status heading.
Removed resistors from IN0/IN1 in Logic Block Diagram.
Added Figure 8 to describe TSOE and TSOD.
*F
3182321
CXQ
02/25/11
*G
3208968
CXQ
03/29/2011
Document Number: 001-56313 Rev. *J
Description of Change
New data sheet
Post to external web.
Changed RP max from 140 k to 165 k and updated RP in Logic Block
Diagram.
Page 12 of 14
CY2CP1504
Document History Page (continued)
Document Title: CY2CP1504, 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-56313
Revision
ECN
Orig. of
Change
Submission
Date
*H
3878020
PURU
01/21/2013
Updated Package Diagram:
spec 51-85118 – Changed revision from *C to *D.
Updated to new template.
*I
4587249
PURU
12/03/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram:
spec 51-85118 – Changed revision from *D to *E.
*J
5267558
PSR
Document Number: 001-56313 Rev. *J
Description of Change
05/13/2016 Added Thermal Resistance.
Updated to new template.
Page 13 of 14
CY2CP1504
Sales, Solutions, and Legal Information
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including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-56313 Rev. *J
Revised May 13, 2016
Page 14 of 14