AN49081 Requirements for Input Clock to West Bridge Devices.pdf

AN49081
Requirements for Input Clock to West Bridge® Devices
Author: Sonia Gandhi
Associated Project: No
Associated Part Family: CYWB012AB, CYWB022AB, CY7C68003
Software Version: NA
Related Application Notes: None
To get the latest version of this application note, or the associated project file, please visit
http://www.cypress.com/go/AN49081.
AN49081 addresses the requirements for the input clock to West Bridge® devices that includes Antioch™, Astoria™, and
TX3LP18. The conversion of phase noise specifications into equivalent RMS jitter is also discussed.
Table 1 lists the specifications for these requirements.
Introduction
This document addresses the input clock requirements for
three devices in the West Bridge® family of products:
Antioch, Astoria, and TX3LP18. The computation of
equivalent RMS jitter from phase noise characteristics is
also discussed.
®
The West Bridge Antioch™ and Astoria™ devices are
peripheral controllers that support High-Speed USB and
mass storage access. These controllers provide access
from both a processor interface and a High-Speed USB
interface to peripherals that include SD, MMC/MMC+, CEATA, SDIO, and NAND.
The MoBL-USB™ TX3LP18 is a low voltage High-Speed
USB 2.0 ULPI Transceiver.
The three devices have the same requirements for the
input clock, which are discussed in this application note.
Input Clock Requirements
The three West Bridge devices each support a subset
(four) of the following input frequencies: 13 MHz,
19.2 MHz, 24 MHz, 26 MHz, 38.4 MHz, and 48 MHz.
The critical requirements for the input clock to these West
Bridge devices are:




Phase noise requirements
Maximum frequency deviation
Maximum rise and fall time
Table 1. Input Clock Specifications for West Bridge
Devices
Specification
Parameter
Description
Unit
Min
Max
100 Hz Offset
-
-75
dBc/Hz
1 kHz Offset
-
-104
dBc/Hz
10 kHz Offset
-
-120
dBc/Hz
100 kHz Offset
-
-128
dBc/Hz
1 MHz Offset
-
-130
dBc/Hz
Maximum
frequency
deviation
-
150
ppm
Duty cycle
30
70
%
Overshoot
-
3
%
Undershoot
-
-3
%
Rise time
-
3
ns
Fall time
-
3
ns
Phase noise
An input clock supplied to a West Bridge device must
meet the requirements specified in Table 1.
Some clock manufacturers specify RMS jitter rather than
phase noise characteristics. Phase noise characteristics
may be directly converted into the equivalent RMS jitter.
This is explained in the next section.
Square wave signal
www.cypress.com
Document No. 001-49081 Rev. *B
1
®
Requirements for Input Clock to West Bridge Devices
or
Computation of RMS Jitter from
Phase Noise
RMSJ per 
The phase noise specifications in Table 1 are precise
measurements for the input clock quality. The equivalent
RMS jitter requirement can be derived from the phase
noise specifications. The input noise specifications listed
in Table 1 are converted into a graph in Figure 1.
Figure 1. Phase Noise Requirements for Input Clock to
West Bridge Devices
Phase Noise Requirements for Input Clock to
West Bridge Devices
-70
Phase Noise
(dBc/Root(Hz))
-90
-100
1000, -104
-110
-120
10000, -120
100000, -128
-130
1000000, -130
-140
10
In Equation 2 and Equation 3:
ai  ( L( fi 1 )  L( fi )) /(log( fi 1 )  log( fi )) Equation 4
bi  L( f i )
100
1000
10000
100000 1000000
In these equations, L(fi) is the value of the phase noise
spectrum at any frequency, and fi. ai is the slope of the
phase noise spectrum between frequencies fi and fi+1.
From Equation 1 to Equation 5, RMS jitter is calculated
from the phase noise spectrum plot.
The internal PLL of the West Bridge devices is sensitive to
phase noise over the frequency range of 100 Hz to
5 MHz. By integrating the piecewise linear form of the
input phase noise characteristics over the frequency range
of 100 Hz to 5 MHz, the equivalent RMS jitter
requirements are obtained. The RMS jitter requirement for
the different input frequencies is calculated and listed in
Table 2.
Table 2. Maximum RMS Jitter for Valid Input Frequencies
Offset (Hz)
Number
The RMS jitter that can be tolerated is a function of the
area under the curve that is shown in Figure 1.
f
RMSJ per  f1tof2
Equation 5
RMS Jitter Requirements
100, -75
-80
1
1
bi
a
ai
K 1
a
1  Equation 3
1
  i 1
 i a
10
21010 fi 10  i  1  fi 10

1  f i
2fc i 1
10  

2
1

2 10
2fc
f1
L( f )
10
df
Equation 1
In Equation 1:
Input Freq (MHz)
Maximum RMS Jitter (ps)
1
13
25.81
2
19.2
17.47
3
24
13.98
4
26
12.90
5
38.4
8.74
6
48
6.99
L(f) = Phase Noise Spectrum
Jper = Period Jitter
Summary
f1-f2 is the frequency band of interest.
Since the frequency axis of the phase noise spectrum
shown in Figure 1 is in log scale, the RMS period jitter is
approximated as a piecewise linear function of L(f) that is
summed up from a provided curve as shown in the same
figure.
This application note addresses the requirements of the
input clock to West Bridge devices Antioch, Astoria, and
TX3LP18. The conversion from phase noise to equivalent
RMS jitter is also discussed. This conversion is applied to
the input phase noise specification. The equivalent RMS
jitter numbers are derived for all input clock frequencies.
The RMS jitter is derived from the following equations:
i
K 1
a
1
 i
21010 f i 10
2fc
i 1
b
RMSJ per 
www.cypress.com
f i 1

ai
f 10 df Equation 2
fi
Document No. 001-49081 Rev. *B
2
®
Requirements for Input Clock to West Bridge Devices
Document History
Document Title: Requirements for Input Clock to West Bridge® Devices - AN49081
Document Number: 001-49081
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
2571675
OSG /
AESA
09/27/2008
New application note.
*A
3412955
HBM
10/18/2011
Updated to new template.
Completing Sunset Review.
*B
4556107
PRVE
10/30/2014
Updated to new template.
Completing Sunset Review.
www.cypress.com
Document No. 001-49081 Rev. *B
3
®
Requirements for Input Clock to West Bridge Devices
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
West Bridge is a registered trademark of Cypress Semiconductor Corp. Astoria, Antioch, and MoBL-USB is trademarks of Cypress Semiconductor
Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2008-2014. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-49081 Rev. *B
4