ATMEL T2801-PLH

T2801
DECT Single-Chip Transceiver
Description
The T2801 is an RF IC for low-power DECT applications. The HP-VFQFP-N48-packaged IC is a complete
transceiver including image rejection mixer, IF amplifier,
FM demodulator, baseband filter, RSSI, TX preamplifier,
power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and
modulation compensation circuit for advanced closedloop modulation concept. No mechanical tuning is
necessary in production.
Electrostatic sensitive device.
Observe precautions for handling.
Features
Supply-voltage range 3 V to 4.6 V (unregulated)
Non-blindslot and blindslot operation
Auxiliary-voltage regulator on-chip
Unlimited multislot operation with advanced closedloop modulation
Low current consumption
Supports multiple reference clocks (10.368 MHz/
13.824 MHz/ 20.736 MHz)
Few low cost external components
No mechanical tuning required
TX preamplifier with 0 dBm output power at 1.9 GHz
and ramp-signal generator for SiGe power amplifier
Block Diagram
MIXER
IF_IN
OUT
IF AMP 1
IR MIXER
DEMOD
TANK
IF_TANK
CF
IF AMP 2
BB_OUT
RF_IN
DEMOD
BB FILTER
RAMP_OUT
D/A
RAMP
GEN
RAMP_SET
DEMOD DAC
RSSI
RSSI
GF
VCO
TX / RX
SWITCH
TX_DATA
PC
PD
f
TX_OUT
MCC
3-WIRE
BUS
CLOCK
DATA
ENABLE
RC
CTRL
LOGIC
RX_ON
TX_ON
PU_RX/TX
PU_PLL
:n
TX DRIVER
PU_VCO
VCO
REG
CP
AUX
REG
f
:n
VREG_VCO
VS_VCO
VREG VS_REG VTUNE
GND_VCO
PU_REG REG_CTRL
CP
LD
REF_CLK
I_CPSW
Figure 1. Block diagram
Ordering Information
Extended Type Number
T2801-PLH
Package
HP-VFQFP-N48
Remarks
Taped and reeled
Rev. A9, 11-Dec-01
1 (27)
Preliminary Information
T2801
Functional Block Description
Name
Description
Name
Description
AUX REG
Auxiliary voltage regulator
PC
Programmable counter
BBF
Baseband filter
PD
Phase detector
CP
Charge pump
RAMP GEN
Ramp-signal generator
DAC
D/A converter for demodulator tuning
RC
Reference counter
DEMOD
Demodulator
RSSI
Received signal-strength indicator
GF
Gaussian filter for transmit data
TX DRIVER Buffer amplifier for TX_OUT
IF AMP1
1st intermediate frequency amplifier
IF AMP2
2nd intermediate frequency amplifier
TX/RX
SWITCH
Switches VCO signal to IR MIXER
resp. TX DRIVER
IR MIXER
Image rejection mixer
VCO
Voltage-controlled oscillator
MCC
Modulation compensation circuit
VCO REG
Voltage regulator for VCO
I_CPSW
TX_DATA
PU_PULL
PU_RX/TX
PU_VCO
GND_PLL
VS_MIXER
MIXER_OUT2
MIXER_OUT1
TX_ON
RX_ON
RAMP_SET
Pinning
48
47
46
45
44
43
42
41
40
39
38
37
CLOCK
1
36
RAMP_OUT
DATA
2
35
IF_IN2
ENABLE
3
34
IF_IN1
REF_CLK
4
33
VS_IF
LD
5
32
TX_OUT
PU_REG
6
31
GND3
VS_PLL
7
30
RF_IN2
VREG
8
29
RF_IN1
REG_CTRL
9
28
GND2
VS_REG
10
27
IF_TANK2
GND_CP
11
26
IF_TANK1
VS_CP
12
25
RSSI
20
21
22
23
24
BB_CF
BB_OUT
GND_VCO
19
REG_DEC
VREG_VCO
18
DAC_DEC
VS_VCO
17
DEMOD_TANK2
16
DEMOD_TANK1
15
GND1
14
VTUNE
13
CP
T2801
Figure 2. Pinning
2 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Pin Description
Pin
Symbol
1
CLOCK
Function
3-wire-bus: Clock input
Configuration
VS_PLL
7
2
3
DATA
ENABLE
3-wire-bus: Data input
3-wire-bus: Enable input
CLOCK
DATA
ENABLE
123
1,2,3
5k
5k
GND_PLL
43
4
REF_CLK
Reference-frequency input
VS_PLL
7
10k
10k
REF_CLK
4
GND_PLL
43
5
LD
Lock-detect output
LD
5
100
GND_PLL
43
6
PU_REG
Power-up input for aux. voltage
regulator
PU_REG
6
25k
25k
GND_PLL
43
Rev. A9, 11-Dec-01
3 (27)
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
7
VS_PLL
Function
PLL supply voltage
Configuration
VS_PLL
7
GND1
VS_REG
10
VS_CP
12
18
GND2
28
VS_VCO
14
GND3
31
VS_IF
33
GND_VCO
16
GND_CP
11
GND_PLL
43
VS_MIXER
42
8
VREG
Aux. voltage-regulator output
VS_REG
10
REG_CTRL
9
9
10
REG_CTRL
VS_REG
Aux. voltage-regulator control
output
VREG
8
Aux. voltage-regulator supply
voltage
GND_PLL
43
11
GND_CP
12
VS_CP
Charge-pump ground
Charge-pump supply voltage
VS_CP
12
CP
13
13
CP
Charge-pump output
GND_CP
11
4 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
Function
14
VS_VCO
VCO voltage-regulator supply
voltage
15
VREG_VCO
VCO voltage-regulator control
output
16
GND_VCO
VCO ground
Configuration
VS_VCO
14
VREG_VCO
VREG
VCO
15
GND_VCO
16
17
VTUNE
VCO tuning voltage input
VREG_VCO
15
VTUNE
17
GND_VCO
16
18
GND1
Ground
VS_PLL
7
VS_REG
10
VS_CP
12
GND1
18
GND2
28
VS_VCO
14
GND3
31
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
Rev. A9, 11-Dec-01
GND_PLL
43
5 (27)
Preliminary Information
T2801
Pin Description (continued)
Pin
19
Symbol
Function
DEMOD_TANK1 Demodulator tank circuit
Configuration
VS_MIXER
42
10k
20
10k
DEMOD_
TANK1
DEMOD_
TANK2
19
20
DEMOD_TANK2 Demodulator tank circuit
GND1
18
21
DAC_DEC
Decoupling PIN for VCO_DAC
VREG_VCO
15
10k
DAC_DEC
21
400
GND_VCO
16
22
REG_DEC
Decoupling PIN for VCO_REG
VREG_VCO
15
2k
REG_DEC
22
42k
GND_VCO
16
23
BB_CF
Baseband filter corner-frequency
control input
VS_IF
33
BB_CF
23
GND1
18
6 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
24
BB_OUT
Function
Configuration
Baseband filter output
VS_IF
33
BB_OUT
24
GND1
18
25
RSSI
Received signal-strength indicator
output
VS_IF
33
RSSI
25
13k
GND2
28
26
IF_TANK1
IF tank circuit
VS_IF
33
IF_TANK1
26
27
IF_TANK2
IF_TANK2
27
IF tank circuit
GND2
28
28
GND2
Ground
VS_PLL
7
VS_REG
10
VS_CP
12
GND1
18
GND2
28
VS_VCO
14
GND3
31
VS_IF
33
GND_VCO
16
GND_CP
11
VS_MIXER
42
Rev. A9, 11-Dec-01
GND_PLL
43
7 (27)
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
Function
29
RF_IN1
RF input of image reject mixer
30
RF_IN2
RF input of image reject mixer
Configuration
VS_MIXER
42
RF_IN1
RF
IN1
29
RF_IN2
RF
IN2
30
GND2
28
31
GND3
Ground
VS_PLL
7
GND1
VS_REG
10
VS_CP
12
18
GND2
28
VS_VCO
14
GND3
31
VS_IF
33
GND_VCO
16
GND_CP
11
GND_PLL
43
VS_MIXER
42
32
TX_OUT
TX driver amplifier output for PA
TX_OUT
32
GND3
31
8 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
33
VS_IF
Function
Configuration
IF amplifier supply voltage
VS_PLL
7
GND1
VS_REG
10
VS_CP
12
18
GND2
28
VS_VCO
14
GND3
31
VS_IF
33
GND_VCO
16
GND_CP
11
GND_PLL
43
VS_MIXER
42
34
IF_IN1
IF input of IF amplifier
35
IF_IN2
IF input of IF amplifier
VS_IF
33
IF_IN1
IF
IN1
34
IF_IN2
IF
IN2
35
4.3k
GND2
28
36
RAMP_OUT
Ramp-generator output for PA
power ramping
VS_MIXER
42
RAMP_OUT
36
GND2
28
Rev. A9, 11-Dec-01
9 (27)
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
Function
37
RAMP_SET
Slew-rate setting of ramping signal
Configuration
VS_MIXER
42
RAMP_SET
37
56
GND2
25
38
RX_ON
RX control input
39
TX_ON
TX control input
VS_IF
33
RX_ON
TX_ON
38, 39
5k
5k
GND1
18
40
MIXER_OUT1
Mixer output to SAW filter
VS_MIXER
42
MIXER_
OUT1
40
41
MIXER_OUT2
270
270
MIXER_
OUT2
41
Mixer output to SAW filter
GND2
28
10 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Pin Description (continued)
Pin
Symbol
42
VS_MIXER
Function
Configuration
Mixer supply voltage
VS_PLL
7
GND1
VS_REG
10
VS_CP
12
18
GND2
28
VS_VCO
14
GND3
31
43
GND_PLL
PLL ground
VS_IF
33
GND_VCO
16
GND_CP
11
GND_PLL
43
VS_MIXER
42
44
PU_VCO
VCO power-up input
VS_VCO
14
PU_VCO
44
5k
5k
GND_VCO
16
45
PU_RX/TX
RX/TX power-up input
PU_RX/TX
45
25k
25k
GND1
18
Rev. A9, 11-Dec-01
11 (27)
Preliminary Information
T2801
Pin Description (continued)
Pin
46
Symbol
PU_PLL
Function
Configuration
20k
PLL power-up input
10k
140k
10k
10k
25k
25k
PU_
PLL
46
GND_
PLL
43
47
TX_DATA
TX data input of Gaussian filter and
modulation-compensation circuit
VS_PLL
7
TX_DATA
47
5k
5k
GND_PLL
43
48
I_CPSW
Charge pump switch input controls
charge pump current
VS_PLL
7
I_CPSW
48
5k
GND_PLL
43
12 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Functional Description
Receiver
Synthesizer
The RF signal at RF_IN is fed to an image rejection mixer
IR_MIXER with its differential outputs MIXER_OUT1
and MIXER_OUT2 driving an IF-SAW filter at
110.592 MHz or 112.32 MHz. The IF amplifiers
IF_AMP1 and IF_AMP2 with an external IF_TANK and
an integrated RSSI function feed the signal to the
demodulator DEMOD working at f = fIF/2 (55 MHz)
and finally to an integrated baseband filter BB. For
demodulator tuning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the
on-chip varicap diode.
The IR_MIXER, the TX_DRIVER and the
programmable counter PC are driven by the fully
integrated VCO (including on-chip inductors and
varactors). An 3-bit digital-to-analog converter is used to
pretune the frequency. The output signal is frequencydivided to supply the desired frequency to the
TX_DRIVER, 0/90 degree phase shifter for the
IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation
is possible by using the integrated advanced closed-loop
modulation concept based on the modulation
compensation circuit MCC.
Transmitter
The transmit data at TX_DATA is filtered by an integrated
Gaussian Filter GF and fed to the fully integrated VCO
operating at twice the output frequency. After modulation
the signal is frequency-divided by 2 and fed via a TX/RX
SWITCH to the TX_DRIVER. This bus-controlled driver
amplifier supplies typical +3 dBm output power at
TX_OUT. A ramp-signal generator RAMP_GEN, provides a ramp signal at RAMP_OUT for the external power
amplifier, is integrated. The slope of the ramp signal is
controlled by a capacitor at the RAMP_SET pin.
Power Supply
An integrated bandgap-stabilized voltage regulator for
use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes
are provided.
Rev. A9, 11-Dec-01
13 (27)
Preliminary Information
T2801
PLL Principle
RF_IN
Programable counter PC
”– Main counter MC
”– Swallow counter SC
fVCO = fPD x (SMC x 32 + SSC)
fVCO
ext. loop filter
PA driver
Phase frequency
detector PD
fPD = 3.456 MHz
Charge
pump
Divider
by 2
VCO
Mixer
VCO
DAC
GF_DATA
Controlled phase shifting
Reference counter RC
REF_CLK
SRC
10.368MHz
13.824MHz
20.736MHz
3
4
6
Modulation
compensation MCC
Gaussian
filter GF
6.912 MHz
1.152 Mbit/s
PLL reference
Frequency
REF_CLK
TX_DATA
Baseband controller
Figure 3.
14 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
The following table shows the LO frequencies for RX and TX for the DECT band plus additional channels for the
extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported.
Table 1 LO frequencies
Mode
fIF/MHz
TX
RX
RX
110.592
112.320
Channel
fANT/MHz
fVCO/MHz
SMC
SSC
C9
1881.792
1881.792
34
1
C8
1883.520
1883.520
34
2
...
...
...
...
...
C1
1895.616
1895.616
34
9
C0
1897.344
1897.344
34
10
C10
1899.072
1899.072
34
11
C11
1900.800
1900.800
34
12
...
...
...
...
...
C29
1931.904
1931.904
34
30
C30
1933.632
1933.632
34
31
C9
1881.792
1771.200
32
1
C8
1883.520
1772.928
32
2
...
...
...
...
...
C1
1895.616
1785.024
32
9
C0
1897.344
1786.752
32
10
C10
1899.072
1788.480
32
11
C11
1900.800
1790.208
32
12
...
...
...
...
...
C29
1931.904
1821.312
32
30
C30
1933.632
1823.040
32
31
C9
1881.792
1769.472
32
0
C8
1883.520
1771.200
32
1
...
...
...
...
...
C1
1895.616
1783.296
32
8
C0
1897.344
1785.024
32
9
C10
1899.072
1786.752
32
10
C11
1900.800
1788.480
32
11
...
...
...
...
...
C29
1931.904
1819.584
32
29
C30
1933.632
1821.312
32
30
Formula
TX:
fANT = fVCO = 1.728 MHz × (32 × SMC + SSC)
RX:
fANT = 1.728 MHz × (32 × SMC + SSC) + fIF
Rev. A9, 11-Dec-01
15 (27)
Preliminary Information
T2801
Control Signals
Table 2
Signal
Function
I_CPSW
Controls the charge pump current
PU_REG
Activates AUX voltage regulator supplying the complete transceiver.
PU_VCO
Activates VCO voltage regulator which supplies only the VCO.
PU_RX/TX
Activates RX/TX switch.
PU_PLL
Activates PLL circuits: PC, PD, CP, RC
RX_ON
Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER
TX_ON
Activates TX circuits: TX-DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT.
Data Word 1
Bit D10
Activates GF in TX mode.
Data Word 1
Bit D9
Activates MCC in TX mode.
Table 3
Mode
PU_REG
PU_VCO
PU_RX/TX
PU_PLL
RX_ON
TX_ON
BB filter
Demodulator
IF amplifiers and RSSI
IR mixer
RX switch
TX switch
TX driver
Ramp generator
Programmable counter
Voltage-controlled oscillator
Gaussian filter
Phase detector / charge pump
Modulation compensation circuit
Reference counter
Typ. current consumption / mA @ VS = 3.2 V
TX Mode
1
1
1
1
0
1
RX Mode
1
1
1
1
1
0
RSSI Only
1
1
1
1
1
1
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
ON
54
85
80
16 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Serial Programming Bus
The transceiver is programmed by the 3-wire bus
(CLOCK, DATA and ENABLE).
many pulses arrived during enable-low condition. During
enable low condition the bus current is increased to speed
up the bus logic.
After setting enable signal to low condition, on the rising
edge of the clock signal, the data is transferred bit by bit
into the shift register, starting with the MSB-bit. After
enable returning to high condition the programmed
information is loaded into the addressed latches,
according to the addressbit condition (last bit). Additional
leading bits are ignored and there is no check made how
The programming of the transceiver is separated into two
data words. Data word 1 controls mainly the channel information together with settings, which are closely
related with the channel. Dataword 2 holds setup information, which is adjusted during production.
Data Word 1
MSB
LSB
Data bits
D22
D21
D20
D19
D18
RC
D17
D16
SC
D15
D14
MC
Address
bit
D13
D12
D11
D10
D9
VCOS
1
1
GF
MCC
D8
D7
D6
D5
GFCS
D4
D3
D2
D1
VCODAC
D0
CPCS
A0
1
Data Word 2
E10
E9
E8
E7
E6
E5
DEMODDAC
E4
E3
E2
E1
MCCS
E0
A0
TEST
0
Data Word 1 Programs
PLL Settings
SC (Swallow Counter)
With the Reference Counter bits D21 – D22
RC (Reference Counter)
D20
D19
D18
D17
D16
SSC
0
0
0
0
0
0
D22
D21
SRC
REF_CLK
0
0
0
0
1
1
0
0
3
10.368 MHz
0
0
0
1
0
2
0
1
4
13.824 MHz
...
1
0
6
20.736 MHz
With the Main Counter bits D14 – D15
1
1
1
0
1
29
1
1
1
1
0
30
1
1
1
1
1
31
MC (Main Counter)
D15
D14
SMC
0
0
32
0
1
33
1
0
34
1
1
35
...
With the Swallow Counter bits D16 – D20
Rev. A9, 11-Dec-01
17 (27)
Preliminary Information
T2801
VCO Select (RX/TX VCO)
VCO_DAC Adjustment
With bit D13
With bit D3 – D5
Used to switch between RX/TX VCO
D13
VCOS (VCO Select)
0
RX-VCO
Used to pretune the VCO frequency in case of production
tolerances of the device. Tuning voltage in locked condition should be around 1.8 V at room temperature. This
gives margin for ambient temperature changes.
1
TX-VCO
Pretune DAC Voltage
D5
D4
D3
fVCO/%
Gaussian Filter on/off
0
0
0
–5
With bit D10
0
0
1
...
GF is used only in TX mode
0
1
0
...
0
1
1
...
1
0
0
...
1
0
1
...
1
1
0
...
1
1
1
5
D10
GF (Gaussian Filter)
0
OFF
1
ON
Modulation Compensation Circuit on/off
With bit D9
CPCS Adjustment
MCC is used only in TX mode
With bit D0 – D2
D9
MCC (Modulation Compensation Circuit)
0
OFF
1
ON
Used to adjust the charge pump current. This can be used
to compensate the change of the tuning sensitivity over
frequency and device tolerances.
CPCS (Charge-Pump Current Settings)
GFCS Adjustment
With bit D6 – D8
Only in TX mode effective for setting the frequency deviation of the modulation
GFCS (Gaussian Filter Settings)
D8
D7
D6
GFCS
0
0
0
60%
0
0
1
70%
0
1
0
80%
0
1
1
90%
1
0
0
100%
1
0
1
110%
1
1
0
120%
1
1
1
130%
D2
D1
D0
CPCS
0
0
0
–4
0
0
1
–3
0
1
0
–2
0
1
1
–1
1
0
0
0
1
0
1
1
1
1
0
2
1
1
1
3
18 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Data Word 2 Programs
DEMODDAC Adjustment
TEST Mode Settings
With bits E6 – E10
Only in RX mode effective. Used to tune the demodulator
center frequency and allows to compensate tolerances of
external components and the T2801.
With bit E0 – E2 and D11
In normal operation Lock detect output is used. All other
settings are for test only.
D11 E2
Demod DAC Voltage
E10
E9
E8
E7
E6
fIFcenter %
0
0
0
0
0
–5
0
0
0
0
1
...
0
0
0
1
0
...
E1
E0
Signal at lock
detect output
CP mode
1
0
0
0
Lock detect
Active
0
0
0
1
RC out
Active
1
0
1
0
PC out
Active
X
0
1
1
MCCTEST:
Active
RC out divided by
2048
...
1
1
1
0
1
...
1
1
1
1
0
...
1
1
0
0
Lock detect
High imp.
1
1
1
1
1
5
0
1
0
1
RC out
High imp.
1
1
1
0
PC out
High imp.
X
1
1
1
GFTEST: RC out
divided by 2
High imp.
MCCS Adjustment
With bits E3 – E5
Only in TX mode effective. Adjusts the modulation compensation circuit for closed loop modulation. This
adjustment is done with a test sequence of a long stream
of ,1‘ – ,0‘. The correct setting is achieved, if the modulation is not affected by the PLL.
MCCS (Modulation Compensation Settings)
E5
E4
E3
MCCS
0
0
0
60%
0
0
1
70%
0
1
0
80%
0
1
1
90%
1
0
0
100%
1
0
1
110%
1
1
0
120%
1
1
1
130%
Rev. A9, 11-Dec-01
19 (27)
Preliminary Information
T2801
3-Wire Bus Protocol Timing Diagram
DATA
CLOCK
ENABLE
TC
TPER
TL
TS
TEC
TT
TH
16525
Figure 4.
Description
Symbol
Min. Value
Unit
TPER
125
ns
Set time data to clock
TS
60
ns
Hold time data to clock
TH
60
ns
Clock pulse width
TC
60
ns
Set time enable to clock
TL
200
ns
Hold time enable to data
TEC
0
ns
TT
250
ns
Clock period
Time between two protocols
TX DATA Timing
RefCLK
TX_DATA
TH
TS
Set-up time TX DATA
TS
10 ns
Hold time TX DATA
TH
10 ns
TS and TH must be considered for both (falling and
rising) edges of RefCLK when using REF_CLK =
10.368 MHz.
Figure 5. TX DATA timing
Absolute Maximum Ratings
All voltages refer to GND
Parameter
Symbol
Min.
Max.
Unit
VS_REG
3.2
4.7
V
Supply voltage regulator
Pin 10
Supply voltage
Pins 7, 12, 14, 33 and 42
VS
3.0
4.7
V
Logic input voltage
Pins 1, 2, 3, 38, 39, 44,
45, 46, 47 and 48
VIN
– 0.3
VS
V
150
C
150
C
Junction temperature
Tjmax
Storage temperature
Tstg
–40
Thermal Resistance
Parameter
Junction ambient
Symbol
Value
Unit
RthJA
t.b.d.
K/W
20 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Operating Range
Parameter
Supply voltage regulator
Pins 10
Supply voltage
Pins 7, 12, 14, 33 and 42
Ambient temperature
Symbol
Min.
Typ.
Max.
Unit
VS_REG
3.2
3.6
4.6
V
VS
3.0
3.0
4.6
V
Tamb
–25
+85
C
Max.
Unit
Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C
Parameter
IR mixer
Input impedance
Input matching
Image rejection ratio
DSB noise figure
Conversion gain
Input interception point
IF amplifier
Input impedance
Lower cut-off frequency
Upper cut-off frequency
Power gain
Bandwidth of external tank
circuit
Noise figure
RSSI
RSSI sensitivity
RSSI compression
RSSI dynamic range
RSSI resolution
RSSI rise time
RSSI fall time
Quiescent output current
Maximum output current
Test Conditions / Pins
Pins 29, 30, 40 and 41
Pins 29 and 30
Pins 29 and 30
Pins 40 and 41
Pins 40 and 41
Rload = 200 Ω
Pins 40 and 41
Pins 26, 27, 34 and 35
Pins 34 and 35
Pins 26 and 27
Pins 25, 34 and 35
at IF_IN1, IF_IN2
Pins 34 and 35
at IF_IN1, IF_IN2
Pins 34 and 35
Slope of the RSSI has to be
steady
Pin = 30 to 100 dBµV, Pin 25
Pin = 100 to 30 dBµV, Pin 25
@ Pin < 20 dBµV at IF_IN1,
IF_IN2 Pin 25
@ Pin = 100 dBµV at
IF_IN1, IF_IN2 Pin 25
Symbol
Min.
Zin
VSWRin
IRR
NFDSB=
NFSSB
Gconv
IIP3
Typ.
Ω
50
<2:1
20
10
dB
dB
11
–10
dB
dBm
90
130
85
10
Ω
MHz
MHz
dB
MHz
NF
9
dB
Pmin
20
dBµV
Pmax
100
dBµV
DR
Acc
80
±2
dB
dB
tr
tf
Iout
1
1
30
µs
µs
µA
Iout
150
µA
Zin
fl3dB
fu3dB
Gp
BW3dB
Rev. A9, 11-Dec-01
200
400
21 (27)
Preliminary Information
T2801
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C
Parameter
Test Conditions / Pins
FM demodulator, BB-Filter
Pins 19, 20, 23 and 24
Co-channel rejection ratio
@ Pin = –75 dBm at
IR-mixer input
Sensitivity
Quality factor of external
tank circuit approx. 20,
fres = FIF/2,
Pin 24
Amplitude of recovered
Nominal deviation of signal
signal
± 288 kHz, Pin 24
Corner frequency
Pin 23: C = 68 pF
Output voltage DC range
Pin 24
DAC for FM demodulator (internally connected)
DEMOD_DAC range
(see bus protocol E6 ... E10)
VCO
RX–VCO frequency range
VCOS = ‘0’
Bit D13
TX–VCO frequency range
VCOS = ‘1’
Bit D13
Tuning gain
Frequency control voltage
Pin 17
range
VCO_DAC range
(see bus protocol D3 ... D5)
PLL
Scaling factor prescaler
Scaling factor main counter
Scaling factor swallow
counter
External reference input
AC coupled sinewave
frequency
Pin 4
External reference input
voltage
Scaling factor reference
counter
Charge pump
Output current
Output current
Current scaling
Leakage current
AC coupled sinewave
Pin 4
Pin 13
VCP = VVS_CP / 2,
I_CPSW = ‘1’
Pin 48
VCP = VVS_CP / 2,
I_CPSW = ‘0’
Pin 48
ICP =
ICP_nom + CPCS * ICP_step
(see bus protocol D0 ... D2)
Symbol
Min.
Typ.
Max.
Unit
CCRR
10
dB
S
0.5
V/MHz
A
450
mVss
fc
680
kHz
V
VoutDC
1
±5
fIFcenter
fvco
fvco
Gtune
Vtune
Vs–1
%
1750
1860
1840
1950
40
0.4
2.8
∆fvco,DAC
±5
SPSC
SMC
SSC
32 / 33
32 / 33 / 34 / 35
0
31
fREF_CLK
10.368
13.824
20.736
VREF_CLK
MHz
MHz
MHz/V
V
%
MHz
MHz
MHz
50
250
mVRMS
SRC
3/4/6/8
ICP_nom
± 6.5
mA
ICP_nom
± 1.2
mA
ICP_step
0.2
mA
IL
± 100
pA
22 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C
Parameter
Test Conditions / Pins
Gaussian transmit filter (Gaussian shape B∗T = 0.5)
Tx data filter clock
12 taps in filter
Frequency deviation
Frequency deviation scaling GFFM = GFFM_nom * GFCS
(see bus protocol D6 ... D8)
Modulation compensation circuit
Oversampling
Digital sum variation
Current scaling factor
(see bus protocol E3 ... E5)
VCO switch and TX driver
Pin 32
Power gain
@ Pin = –40 dBm
Output impedance
Pin 32
Maximum output power
Pin 32
Gain compression
@ TX_RF_OUT, Pin 32
Output interception point
Pin 32
Ramp generator
Pins 36 and 37
Minimum output voltage
According to RAMP_SET
input
Maximum output voltage
According to RAMP_SET
input
Rise time
Cramp = 270 pF at Pin 37
Fall time
Cramp = 270 pF at Pin 37
Lock detect and test mode output
Pin 5
Lock detect output,
locked = ‘1’, unlocked = ‘0’
test mode output
test modes (see bus protocol
E0 ... E2)
Leakage current
VOH = 4.6 V
Saturation voltage
IOL = 0.5 mA
Auxiliary regulator
Pins 8, 9 and 10
Output voltage
VSREG = 3 V
Pin 8
Supply voltage rejection
VPin10 = VDC + 0.1 Vpp
fPin10 = 0.1 to 10 kHz
CPin8 = 100 nF
VCO regulator
Pins 14, 15 and 12
Output voltage
VSVCO = 3 V
Pin 15
3-wire bus
Clock
Symbol
fTXFCLK
GFFM_nom
GFCS
OVS
DSV
MCCS
Gp
Zout
Pmax
P1dB
OIP3
Min.
Typ.
Max.
Unit
130
MHz
kHz
%
85
130
%
13.824
±350
60
6
60
30
100
3
1
10
dB
Ω
dBm
dBm
dBm
Vmin
0.2
V
Vmax
1.95
V
tr
tf
5
5
µs
µs
0
LD
IL
VSL
5
0.4
µA
V
VREG
SVR
2.9
3.0
t.b.d.
3.1
V
dB
VREG_VCO
2.6
2.7
2.8
V
6.912
MHz
fClock
Rev. A9, 11-Dec-01
23 (27)
Preliminary Information
T2801
Electrical Characteristics (continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25°C
Parameter
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Logic input levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, I_CPSW)
Pins 1, 2, 3, 38, 39, 44, 47 and 48
High input level
= ‘1’
ViH
1.5
Low input level
= ‘0’
ViL
0.5
High input current
= ‘1’
IiH
–5
5
Low input current
= ‘0’
IiL
–5
5
Standby control
Pins 6, 45 and 46
Power up
PU_REG = ‘1‘
Pin 6
VPU_REG
PU_RX/TX = ‘1‘
Pin 45
VPU_RX/TX
2.0
PU_PLL = ‘1‘
Pin 46
VPU_PLL
High input level
Standby
PU_REG = ‘0‘
PU_RX/TX = ‘0‘
PU_PLL = ‘0‘
Low input level
Power up
PU_REG = ‘1‘
PU_RX/TX = ‘1‘
PU_PLL = ‘1‘
High input current
Standby
PU_xxxx = ‘0’
Low input current
Settling time
VS = 0 → active operation
Settling time
standby → active operation
Settling time
active operation → standby
Power supply
Total supply
pp y current
Standby current
Supply current CP
Pin 6
Pin 45
Pin 46
VPU_REG,OFF
VPU_RX/TX,OFF
VPU_PLL,OFF
VPU = 3 V
VPU = 5.5 V
Pin 6
Pin 45
IPU_REG
IPU_RX/TX
20
60
VPU = 3 V
VPU = 5.5 V
Pin 46
IPU_PLL
100
200
VPU = 0 V
Pin 6,
VPU = 0.5 V Pins 45, 46
Switched from
VS = 0 to VS = 3V
Switched from
PU = ‘0’ to PU = ‘1’
Switched from
PU = ‘1’ to standby
Pins 7, 10, 12, 14, 33 and 42
RX
RSSI only
TX
TX (MCC, GF active)
PU_RX/TX = GND
VVS_CP = 3 V, PLL in lock
condition
Pin 13
Unit
V
V
µA
µA
V
0.7
V
30
80
40
100
µA
µA
125
300
150
400
µA
µA
0.1
1
µA
µA
IPU,OFF
tsoa
< 10
µs
tssa
< 10
µs
tsas
<2
µs
IS
IS
IS
IS
IS
ICP
85
82
54
58
1
1
mA
mA
mA
mA
µA
µA
24 (27)
10
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Application Circuit
RAMP_OUT
TX_OUT RF_IN
33 pF
180 nH
100 nH
SAW
Filter
TFS
112B
33 pF
18 pF
15 pF
RSSI
68 pF
RAMP_OUT 36
IF_IN2 35
IF_IN1 34
VS_IF 33
TX_OUT 32
GND3 31
RF_IN2 30
RF_IN1 29
GND2 28
IF_TANK2 27
IF_TANK1 26
RSSI 25
270 nH
560 pF
RX_ON
TX_ON
PU_VCO
PU_RX/TX
PU_PLL
TX_DATA
I_CPSW
37
38
39
40
41
42
43
44
45
46
47
48
RAMP_SET
RX_ON
TX_ON
MIXER_OUT1
MIXER_OUT2
VS_MIXER
GND_PLL
PU_VCO
PU_RX/TX
PU_PLL
TX_DATA
I_CPSW
BB_OUT
BB_CF
REG_DEC
DAC_DEC
DEMOD_TANK2
DEMOD_TANK1
GND1
VTUNE
GND_VCO
VREG_VCO
VS_VCO
CP
T2801
1 CLOCK
2 DATA
3 ENABLE
4 REF_CLOCK
5 LD
6 PU_REG
7 VS_PLL
8 VREG
9 REG_CTRL
10 VS_REG
11 GND_CP
12 VS_CP
15 pF
CLOCK
DATA
ENABLE
REF_CLK
LD
PU_REG
24
23
22
21
20
19
18
17
16
15
14
13
BB_OUT
68 pF
2.2 nF
100 pF
tbd
tbd
22 nF
180Ω 150 nF
56 pF
470 nF
220 pF
4.7 nF
VCC
BC808
or similar
tantal
tantal
Figure 6. Application circuit
Rev. A9, 11-Dec-01
25 (27)
Preliminary Information
T2801
Package Information
26 (27)
Rev. A9, 11-Dec-01
Preliminary Information
T2801
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
8.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel products for any unintended or unauthorized application,
the buyer shall indemnify Atmel against all claims, costs, damages, and expenses, arising out of, directly or
indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A9, 11-Dec-01
27 (27)
Preliminary Information