TMP275 SBOS363A − JUNE 2006 − REVISED JUNE 2006 0.5°C Digital Out Temperature Sensor FEATURES D D D D DESCRIPTION 8 ADDRESSES DIGITAL OUTPUT: Two-Wire Serial Interface RESOLUTION: 9- to 12-Bits, User-Selectable ACCURACY: ±0.5°C (max) from +10°C to +85°C ±0.75°C (max) from +0°C to +100°C The TMP275 is a 0.5°C accurate, two-wire, serial output temperature sensor available in the MSOP-8 package. The TMP275 is capable of reading temperatures with a resolution of 0.0625°C. The TMP275 is SMBus-compatible and allows up to eight devices on one bus. It is ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. D LOW QUIESCENT CURRENT: 50µA, 0.1µA Standby D WIDE SUPPLY RANGE: 2.7V to 5.5V D SMALL MSOP-8 PACKAGE The TMP275 is specified for operation over a temperature range of −40°C to +125°C. APPLICATIONS Temperature D POWER-SUPPLY TEMPERATURE MONITORING SDA 1 D COMPUTER PERIPHERAL THERMAL PROTECTION D D D D D D D SCL NOTEBOOK COMPUTERS ALERT 8 Control Logic 2 CELL PHONES BATTERY MANAGEMENT Diode Temp. Sensor 3 7 ∆Σ A/D Converter V+ A0 Serial Interface 6 A1 OFFICE MACHINES THERMOSTAT CONTROLS GND 4 Config. and Temp. Register OSC ENVIRONMENTAL MONITORING AND HVAC ELECTROMECHANICAL DEVICE TEMPERATURE 5 A2 TMP275 TEMPERATURE ERROR AT 25_C TEMPERATURE ERROR vs TEMPERATURE 0.500 Population Temperature Error (_C) 0.375 0.250 0.125 0 −0.125 −0.250 −0.500 0.50 0.40 0.30 0.20 0.10 0.00 −0.10 −0.20 −0.30 −0.45 −0.50 −0.375 36 Units Shown −55 −35 −15 5 25 45 65 85 105 125 130 Temperature (_ C) Temperature Error (_C) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2006, Texas Instruments Incorporated ! ! www.ti.com "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ABSOLUTE MAXIMUM RATINGS(1) Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +130°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . . . . +150°C ESD Rating: Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 4000V Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . 1000V Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input voltage rating applies to all TMP275 input voltages. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR TMP275 MSOP-8 DGK PACKAGE MARKING T275 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PIN ASSIGNMENTS Top View 1 SCL 2 ALERT 3 GND 4 T275 SDA 8 V+ 7 A0 6 A1 5 A2 MSOP−8 NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram. 2 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 ELECTRICAL CHARACTERISTICS At TA = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted. TMP275 PARAMETER CONDITION MIN TYP MAX UNITS TEMPERATURE INPUT +125 °C +10°C to +85°C, V+ = 3.3V ±0.0625 ±0.5 °C 0°C to +100°C, V+ = 3.0V to 3.6V ±0.0625 ±0.75 °C −40°C to +125°C, V+ = 3.0V to 3.6V ±0.0625 ±1 °C +25°C to +100°C, V+ = 3.3V to 5.5V 0.2 ±1.5 °C Selectable +0.0625 °C 3 pF Range −40 Accuracy (Temperature Error) Resolution(1) DIGITAL INPUT/OUTPUT Input Capacitance Input Logic Levels: VIH VIL 0.7(V+) 6.0 −0.5 0.3(V+) V 1 µA 0V ≤ VIN ≤ 6V Leakage Input Current, IIN Input Voltage Hysteresis SCL and SDA Pins 500 V mV Output Logic Levels: VOL SDA VOL ALERT IOL = 3mA IOL = 4mA Resolution Conversion Time 0 0 0.15 0.4 0.15 0.4 Selectable 9 to 12 V V Bits 9-Bit 27.5 37.5 ms 10-Bit 55 75 ms 11-Bit 110 150 ms 12-Bit 220 300 ms 54 74 ms Timeout Time 25 POWER SUPPLY Operating Range Quiescent Current Shutdown Current 2.7 IQ ISD Serial Bus Inactive 50 5.5 V 85 µA µA Serial Bus Active, SCL Freq = 400kHz 100 Serial Bus Active, SCL Freq = 3.4MHz 410 Serial Bus Inactive 0.1 Serial Bus Active, SCL Freq = 400kHz 60 µA Serial Bus Active, SCL Freq = 3.4MHz 380 µA µA 3 µA TEMPERATURE RANGE Specified Range −40 +125 °C Operating Range −55 +127 °C Thermal Resistance MSOP-8 qJA 250 °C/W (1) Specified for 12-bit resolution. 3 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 TYPICAL CHARACTERISTICS At TA = +25°C and V+ = 5.0V, unless otherwise noted. SHUTDOWN CURRENT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE 1.0 85 0.9 75 0.8 0.7 0.6 V+ = 5V ISD (µA) IQ (µA) 65 55 0.5 0.4 0.3 45 0.2 V+ = 2.7V 0.1 35 0.0 Serial Bus Inactive −0.1 25 −55 −35 −15 5 25 45 65 85 105 −55 125 130 −35 −15 5 25 45 65 85 105 125 130 Temperature (_ C) Temperature (_ C) CONVERSION TIME vs TEMPERATURE TEMPERATURE ERROR vs TEMPERATURE 300 0.500 200 Temperature Error (_C) Conversion Time (ms) 0.375 V+ = 5V 250 V+ = 2.7V 150 −35 −15 5 25 45 65 85 105 0.125 0 −0.125 −0.250 −0.375 12−bit resolution. 100 −55 0.250 125 130 −0.500 36 Units Shown −55 −35 −15 5 25 45 65 85 105 Temperature (_ C) Temperature (_ C) QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE TEMPERATURE ERROR AT 25_ C 125 130 500 Hs MODE FAST MODE 450 400 Population 300 250 200 125_C 150 4 Temperature Error (_ C) 0.50 0.40 10M 0.30 1M 0.20 100k Frequency (Hz) 0.10 10k 0.00 1k −0.10 −55_C 0 −0.20 50 −0.30 100 −0.45 25_ C −0.50 IQ (µA) 350 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 APPLICATIONS INFORMATION Pointer Register The TMP275 is a digital temperature sensor that is optimal for thermal management and thermal protection applications. The TMP275 is Two-Wire and SMBus interface-compatible, and is specified over a temperature range of −40°C to +125°C. Temperature Register The TMP275 requires no external components for operation except for pull-up resistors on SCL, SDA, and ALERT, although a 0.1µF bypass capacitor is recommended, as shown in Figure 1. 2 SDA 1 7 A0 6 TMP275 SDA THIGH Register 0.1µF 8 SCL I/O Control Interface TLOW Register V+ To Two−Wire Controller SCL Configuration Register Figure 2. Internal Register Structure of the TMP275 A1 5 A2 3 ALERT (Output) 4 P1 P0 0 0 Temperature Register (READ Only) 0 1 Configuration Register (READ/WRITE) 1 0 1 1 TLOW Register (READ/WRITE) THIGH Register (READ/WRITE) NOTE: SCL, SDA, and ALERT pins require pull−up resistors. GND Figure 1. Typical Connections of the TMP275 The sensing device of the TMP275 is the chip itself. Thermal paths run through the package leads as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary thermal path. To maintain accuracy in applications requiring air or surface temperature measurement, care should be taken to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive will assist in achieving accurate surface temperature measurement. POINTER REGISTER Figure 2 shows the internal register structure of the TMP275. The 8-bit Pointer Register of the devices is used to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers should respond to a read or write command. Table 1 identifies the bits of the Pointer Register byte. Table 2 describes the pointer address of the registers available in the TMP275. Power-up reset value of P1/P0 is 00. P7 P6 P5 P4 P3 P2 0 0 0 0 0 0 P1 P0 Register Bits REGISTER Table 2. Pointer Addresses of the TMP275 TEMPERATURE REGISTER The Temperature Register of the TMP275 is a 12-bit, read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data, and are described in Table 3 and Table 4. Note that byte 1 is the most significant byte, followed by byte 2, the least significant byte. The first 12 bits are used to indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if that information is not needed. Data format for temperature is summarized in Table 5. Following power-up or reset, the Temperature Register will read 0°C until the first conversion is complete. D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 Table 3. Byte 1 of Temperature Register D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 Table 4. Byte 2 of Temperature Register Table 1. Pointer Register Byte 5 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 TEMPERATURE (°C) DIGITAL OUTPUT (BINARY) HEX 128 0111 1111 1111 7FF 127.9375 0111 1111 1111 7FF 100 0110 0100 0000 640 80 0101 0000 0000 500 75 0100 1011 0000 4B0 50 0011 0010 0000 320 25 0001 1001 0000 190 0.25 0000 0000 0100 004 0 0000 0000 0000 000 −0.25 1111 1111 1100 FFC −25 1110 0111 0000 E70 −55 1100 1001 0000 C90 POLARITY (POL) The Polarity Bit of the TMP275 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin will be active LOW, as shown in Figure 3. For POL = 1, the ALERT pin will be active HIGH, and the state of the ALERT pin is inverted. TL O W Table 5. Temperature Data Format The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration Register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits in the Temperature Register are used with the unused LSBs set to zero. CONFIGURATION REGISTER The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration Register for the TMP275 is shown in Table 6, followed by a breakdown of the register bits. The power-up/reset value of the Configuration Register is all bits equal to 0. BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 OS R1 R0 F1 F0 POL TM SD Table 6. Configuration Register Format SHUTDOWN MODE (SD) The Shutdown Mode of the TMP275 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to typically less than 0.1µA. Shutdown Mode is enabled when the SD bit is 1; the device will shut down once the current conversion is completed. When SD is equal to 0, the device will maintain a continuous conversion state. THERMOSTAT MODE (TM) The Thermostat Mode bit of the TMP275 indicates to the device whether to operate in Comparator Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the High and Low Limit Registers section. 6 T HIG H Measured Temperature TMP275 ALERT PIN (Comparator Mode) POL = 0 TMP275 ALERT PIN (Interrupt Mode) POL = 0 TMP275 ALERT PIN (Comparator Mode) POL = 1 TMP275 ALERT PIN (Interrupt Mode) POL = 1 Read Read Read Time Figure 3. Output Transfer Function Diagrams FAULT QUEUE (F1/F0) A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the THIGH and TLOW Registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of environmental noise. The fault queue requires consecutive fault measurements in order to trigger the alert function. Table 7 defines the number of measured faults that may be programmed to trigger an alert condition in the device. For THIGH and TLOW register format and byte order, see section High and Low Limit Registers. F1 F0 CONSECUTIVE FAULTS 0 0 1 0 1 2 1 0 4 1 1 6 Table 7. Fault Settings of the TMP275 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 CONVERTER RESOLUTION (R1/R0) The Converter Resolution Bits control the resolution of the internal Analog-to-Digital (A/D) converter. This control allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8 identifies the Resolution Bits and the relationship between resolution and conversion time. Both operational modes are represented in Figure 3. Table 9 and Table 10 describe the format for the THIGH and TLOW registers. Note that the most significant byte is sent first, followed by the least significant byte. Power-up reset values for THIGH and TLOW are: THIGH = 80°C and TLOW = 75°C The format of the data for THIGH and TLOW is the same as for the Temperature Register. R1 R0 RESOLUTION CONVERSION TIME (typical) 0 0 9 Bits (0.5°C) 27.5ms 0 1 10 Bits (0.25°C) 55ms 1 0 11 Bits (0.125°C) 1 1 12 Bits (0.0625°C) BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 H11 H10 H9 H8 H7 H6 H5 H4 110ms BYTE D7 D6 D5 D4 D3 D2 D1 D0 220ms 2 H3 H2 H1 H0 0 0 0 0 Table 8. Resolution of the TMP275 ONE-SHOT (OS) The TMP275 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a ‘1’ to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the completion of the single conversion. This mode is useful for reducing power consumption in the TMP275 when continuous temperature monitoring is not required. When the configuration register is read, the OS always reads zero. HIGH AND LOW LIMIT REGISTERS In Comparator Mode (TM = 0), the ALERT pin of the TMP275 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin remains active until the temperature falls below the indicated TLOW value for the same number of faults. In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs, or the device successfully responds to the SMBus Alert Response Address. The ALERT pin is also cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it only becomes active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin becomes active and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert Response Address. Once the ALERT pin is cleared, the above cycle repeats, with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This command also clears the state of the internal registers in the device, returning the device to Comparator Mode (TM = 0). Table 9. Bytes 1 and 2 of THIGH Register BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 L11 L10 L9 L8 L7 L6 L5 L4 BYTE D7 D6 D5 D4 D3 D2 D1 D0 2 L3 L2 L1 L0 0 0 0 0 Table 10. Bytes 1 and 2 of TLOW Register All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. SERIAL INTERFACE The TMP275 operates only as a slave device on the Two-Wire bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP275 supports the transmission protocol for fast (1kHz to 400kHz) and high-speed (1kHz to 3.4MHz) modes. All data bytes are transmitted MSB first. SERIAL BUS ADDRESS To communicate with the TMP275, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP275 features three address pins allowing up to eight devices to be connected per bus. Pin logic levels are described in Table 11. The address pins of the TMP275 are read after reset, at start of communication, or in response to a Two-Wire address acquire request. Following reading the state of the pins the address is latched to minimize power dissipation associated with detection. 7 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 A2 A1 A0 SLAVE ADDRESS 0 0 0 1001000 0 0 1 1001001 0 1 0 1001010 0 1 1 1001011 1 0 0 1001100 1 0 1 1001101 1 1 0 1001110 1 1 1 1001111 Table 11. Address Pins and Slave Addresses for the TMP275 Figure 6 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes, as the TMP275 remembers the Pointer Register value until it is changed by the next write operation. Note that register bytes are sent most-significant byte first, followed by the least significant byte. SLAVE MODE OPERATIONS The TMP275 can operate as a slave receiver or slave transmitter. Slave Receiver Mode: BUS OVERVIEW The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH is interpreted as a control signal. Once all data has been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH. WRITING/READING TO THE TMP275 Accessing a particular register on the TMP275 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the slave address byte with the R/W bit LOW. Every write operation to the TMP275 requires a value for the Pointer Register. (Refer to Figure 5.) When reading from the TMP275, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W bit LOW, followed by the Pointer Register Byte. No additional data is required. The master can then generate a START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See 8 The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP275 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP275 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The TMP275 acknowledges reception of each data byte. The master may terminate data transfer by generating a START or STOP condition. Slave Transmitter Mode: The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. SMBus ALERT FUNCTION The TMP275 supports the SMBus Alert function. When the TMP275 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP275 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP275 is active, the device acknowledges the SMBus Alert command and responds by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. This bit will be HIGH if the temperature is greater than or equal to THIGH. This bit will be LOW if the temperature is less than TLOW. Refer to Figure 7 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus Alert command determines which device will clear its ALERT status. If the TMP275 wins the arbitration, "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 TIMING DIAGRAMS its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP275 loses the arbitration, its ALERT pin will remain active. The TMP275 is Two-Wire and SMBus-compatible. Figure 4 to Figure 7 describe the various operations on the TMP275. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12. GENERAL CALL The TMP275 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device acknowledges the General Call address and responds to commands in the second byte. If the second byte is 00000100, the TMP275 latches the status of the address pins, but does not reset. If the second byte is 00000110, the TMP275 latches the status of the address pins and resets the internal registers to the power-up values. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. HIGH-SPEED MODE In order for the Two-Wire bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP275 will not acknowledge this byte, but will switch its input filters on SDA and SCL and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master transmits a Two-Wire slave address to initiate a data transfer operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP275 switches the input and output filters back to fast-mode operation. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. TIMEOUT FUNCTION The TMP275 resets the serial interface if either SCL or SDA is held LOW for 54ms (typ) between a START and STOP condition. The TMP275 releases the bus if it is pulled LOW and waits for a START condition. To avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL operating frequency. FAST MODE PARAMETER SCL Operating Frequency Bus Free Time Between STOP and START Condition Hold time after repeated START condition. After this period, the first clock is generated. Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time SCL Clock LOW Period SCL Clock HIGH Period Clock/Data Fall Time Clock/Data Rise Time for SCLK ≤ 100kHz HIGH-SPEED MODE UNITS MIN MAX MIN MAX f(SCL) t(BUF) 0.001 0.4 0.001 3.4 600 160 ns t(HDSTA) 100 100 ns t(SUSTA) t(SUSTO) t(HDDAT) 100 100 ns 100 100 ns 0 0 ns t(SUDAT) t(LOW) t(HIGH) tF tR tR MHz 100 10 ns 1300 160 ns 600 60 ns 300 160 ns 300 1000 160 ns ns Table 12. Timing Diagram Definitions for the TMP275 9 "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 TWO-WIRE TIMING DIAGRAMS t(LOW) tF tR t(HDSTA) SCL t(HDSTA) t(HIGH) t(SUSTO) t(SUSTA) t(HDDAT) t(SUDAT) SDA t(BU F ) P S S P Figure 4. Two-Wire Timing Diagram 1 9 9 1 … SCL SDA 1 0 0 1 A2 A1 A0 R/W Start By Master 0 0 0 0 0 0 P1 … P0 ACK By TMP275 ACK By TMP275 Frame 2 Pointer Register Byte Frame 1 Two−Wire Slave Address Byte 1 9 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 ACK By TMP275 Frame 3 Data Byte 1 ACK By TMP275 Frame 4 Data Byte 2 Figure 5. Two-Wire Timing Diagram for TMP275 Write Word Format 10 D0 Stop By Master "#$% www.ti.com SBOS363A − JUNE 2006 − REVISED JUNE 2006 1 9 1 9 … SCL SDA 1 0 0 1 0 0 0 R/W Start By Master 0 0 0 0 0 0 P1 … P0 ACK By TMP275 ACK By TMP275 Frame 1 Two−Wire Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 … SCL (Continued) SDA (Continued) 1 0 0 0 1 0 0 D7 R/W Start By Master D6 D5 D4 D3 D2 ACK By TMP275 … D0 From TMP275 Frame 3 Two−Wire Slave Address Byte 1 D1 ACK By Master Frame 4 Data Byte 1 Read Register 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 From TMP275 ACK By Master Stop By Master Frame 5 Data Byte 2 Read Register NOTE: Address Pins A0, A1, A2 = 0 Figure 6. Two-Wire Timing Diagram for Read Word Format ALERT 1 9 1 9 SCL SDA 0 Start By Master 0 0 1 1 0 0 R/W 1 0 0 1 0 ACK By TMP275 Frame 1 SMBus ALERT Response Address Byte 0 0 From TMP275 S ta tu s NACK By Master Stop By Master Frame 2 Slave Address Byte NOTE: Address Pins A0, A1, A2 = 0 Figure 7. Timing Diagram for SMBus ALERT 11 PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TMP275AIDGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP275AIDGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP275AIDGKT ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP275AIDGKTG4 ACTIVE MSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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