STMICROELECTRONICS STDS75DS2F

STDS75
Digital temperature sensor and thermal watchdog
Features
■
Measures temperatures from –55°C to +125°C
(–67°F to +257°F)
– ±2°C Accuracy from –25°C to +100°C
(max)
■
Low operating current: 125µA (typ)
■
No external components required
■
2-wire I2C/SMBus-compatible serial interface
– Selectable serial bus address allows
connection of up to eight devices on the
same bus
■
Thermometer resolution is user-configurable
from 9 (Default) to 12 bits (0.5°C to 0.0625°C)
■
9-bit conversion time is 150ms (max)
■
Programmable temperature threshold and
hysteresis set points
■
Wide power supply range-operating voltage
range: 2.7V to 5.5V
■
Pin- and software-compatible with DS75 (dropin replacement)
■
Power up defaults permit stand-alone
operation as thermostat
■
Shutdown mode to minimize power
consumption
■
Separate open drain output pin operates as an
interrupt or comparator/thermostat output (dual
purpose event pin)
■
Packages:
– SO8
– MSOP8 (TSSOP8)(a)
SO8 (M)
MSOP8
(TSSOP8) (DS)
a. Contact local ST sales office for availability
June 2007
Rev 5
1/37
www.st.com
1
Contents
STDS75
Contents
1
2
3
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Temperature sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.2
SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.3
OS/INT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.4
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.5
A2, A1, A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3.6
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2
Thermal alarm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Fault tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
Temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
2/37
1.3.1
Registers and register set formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1
Command/pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.3
Temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.4
Over-limit temperature register (TOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.5
Hysteresis temperature register (THYS) . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Power-up default conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STDS75
Contents
3.4.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
List of tables
STDS75
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
4/37
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Fault tolerance setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Relationship between temperature and digital output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command/pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register pointers selection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programmable resolution configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TOS and THYS register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
STDS75 serial bus slave addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO8 – 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 33
MSOP8 (TSSOP8) – 8-lead, thin shrink small package (3mm x 3mm) outline mechanical data
34
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STDS75
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Connections (SO8 and TSSOP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Typical 2-wire interface connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OS output temperature response diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical 2-byte READ from preset pointer location (e.g. temp - TOS, THYS) . . . . . . . . . . . . 24
Typical pointer set followed by an immediate READ for 2-byte register (e.g. temp). . . . . . 24
Typical 1-byte READ from the configuration register with preset pointer . . . . . . . . . . . . . . 24
Typical pointer set followed by an Immediate READ from the configuration register . . . . . 25
Configuration register WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TOS and THYS WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Temperature variation vs. voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SO8 – 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MSOP8 (TSSOP8) – 8-lead, thin shrink small package (3mm x 3mm) outline. . . . . . . . . . 34
5/37
Summary description
1
STDS75
Summary description
The STDS75 is a high-precision CMOS (Digital) temperature sensor IC with a Delta-Sigma
analog-to-digital (ADC) converter and an I2C-compatible serial digital interface (see Figure 1
on page 7). It is targeted for general applications such as personal computers, system
thermal management, electronics equipment, and industrial controllers, and is packaged in
the industry standard 8-lead TSSOP and SO8 packages (see Figure 2 on page 8).
The device contains a band gap temperature sensor and programmable 9-to 12-bit ADC
which monitor and digitize the temperature to a resolution up to 0.0625°C. The STDS75 is
typically accurate to (±3°C - max) over the full temperature measurement range of –55°C to
125°C with ±2°C accuracy in the –25°C to +100°C range. At power-up, the STDS75 defaults
to 9-bit resolution for software compatibility with the STLM75.
STDS75 is specified for operating at supply voltages from 2.7V to 5.5V. Operating at 3.3V,
the supply current is typically (125µA).
The on-board delta sigma analog-to-digital converter (ADC) converts the measured
temperature to a digital value that is calibrated in °C; for Fahrenheit applications a lookup
table or conversion routine is required.
The STDS75 is factory-calibrated and requires no external components to measure
temperature.
1.1
Serial communications
The STDS75 has a simple 2-wire I2C-compatible digital serial interface which allows the
user to access the data in the temperature register at any time. It communicates via the
serial interface with a master controller which operates at speeds up to 400kHz. Three pins
(A0, A1, and A2) are available for address selection, and enable the user to connect up to 8
devices on the same bus without address conflict.
In addition, the serial interface gives the user easy access to all STDS75 registers to
customize operation of the device.
1.2
Temperature sensor output
The STDS75 Temperature Sensor has a dedicated open drain Over-Limit Signal/Alert
(OS/INT/Alert) output which features a thermal Alarm function. This function provides a
user-programmable trip and turn-off temperature. It can operate in either of two selectable
modes:
●
Comparator mode, and
●
Interrupt mode.
At power-up the STDS75 comes up in 9-bit mode and immediately begins measuring the
temperature and converting the temperature to a digital value. The resolution of the digital
output data is user-configurable to 9, 10, 11, or 12 bits which correspond to temperature
increments of 0.5°C, 0.25°C, 0.125°C, and 0.0625°C, respectively.
6/37
STDS75
Summary description
The measured temperature value is compared with a temperature limit (which is stored in
the 16-bit (TOS) READ/WRITE register), and the hysteresis temperature (which is stored in
the 16-bit (THYS) READ/WRITE register). If the measured value exceeds these limits, the
OS/INT pin is activated (see Figure 3 on page 8).
Figure 1.
Logic diagram
VDD
SDA(1)
A0
SCL
A1
STDS75
O.S./INT(1)
A2
GND
AI11840
1. SDA and OS/INT are open drain.
Note:
See Pin descriptions on page 9 for details.
Table 1.
Signal names
Pin
Symbol/Name
Type/Direction
1
SDA(1)
Input/ Output
2
SCL
Input
(1)
Output
Description
Serial data input/output
Serial clock input
Over-limit signal/interrupt alert output
3
OS/INT
4
GND
Supply ground
5
A2
Input
Address2 input
6
A1
Input
Address1 input
7
A0
Input
Address0 input
8
VDD
Supply power
Ground
Supply voltage (2.7V to 5.5V)
1. SDA and OS/INT are open drain.
Note:
See Pin descriptions on page 9 for details.
7/37
Summary description
Figure 2.
STDS75
Connections (SO8 and TSSOP8)
SDA(1)
SCL
O.S./INT(1)
GND
1
2
3
4
8
7
6
5
VDD
A0
A1
A2
AI11841
1. SDA and OS/INT are open drain.
Note:
See Pin descriptions on page 9 for details.
Figure 3.
Functional block diagram
Temperature
Sensor and
Analog-to-Digital
Converter (ADC)
Σ-Δ
Pointer Register
Configuration Register
Temperature Register
THYS Set Point Register
VDD
Control and Logic
Comparator
TOS Set Point Register
SDA
A0
A1
O.S.
2-wire I2C Interface
A2
SCL
GND
AI11833a
8/37
STDS75
1.3
Summary description
Pin descriptions
See Figure 1 on page 7 and Table 1 on page 7 for a brief overview of the signals connected
to this device.
1.3.1
SDA (open drain)
This is the Serial Data Input/Output pin for the 2-wire serial communication port.
1.3.2
SCL
This is the Serial Clock Input pin for the 2-wire serial communication port.
1.3.3
OS/INT (open drain)
This is the Over-Limit Signal/Interrupt Alert Output pin. It is open drain, so it needs a pull-up
resistor.
Note:
The open drain thermostat output that indicates if the temperature has exceeded userprogrammable limits (Over/Under Temperature indicator).
1.3.4
GND
Ground; it is the reference for the power supply. It must be connected to system ground.
1.3.5
A2, A1, A0
A2, A1, and A0 are selectable address pins for the 3LSBs of the I2C interface address. They
can be set to VDD or GND to provide 8 unique address selections.
1.3.6
VDD
This is the supply voltage pin, and ranges from +2.7V to +5.5V.
9/37
Operation
2
STDS75
Operation
After each temperature measurement and analog-to-digital conversion, the STDS75 stores
the temperature as a 16-bit two’s complement number in the 2-byte temperature register
(see Table 8: Temperature register format). The most significant Bit (S, Bit 15) indicates if
the temperature is positive or negative:
●
for positive numbers S = 0, and
●
for negative numbers S = 1.
The most recently converted digital measurement can be read from the temperature register
at any time. Since temperature conversions are performed in the background, reading the
temperature register does not affect the operation in progress.
Bits 3 through 0 of the temperature register are hardwired to logic '0.' When the STDS75 is
configured for 12-bit resolution, the 12MSBs (Bits 15 through 4) of the temperature register
will contain temperature data. For 11-bit resolution, the 11MSBs (Bits 15 through 5) of the
temperature register will contain data, and Bit 4 will read out as logic '0.' For 10-bit
resolution, the 10MSbs (Bits 15 through 6) will contain data, and for 9-bit resolution the
9MSbs (Bits 15 through 7) will contain data and all unused LSBs will contain '0s.'
Table 3 on page 15 gives examples of 12-bit resolution digital output data and the
corresponding temperatures. The data is compared to the values in the TOS and THYS
registers, and then the OS/INT is updated based on the result of the comparison and the
operating mode. The number of TOS and THYS bits used during the thermostat comparison
is equal to the conversion resolution set by the FT1 and FT0 Bits in the Configuration
register. For example, if the resolution is 9 bits, only the 9MSbs of TOS and THYS will be used
by the thermostat comparator. The alarm fault tolerance is controlled by the FTI and FTO
Bits in the Configuration register. They are used to set up a fault queue. This prevents false
tripping of the OS/INT pin when the STDS75 is used in a noisy environment (see Table 2 on
page 14).
The active state of the OS/INT output can be changed via the Polarity (POL) Bit in the
Configuration register. The power-up default is active-low.
If the user does not wish to use the thermostat capabilities of the STDS75, the OS/INT
output should be left floating.
Note:
10/37
If the thermostat is not used, the TOS and THYS registers can be used for general storage of
system data.
STDS75
2.1
Operation
Applications information
STDS75 digital Temperature Sensors are optimal for thermal management and thermal
protection applications. They require no external components for operations except for pullup resistors on SCL, SDA, and OS/INT outputs. A 0.1µF bypass capacitor is recommended.
The sensing device of STDS75 is the chip itself. The typical interface connection for this
type of digital sensor is shown in Figure 4 on page 11.
Intended Applications include:
●
System Thermal Management
●
Computers/Disk Drivers
●
Electronics/Test Equipment
●
Power Supply Modules
●
Consumer Products
●
Battery Management
●
FAX/Printers Management
●
Automotive
Figure 4.
Typical 2-wire interface connection diagram
Pull-up
VDD
VDD
VDD
10kΩ
STDS75
O.S./INT(1) SCL
A0
10kΩ
0.1μF
Master
Device
SDA(1)
I2C Address = 1001000 (1001A2A1A0)
A1
A2
10kΩ
Pull-up
VDD
GND
AI11832
1. SDA and OS/INT are open drain.
11/37
Operation
2.2
STDS75
Thermal alarm function
The STDS75 thermal alarm function provides user-programmable thermostat capability and
allows the STDS75 to function as a standalone thermostat without using the serial interface.
The OS/INT output is the alarm output. This signal is an open drain output, and at power-up,
this pin is configured with active-low polarity by default.
2.3
Comparator mode
In Comparator mode, each time a temperature-to-digital (T-to-D) temperature conversion
occurs, the new digital temperature is compared to the value stored in the TOS and THYS
registers. If a fault tolerance number of consecutive temperature measurements are greater
than the value stored in the TOS register, the OS/INT output will be activated.
For example, if the FT1 and FT0 Bits are equal to “10” (fault tolerance = 4), four consecutive
temperature measurements must exceed TOS to activate the OS/INT output. Once the
OS/INT output is active, it will remain active until the first time the measured temperature
drops below the temperature stored in the THYS register.
When the thermostat is in comparator mode, the OS/INT can be programmed to operate
with any amount of hysteresis. The OS/INT output becomes active when the measured
temperature exceeds the TOS value a consecutive number of times as defined by the FT1
and FT0 fault tolerance (FT) Bits in the configuration register. The OS/INT then stays active
until the first time the temperature falls below the value stored in THYS. Putting the device
into shutdown mode does not clear OS/INT in comparator mode.
12/37
STDS75
2.4
Operation
Interrupt mode
In Interrupt mode, the OS/INT output first becomes active when the measured temperature
exceeds the TOS value a consecutive number of times equal to the FT value in the
Configuration register. Once activated, the OS/INT can only be cleared by either putting the
STDS75 into shutdown mode or by reading from any register (temperature, configuration,
TOS, or THYS) on the device. Once the OS/INT has been deactivated, it will only be
reactivated when the measured temperature falls below the THYS value a consecutive
number of times equal to the FT value. Figure 5 illustrates typical OS output temperature
response for STDS75 configured to have a fault tolerance of 2. The interrupt/clear process
is cyclical between TOS and THYS.
Figure 5.
OS output temperature response diagram
TOS
Temperature
THYS
Inactive
OS Output - Comparator mode
Active
Inactive
OS Output - Interrupt mode
(1)
(1)
(1)
Active
Conversions
AI12224b
1. This assumes that a READ has occurred.
Note:
The STDS75 is configured to have a fault tolerance of 2 in this example.
13/37
Operation
2.5
STDS75
Fault tolerance
For both Comparator and Interrupt modes, the alarm “fault tolerance” setting plays a role in
determining when the OS/INT output will be activated. Fault tolerance refers to the number
of consecutive times an error condition must be detected before the user is notified. Higher
fault tolerance settings can help eliminate false alarms caused by noise in the system. The
alarm fault tolerance is controlled by the bits (Bits 4 and 3) in the Configuration Register.
These bits can be used to set the fault tolerance to 1, 2, 4, or 6 as shown in Table 2. At
power-up, these bits both default to logic '0.'
Table 2.
2.6
Fault tolerance setting
FT1
FT0
STDS75 (Consecutive Faults)
0
0
1
0
1
2
1
0
4
1
1
6
Comments
Power-up default
Shutdown mode
For power-sensitive applications, the STDS75 offers a low-power shutdown mode. The SD
Bit in the Configuration register controls shutdown mode. When SD is changed to login '1,'
the conversion in progress will be completed and the result stored in the temperature
register, after which the STDS75 will go into a low-power standby state. The OS/INT output
will be cleared if the thermostat is operating in Interrupt mode and the OS/INT will remain
unchanged in Comparator mode. The 2-wire interface remains operational in shutdown
mode, and writing a '0' to the SD Bit returns the STDS75 to normal operation.
14/37
STDS75
2.7
Operation
Temperature data format
Table 3 shows the relationship between the output digital data and the external temperature
for 12-bit resolution.
Temperature data for Temperature, TOS and THYS Registers is represented by 9-bit, 10-bit,
11-bit, and 12-bit depending upon the resolution bits RC1, RC0 (Bits 6 and 5) in the
Configuration Register (see Table 7 on page 17). The default resolution is 9-bits.
The left-most hot in the output data stream controls temperature polarity information for
each conversion. If the Sign Bit is '0', the temperature is positive and of the Sign Bit is '1', the
temperature is negative.
Table 3.
Relationship between temperature and digital output
Temperature
Sign
Number of Bits used by
Conversion Resolution
9
10
11
12
12-Bit Resolution
0000
11- Bit Resolution
0
0000
0
0
0000
0
0
0
0000
10-Bit Resolution
9-Bit Resolution
Always
Zero
Digital
output
(HEX)
+125°C
0
111
1101
0
0
0
0
0000
7D00
+25.0625°C
0
001
1001
0
0
0
1
0000
1910
+10.125°C
0
000
1010
0
0
1
0
0000
0A20
+0.5°C
0
000
0000
1
0
0
0
0000
0080
0°C
0
000
0000
0
0
0
0
0000
0000
–0.5°C
1
111
1111
1
0
0
0
0000
FF80
–10.25°C
1
111
0101
1
1
1
0
0000
F5E0
–25.0625°C
1
110
0110
1
1
1
1
0000
E6F0
–55°C
1
100
1001
0
0
0
0
0000
C900
15/37
Functional description
3
STDS75
Functional description
The STDS75 registers have unique pointer designations which are defined in Table 5 on
page 16. Whenever any READ/WRITE operation to the STDS75 register is desired, the
user must “point” to the device register to be accessed.
All of these user-accessible registers can be accessed via the digital serial interface at
anytime (see Serial interface on page 20), and they include:
●
Command Register/Address Pointer Register
●
Configuration Register
●
Temperature Register
●
Over-Limit Signal Temperature Register (TOS)
●
Hysteresis Temperature Register (THYS)
3.1
Registers and register set formats
3.1.1
Command/pointer register
The Most Significant Bits (MSBs) of the Command Register must always be zero. Writing a
'1' into any of these bits will cause the current operation to be terminated (see Table 4).
The Command Register retains pointer information between operations. Therefore, this
register only needs to be updated once for consecutive READ operations from the same
register. All bits in the Command Register default to '0' at power-up.
Table 4.
Command/pointer register format
MSB
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
0
P1
P0
Pointer
Table 5.
Pointer
Value
(H)
P1
P0
Name
Description
00
0
0
TEMP
Temperature
Register
16
Read
only
N/A
01
0
1
CONF
Configuration
Register
8
R/W
00
02
1
0
THYS
Hysteresis
Register
16
R/W
4800
Default = 75°C
TOS
Overtemperature
Shutdown
5000
Set point for Overtemperature
Shutdown (TOS) limit
default = 80°C
03
16/37
Register pointers selection summary
1
1
Width Type
(Bits) (R/W)
16
R/W
Power-on
default
Comments
To store Measured
Temperature Data
STDS75
3.1.2
Functional description
Configuration register
The Configuration register is used to store the device settings such as Device Operation
mode, OS/INT Operation mode, OS/INT Polarity, and OS/INT Fault Queue.
The Configuration register allows the user to program various options such as conversion
resolution (see Table 7), thermostat fault tolerance, thermostat polarity, thermostat
operating mode, and shutdown mode. The user has READ/WRITE access to all of the bits
in the Configuration register except the MSB (Bit7), which is reserved as a “Read only” bit
(see Table 6). The entire register is volatile and thus powers-up in its default state only.
Table 6.
Configuration register format
MSB
LSB
Byte
Bit7
STDS75 Reserved
Default
Keys:
0
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RC1
RC0
FT1
FT0
POL
M
SD
0
0
0
0
0
0
0
SD =Shutdown Control Bit
FT1 =Fault Tolerance1 Bit
M =Thermostat Mode(1)
POL =Output
RC0 =Resolution Conversion0 Bit
Polarity(2)
RC1 =Resolution Conversion1 Bit
FT0 =Fault Tolerance0 Bit
Bit7 =Must be set to '0.' Reserved
1. Indicates Operation mode; 0 = Comparator mode, and 1 = Interrupt mode (see Comparator mode on
page 12 and Interrupt mode on page 13).
2. The OS/INT is active-low ('0').
Table 7.
Programmable resolution configurations
RC1
RC0
Resolution
Conversion Time
Remarks
0
0
9-bit
0.5°C
150ms
Default Resolution
0
1
10-bit
0.25°C
300ms
1
0
11-bit
0.125°C
600ms
1
1
12-bit
0.0625°C
1200ms
17/37
Functional description
3.1.3
STDS75
Temperature register
The Temperature register is a two-byte (16-bit) “Read only” register (see Table 8 on
page 18). Digital temperatures from the ADC are stored in the Temperature Register in
two’s complement format, and the contents of this register are updated each time the A/D
conversion is finished.
The user can read data from the Temperature Register at any time. When a A/D conversion
is completed, the new data is loaded into a comparator buffer to evaluate fault conditions,
and will update the Temperature Register if a read cycle is not ongoing. The STDS75 is
continuously evaluating fault conditions regardless of READ or WRITE activity on the bus. If
a READ is ongoing, the previous temperature will be read. The readable temperature will be
updated upon the completion of the next A/D conversion that is not masked by a read cycle.
Depending on the A/D conversion resolution, the 9-, 10-, 11- or 12-bit MSBs of the register
will contain temperature data. All unused bits following the digital temperature will be zero.
The MSB (Bit 15) of the Temperature Register denotes whether the temperature data is
positive or negative. A '0' in Bit 15 is positive and a '1' is negative.
Table 8.
Temperature register format
Bytes
MS Byte
MSB
LS Byte
THSB
TLSB
LSB
Bits
15
STDS75
Keys:
SB
14
13
12
11
10
9
8
TMSB TD TD TD TD TD TD
7
9-bit
LSB
6
5
4
3 2 1
0
10-bit 11-bit 12-bit
0 0 0
LSB LSB LSB
0
SB =Two’s complement Sign Bit
TMSB =Temperature MSB
TLSB =Temperature LSB
TD =Temperature Data
Note:
These are comparable formats to the DS75 and LM75.
3.1.4
Over-limit temperature register (TOS)
The TOS Register is a two-byte (16-bit) READ/WRITE register that stores the userprogrammable upper trip-point temperature for the thermal alarm in two’s complement
format (see Table 9 on page 19). This register defaults to 80°C at power-up (i.e., 0101 0000
0000 0000).
The format of the TOS Register is identical to that of the Temperature Register. The 4 LSBs
of the TOS Register are hardwired to zero, so data written to these register bits will be
ignored. The MSB position contains the sign bit for the digital temperature and Bit14
contains the temperature MSB.
The resolution setting for the A/D conversion determines how many bits of the TOS Register
are used by the thermal alarm. For example, for 9-bit conversions, the trip-point temperature
is defined by the 9 MSBs of the TOS register, and all remaining bits are “Don’t cares.”
18/37
STDS75
3.1.5
Functional description
Hysteresis temperature register (THYS)
THYS Register is a two-byte (16-bit) READ/WRITE register that stores the userprogrammable lower trip-point temperature for the thermal alarm in two’s complement
format (see Table 9). This register defaults to 75°C at power-up (i.e., 0100 1011 0000
0000).
The format of this register is the same as that of the Temperature Register. The 4 LSBs of
the THYS Register are hardwired to zero, so data written to these bits is ignored. The MSB
position contains the sign bit for the digital temperature and Bit14 contains the temperature
MSB.
The resolution setting for the A/D conversion determines how many bits of the THYS
Register are used by the thermal alarm. For example, for 9-bit conversions, the hysteresis
temperature is defined by the 9 MSBs of the THYS Register, and all remaining bits are “Don’t
cares.”
Table 9.
TOS and THYS register format
Bytes
MS Byte
MSB
LS Byte
THSB
TLSB
LSB
Bits
15
STDS75
Keys:
SB
14
13
12
11
10
9
8
TMSB TD TD TD TD TD TD
7
9-bit
LSB
6
5
4
3 2 1
0
10-bit 11-bit 12-bit
0 0 0
LSB LSB LSB
0
SB =Two’s complement Sign Bit
TMSB =Temperature MSB
TLSB =Temperature LSB
TD =Temperature Data
Note:
These are comparable formats to the DS75 and LM75.
3.2
Power-up default conditions
The STDS75 always powers up in the following default states:
Note:
●
Thermostat mode = Comparator Mode
●
Polarity = Active-low
●
Fault tolerance = 1 fault (i.e., relevant bits set to '0' in the Configuration register)
●
TOS = 80°C
●
THYS = 75°C
●
Register pointer = 00 (Temperature register)
●
Conversion resolution = 9-bit (i.e., RC0 = 0 and RC1 = 0 in the Configuration register;
see Table 7 on page 17)
After power-up these conditions can be reprogrammed via the serial interface.
19/37
Functional description
3.3
STDS75
Serial interface
Writing to and reading from the STDS75 registers is accomplished via the two-wire serial
interface protocol which requires that one device on the bus initiates and controls all READ
and WRITE operations. This device is called the “master” device. The master device also
generates the SCL signal which provides the clock signal for all other devices on the bus.
These other devices on the bus are called “slave” devices. The STDS75 is a slave device
(see Table 10). Both the master and slave devices can send and receive data on the bus.
During operations, one data bit is transmitted per clock cycle. All operations follow a
repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data
followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device.
Note:
There are no unused clock cycles during any operation, so there must not be any breaks in
the data stream and ACKs/NACKs during data transfers. Conversely, having too few clock
cycles can lead to incorrect operation if an inadvertent 8-bit READ from a 16-bit register
occurs.
Table 10.
STDS75 serial bus slave addresses
MSB
3.4
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
0
0
1
A2
A1
A0
R/W
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
●
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is High.
●
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined (see Figure 6 on page 21):
3.4.1
Bus not busy
Both data and clock lines remain High.
3.4.2
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the
START condition.
3.4.3
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the
STOP condition.
20/37
STDS75
3.4.4
Functional description
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Figure 6.
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI00587
21/37
Functional description
3.4.5
STDS75
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse (see Figure 7). A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
Figure 7.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
22/37
STDS75
3.5
Functional description
READ mode
In this mode the master reads the STDS75 slave after setting the slave address (see
Figure 8). Following the WRITE mode Control Bit (R/W=0) and the Acknowledge Bit, the
word address 'An' is written to the on-chip address pointer.
There are two READ modes:
Preset pointer locations (e.g. Temperature, TOS and THYS registers), and
●
Pointer setting (the pointer has to be set for the register that is to be read).
The Temperature register pointer is usually the default pointer.
These modes are shown in the READ mode typical timing diagrams (see Figure 9,
Figure 10, and Figure 11 on page 24).
Slave address location
R/W
START
A
SLAVE ADDRESS
1
LSB
Figure 8.
MSB
Note:
●
0
0
1
A2 A1 A0
AI12226
23/37
Functional description
Figure 9.
STDS75
Typical 2-byte READ from preset pointer location (e.g. temp - TOS, THYS)
1
9
1
0
0
Start
by
Master
1
A2 A1 A0
1
R
9
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Most Significant Data Byte
Address Byte
9
Least Significant Data Byte
ACK
by
STDS75
ACK
by
Master
Stop
Cond.
by
No ACK
Master
by
Master
AI12281b
Figure 10. Typical pointer set followed by an immediate READ for 2-byte register (e.g. temp)
1
9
1
0
0
Start
by
Master
1
A2 A1 A0
1
W
9
0
0
0
0
0
ACK
by
STDS75
1
ACK
by
STDS75
9
0
0
Repeat
Start
by
Master
1
D1 D0
Pointer Byte
Address Byte
1
0
A2 A1 A0
1
R
9
D7 D6 D5 D4 D3 D2 D1 D0
1
D7 D6 D5 D4 D3 D2 D1 D0
Most Significant Data Byte
Address Byte
Least Significant Data Byte
ACK
by
STDS75
9
ACK
by
Master
Stop
Cond.
No ACK
by
by
Master
Master
AI12282b
Figure 11. Typical 1-byte READ from the configuration register with preset pointer
1
1
Start
by
Master
9
0
0
1
A2 A1 A0
R
1
9
D7 D6 D5 D4 D3 D2 D1 D0
Data Byte
Address Byte
ACK
by
STDS75
Stop
Cond.
by
No ACK
Master
by
Master
AI12283b
24/37
STDS75
3.6
Functional description
WRITE mode
In this mode the master transmitter transmits to the STDS75 slave receiver. Bus protocol is
shown in Figure 12. Following the START condition and slave address, a logic '0' (R/W = 0)
is placed on the bus and indicates to the addressed device that word address will follow and
is to be written to the on-chip address pointer.
These modes are shown in the WRITE mode typical timing diagrams (see Figure 12, and
Figure 13, and Figure 14 on page 26).
Figure 12. Typical pointer set followed by an Immediate READ from the
configuration register
1
9
1
0
0
Start
by
Master
1
A2 A1 A0
1
W
9
0
0
0
0
0
0
Pointer Byte
Address Byte
ACK
by
STDS75
ACK
by
STDS75
1
9
1
0
0
Repeat
Start
by
Master
1
D1 D0
1
A2 A1 A0 R/W
9
D7 D6 D5 D4 D3 D2 D1 D0
Address Byte
Stop
Cond.
No ACK
by
by
Master
STDS75
Data Byte
ACK
by
STDS75
AI12279b
Figure 13. Configuration register WRITE
1
1
Start
by
Master
9
0
0
1
A2 A1 A0
W
1
0
9
0
0
0
0
0
D1 D0
1
0
Pointer Byte
Address Byte
ACK
by
STDS75
9
0
0
D4 D3 D2 D1 D0
Configuration Byte
ACK
by
STDS75
ACK
by
STDS75
Stop
Cond.
by
Master
AI12280b
25/37
Functional description
STDS75
Figure 14. TOS and THYS WRITE
1
9
1
0
Start
by
Master
0
1
A2 A1 A0
1
W
9
0
0
0
0
0
0
D1 D0
Pointer Byte
Address Byte
ACK
by
STDS75
ACK
by
STDS75
1
9
D7 D6 D5 D4 D3 D2 D1 D0
1
9
D7 D6 D5 D4 D3 D2 D1 D0
Most Significant Data Byte
Least Significant Data Byte
ACK
by
STDS75
ACK
by
STDS75
Stop
Cond.
by
Master
AI12284b
26/37
STDS75
Typical operating characteristics
Figure 15. Temperature variation vs. voltage
140
120
100
Temperature (°C)
4
Typical operating characteristics
80
–20
60
0.5
40
85
20
110
0
125
–20
–40
–60
2
3
4
5
6
Voltage (V)
AI12258
27/37
Maximum rating
5
STDS75
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 11.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
TSTG
Storage temperature (VCC off, VBAT off)
–60 to 150
°C
TSLD(1)
Lead solder temperature for 10 seconds
260
°C
VCC +0.5
V
VIO
Input or output voltage
VDD
Supply voltage
7.0
V
VOUT
Output voltage
VDD + 0.5
V
IO
Output current
10
mA
PD
Power dissipation
320
mW
1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C
for between 90 to 150 seconds).
28/37
STDS75
6
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 12. Operating and AC Measurement Conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 12.
Operating and AC measurement conditions
Parameter
STDS75
Unit
VDD/VBAT supply voltage
2.7 to 5.5
V
Ambient operating temperature (TA)
–55 to 125
°C
≤5
ns
Input pulse voltages
0.2 to 0.8VCC
V
Input and output timing reference voltages
0.3 to 0.7VCC
V
Input rise and fall times
29/37
DC and AC parameters
Table 13.
Sym
VDD
IDD
IDD1
STDS75
DC and AC characteristics
Description
Supply voltage
Min
TA = –55 to +125°C
2.7
5.5
V
150
µA
VDD supply current,
communication only
TA = 25°C
70
100
µA
Standby supply current,
serial port inactive
TA =25°C
1.0
µA
–25°C < TA < 100
±2.0
°C
–55°C < TA < 125
±3.0
°C
12-bit Temperature
Data
0.0625
°C
12
bits
9
150
ms
10
300
ms
11
600
ms
12
1200
ms
9
Conversion time
Over-temperature
shutdown
THYS Hysteresis
Default Value
80
°C
Default Value
75
°C
OS/INT saturation voltage
(VDD = 5V)
4mA sink current
VIH
Input logic high
Digital pins (SCL,
SDA, A2-A0)
VIL
Input logic low
Digital pins
VOL2 Output logic (SDA)
CIN
Unit
125
V
VOL1
Max
VDD = 3.3V
Resolution
TOS
Typ(2)
VDD supply current, active
temperature conversions
Accuracy for
corresponding range 2.7V
≤ VDD ≤ 5.5V
tCON
Test Condition(1)
0.5
V
0.5 x VDD
VDD + 0.5
V
-0.45
0.3 x VDD
V
0.4
V
IOL2=3mA
Capacitance
5
1. Valid for ambient operating temperature: TA = –55 to 125°C; VDD = 2.7V to 5.5V (except where noted).
2. Typical number taken at VDD=3V, TA=25°
30/37
pF
STDS75
DC and AC parameters
Figure 16. Bus timing requirements sequence
SDA
tBUF
tHD:STA
tR
tHD:STA
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
tSU:STO
SR
P
AI00589
Table 14.
AC characteristics
Parameter(1)
Sym
fSCL
SCL clock frequency
tBUF
Time the bus must be free before a new transmission can start
tF
tHD:DAT(2)
Min
Max
Unit
0
400
kHz
1.3
SDA and SCL fall time
300
ns
0
µs
START condition hold time (after this period the first clock pulse is
generated)
600
ns
tHIGH
Clock high period
600
ns
tLOW
Clock low period
1.3
µs
tHD:STA
tR
Data hold time
µs
SDA and SCL rise time
300
ns
tSU:DAT
Data setup time
100
ns
tSU:STA
START condition setup time (only relevant for a repeated start
condition)
600
ns
tSU:STO
STOP condition setup time
600
ns
1. Valid for ambient operating temperature: TA = –55 to 125°C; VDD = 2.7V to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling
edge of SCL.
31/37
Package mechanical data
7
STDS75
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
32/37
STDS75
Package mechanical data
Figure 17. SO8 – 8-lead plastic small package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
Note:
Drawing is not to scale.
Table 15.
SO8 – 8-lead plastic small outline package mechanical data
mm
Symb
Typ
Min
Max
1.75
0.10
0.25
A
A1
inches
Typ
Min
Max
0.069
0.004
0.010
A2
1.25
b
0.28
0.48
0.011
c
0.17
0.23
0.007
ccc
0.049
0.10
0.019
0.009
0.004
D
4.90
4.80
5.00
0.193
0.189
0.197
E
6.00
5.80
6.20
0.236
0.228
0.244
E1
3.90
3.80
4.00
0.154
0.150
0.157
e
1.27
0.25
0.50
0.010
0.020
h
0.050
k
0°
8°
0°
8°
L
0.40
0.127
0.016
0.050
L1
1.04
0.041
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Package mechanical data
STDS75
Figure 18. MSOP8 (TSSOP8) – 8-lead, thin shrink small package (3mm x 3mm) outline
D
8
5
c
E1
1
E
4
k
A1
A
L
L2
A2
L1
ccc
b
e
E3_ME
Note:
Drawing is not to scale.
Table 16.
MSOP8 (TSSOP8) – 8-lead, thin shrink small package (3mm x 3mm) outline
mechanical data
mm
inches
Sym
Typ
Min
A
0.00
0.15
0.75
0.95
b
0.22
c
A2
Typ
Min
1.10
A1
0.85
Max
0.043
0.000
0.006
0.030
0.037
0.40
0.009
0.016
0.08
0.23
0.003
0.009
0.034
D
3.00
2.80
3.20
0.118
0.110
0.126
E
4.90
4.65
5.15
0.193
0.183
0.203
E1
3.00
2.80
3.10
0.118
0.110
0.122
e
0.65
L
0.60
0.016
0.032
L1
0.95
0.037
L2
0.25
0.010
0°
8°
k
ccc
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Max
0.026
0.40
0°
0.80
8°
0.10
0.024
0.004
STDS75
8
Part numbering
Part numbering
Table 17.
Ordering information scheme
Example:
STDS75
M
2
F
Device type
STDS75
Package
M = SO8
DS = MSOP8 (TSSOP8)(1)
Temperature range
2 = –55 to 125°C
Shipping method
F = ECOPACK package, Tape & Reel
E=ECOPACK package, Tube
1. Contact ST sales office for availability
For other options, or for more information on any aspect of this device, please contact the
ST Sales Office nearest you.
35/37
Revision history
9
STDS75
Revision history
Table 18.
36/37
Document revision history
Date
Revision
Changes
28-Nov-2005
1
Initial release.
08-May-06
2
Update characteristics, diagrams (Figure 3, 4, 9, 10, 11,
12, 13, 14, 15; Table 1, 2, 6, 9, 12, 13, 14)
22-Jan-2007
3
Updates to parameters, package mechanical information
(Figure 17,Table 15,Figure 18, Table 16) and part
numbering (Table 17).
01-Mar-2007
4
Updated cover page (package information); Section 2:
Operation; Table 13; package mechanical data (Figure 18
and Table 16); and part numbering (Table 17).
06-Jun-2007
5
Updated cover page, document status upgraded to full
datasheet.
STDS75
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