PHILIPS IP4221CZ6-S

IP4221CZ6-S
Dual USB 2.0 integrated quad with ESD protection to
IEC 61000-4-2, level 4 (Pb-free)
Rev. 01 — 29 April 2008
Product data sheet
1. Product profile
1.1 General description
The IP4221CZ6-S is designed to protect Input/Output (I/O) ports that are sensitive to
capacitive load, such as USB 2.0, Ethernet and DVI from destruction by ElectroStatic
Discharge (ESD). It provides protection to downstream signal and supply components
from ESD voltages as high as ±8 kV (contact discharge).
The IP4221CZ6-S incorporates four pairs of ultra-low capacitance rail-to-rail diodes plus a
Zener diode. The rail-to-rail diodes are connected to the Zener diode which allows ESD
protection to be independent of supply voltage. The IP4221CZ6-S is fabricated using thin
film-on-silicon technology integrating four ultra-low capacitance rail-to-rail ESD protection
diodes in a miniature 6-terminal SOT886 package.
1.2 Features
n
n
n
n
n
Pb-free and RoHS compliant
ESD protection compliant to IEC 61000-4-2 level 4, ±8 kV contact discharge
Four ultra-low input capacitance (1 pF typical) rail-to-rail ESD protection diodes
Low voltage clamping due to integrated Zener diode
Small 6-terminal SOT886 package
1.3 Applications
n General-purpose downstream ESD protection high frequency analog signals and
high-speed serial data transmission for ports inside:
u Cellular and PCS mobile handsets
u PC/notebook USB 2.0/IEEE 1394 ports
u DVI/HDMI interfaces
u Cordless telephones
u Wireless data (WAN/LAN) systems
u PDAs
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
2. Pinning information
Table 1.
Pinning
Pin
Description
Simplified outline
1
ESD protection I/O 1
2
ground (GND)
3
ESD protection I/O 2
4
ESD protection I/O 3
5
supply voltage (VCC)
6
ESD protection I/O 4
1
2
3
6
5
bottom view
4
Graphic symbol
6
5
4
1
2
3
001aag273
3. Ordering information
Table 2.
Ordering information
Type number
IP4221CZ6-S
Package
Name
Description
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
Version
4. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VI
input voltage
Vesd
electrostatic discharge
voltage
Tstg
Conditions
Min
Max
Unit
−0.5
+5.5
V
contact discharge
−8
+8
kV
air discharge
−15
+15
kV
−55
+125
°C
all pins;
IEC 61000-4-2; level 4
storage temperature
5. Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Parameter
Tamb
ambient temperature
Conditions
IP4221CZ6-S_1
Product data sheet
Min
Max
Unit
−40
+85
°C
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
2 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
6. Characteristics
Table 5.
Electrical Characteristics
Tamb = 25 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
-
1.0
pF
C(I/O-GND)
input/output to ground
capacitance
VI = 0 V; f = 1 MHz; VCC = 3 V
[1]
ILR
reverse leakage current
VI = 3 V
[1]
-
-
100
nA
-
20
-
pF
6
-
9
V
-
0.7
-
V
Csup
supply pin to ground
capacitance
VI = 0 V; f = 1 MHz; VCC = 3 V
[2]
VBR
breakdown voltage
Zener diode; II = 1 mA
[2]
VF
forward voltage
[1]
Measured from pins 1, 3, 4 and 6 to ground.
[2]
Measured from pin 5 to pin 2.
7. Application information
7.1 Universal serial bus 1.1 and 2.0 protection
The IP4221CZ6-S is optimized to protect two USB 2.0 ports against ESD.
VBUS
DAT+
DAT+
USB
DAT− PORT
GND
DAT−
USB 2.0/
IEEE 1394
CONTROLLER
1
6
2
5
3
4
VBUS
DAT+
DAT−
DAT+
USB
DAT− PORT
GND
001aah371
Each device is capable of protecting both USB data lines as well as VBUS supply.
Fig 1.
Typical application for USB ESD protection
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
3 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
7.2 Universal serial bus OTG protection
The IP4221CZ6-S is optimized to protect USB 2.0 ports with or without OTG functionality
against ESD.
VBUS
DAT+
DAT−
to phone
USB OTG
RECEPTACLE
CARKIT
ID
GND
Shld GND
mini B receptacle
mini A receptacle
1
6
2
5
3
4
001aag051
The device is capable of protecting the USB data lines as well as VBUS supply and the ID pin.
Fig 2.
Typical application for USB OTG ESD protection
7.3 Universal SIM-card protection
The IP4221CZ6-S protects the SIM-card interfaces against ESD.
I/O
CLOCK
RESET
SIM
VCC
GND
1
6
2
5
3
4
001aag052
This device also protects VCC.
Fig 3.
Typical application for universal SIM-card ESD protection
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
4 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
7.4 IEEE 1394a/b protection
The IP4221CZ6-S is optimized to protect both the IEEE 1394 physical layer and the
IEEE 1394 connector ports against ESD.
TPBIAS
Shld1
1 µF
BUS PWR
PWR
56 Ω
1
56 Ω
TPA+
TPA+
TPA−
TPA−
IEEE 1394
PHYSICAL
LAYER
7
1
6
5
6
1394
CONNECTOR
2
5
3
4
TPB+
TPB+
TPB−
TPB−
GND
56 Ω
56 Ω
Shld2
220 pF
5 kΩ
1 nF
10 nF
4
3
2
8
1 MΩ
001aag050
Fig 4.
Typical application for IEEE 1394a/b ESD protection
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
5 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
7.5 Gigabit Ethernet transceiver protection
The IP4221CZ6-S protects the gigabit Ethernet transceiver against ESD.
TPOPA
R1
C1
C5
C2
C6
TPONA
1
6
2
5
3
4
TPOPB
R2
TPONB
GIGABIT
ETHERNET
TPOPC
TRANSCEIVER
QUAD
TRANSFORMER
R3
RJ45
C3
C7
C4
C8
TPONC
1
6
2
5
3
4
TPOPD
R4
TPOND
001aag053
Fig 5.
Typical application for gigabit Ethernet transceiver ESD protection
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
6 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
7.6 Universal microSD/TransFlash and SD-memory card protection
The IP4221CZ6-S protects each data line of the microSD/TransFlash device against ESD.
DAT0
DAT1
DAT2
DAT3/CD
TRANSFLASH
CMD
CLK
VCC
GND
1
6
1
6
2
5
2
5
3
4
3
4
001aag054
Fig 6.
Typical application for universal microSD/TransFlash and SD-memory card ESD
protection
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
7 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
8. Package outline
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
e1
4
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
Fig 7.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Package outline SOT886 (XSON6)
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
8 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
9. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
9.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
9.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
9.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
9 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
9.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 6 and 7
Table 6.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 7.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
10 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 8.
Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
10. Abbreviations
Table 8.
Abbreviations
Acronym
Description
DVI
Digital Video Interface
ESD
ElectroStatic Discharge
HDMI
High Definition Multimedia interface
LAN
Local Area Network
OTG
On-The-Go
PCS
Personal Computing System
PDA
Personal Digital Assistant
RoHS
Restriction of the use of certain Hazardous substances
SIM
Subscriber Identity Module
USB
Universal Serial Bus
WAN
Wide Area Network
11. Revision history
Table 9.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
IP4221CZ6-S_1
20080429
Product data sheet
-
-
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
11 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
12. Legal information
12.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
IP4221CZ6-S_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 29 April 2008
12 of 13
IP4221CZ6-S
NXP Semiconductors
Dual USB 2.0 integrated quad with ESD protection (Pb-free)
14. Contents
1
1.1
1.2
1.3
2
3
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
8
9
9.1
9.2
9.3
9.4
10
11
12
12.1
12.2
12.3
12.4
13
14
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Recommended operating conditions. . . . . . . . 2
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Application information. . . . . . . . . . . . . . . . . . . 3
Universal serial bus 1.1 and 2.0 protection. . . . 3
Universal serial bus OTG protection . . . . . . . . . 4
Universal SIM-card protection . . . . . . . . . . . . . 4
IEEE 1394a/b protection. . . . . . . . . . . . . . . . . . 5
Gigabit Ethernet transceiver protection . . . . . . 6
Universal microSD/TransFlash and
SD-memory card protection . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Soldering of SMD packages . . . . . . . . . . . . . . . 9
Introduction to soldering . . . . . . . . . . . . . . . . . . 9
Wave and reflow soldering . . . . . . . . . . . . . . . . 9
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . 9
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 29 April 2008
Document identifier: IP4221CZ6-S_1