VISHAY DG507AAK/883

DG506A_MIL/507A_MIL
Vishay Siliconix
Single 16-Ch/Differential 8-Ch CMOS Analog Multiplexers
(Obsolete for non-hermetic. Use DG406/407 as pin-for-pin replacements.)
Low On-Resistance: 240 TTL and CMOS Logic Compatible
Low Power: 30 mW
Break-Before-Make Switching
44-V Power Supply Rating
Transition Time: 600 ns
Easily Interfaced
Low Power Consumption
Low System Crosstalk
Wide Analog Signal Range
Communication Systems
ATE
Data Acquisition Systems
Audio Signal Routing and Multiplexing
Medical Instrumentation
A channel in the on state conducts current equally well in both
directions. In the off state each channel blocks voltages up to
the power supply rails, normally 30 V peak-to-peak. An enable
(EN) function allows for device selection when several
multiplexers are used. All control inputs, address (AX) and
enable (EN) are TTL or CMOS compatible over the full
specified operating temperature range.
ESD protection for ruggedness. An epitaxial layer prevents
latch up.
The DG506A_MIL/507A_MIL are fabricated in the
Vishay Siliconix PLUS-40 process, which includes improved
For wideband/video
recommended.
The DG506A_MIL/507A_MIL are available in hermetic
packages. For plastic packages, use the DG406/407 as
pin-for-pin replacements.
multiplexing,
the
DG536
is
Dual-In-Line
V+
NC
NC
1
2
Dual-In-Line
28
DG506A_MIL
27
D
V+
V–
Db
S8
NC
S7
28
1
DG507A_MIL
Da
V–
2
27
3
26
S8a
S8b
4
25
S7a
S6
S7b
5
24
S6a
S5
S6b
6
23
S5a
3
26
S16
4
25
S15
5
24
S14
6
23
S13
7
22
S4
S5b
7
22
S4a
S12
8
21
S3
S4b
8
21
S3a
S11
9
20
S2
S3b
9
20
S2a
S10
10
19
S1
S2b
10
19
S1a
S9
11
18
EN
S1b
11
18
17
A0
GND
16
A1
NC
15
A2
NC
GND
NC
A3
12
Decoders/Drivers
13
14
Top View
Document Number: 70066
S-00405—Rev. D, 21-Feb-00
12
Decoders/Drivers
13
14
EN
17
A0
16
A1
15
A2
Top View
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5-1
DG506A_MIL/507A_MIL
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLE Ċ DG506A_MIL
TRUTH TABLE Ċ DG507A_MIL
A3
A2
A1
A0
EN
On Switch
A2
A1
A0
EN
On Switch
X
X
X
X
0
None
X
X
X
0
None
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
2
0
0
1
1
2
0
0
1
0
1
3
0
1
0
1
3
0
0
1
1
1
4
0
1
1
1
4
0
1
0
0
1
5
1
0
0
1
5
0
1
0
1
1
6
1
0
1
1
6
0
1
1
0
1
7
1
1
0
1
7
0
1
1
1
1
8
1
1
1
1
8
1
0
0
0
1
9
1
0
0
1
1
10
Logic “0” = VAL 0.8 V
Logic “1” = VAH 2.4 V
X = Don’t Care
1
0
1
0
1
11
1
0
1
1
1
12
1
1
0
0
1
13
1
1
0
1
1
14
1
1
1
0
1
15
1
1
1
1
1
16
ORDERING INFORMATION Ċ DG507A_MIL
Temp Range
ORDERING INFORMATION Ċ DG506A_MIL
Temp Range
Package
28-Pin CerDIP
55 to 125
C
–55
125_C
28-Pin Sidebraze
LCC-28*
Part Number
DG506AAK
Package
28-Pin CerDIP
55 to 125
C
–55
125_C
28-Pin Sidebraze
28-Pin LCC
Part Number
DG507AAK
DG507AAK/883
JM38510/19003BXC
DG507AAZ/883
DG506AAK/883
JM38510/19001BXC
DG506AAZ/883
*Block Diagram and Pin Configuration not shown.
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to V–
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V or
20 mA, whichever occurs first
Power Dissipation (Package)b
28-Pin CerDIP and Sidebraze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW
28-Pin PLCCNO TAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW
LCC-20,28c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Current (Any Terminal, Except S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Storage Temperature
(CerDIP) . . . . . . . . . . . . . . . . . . . . –65 to 150_C
(Plastic DIP) . . . . . . . . . . . . . . . . –65 to 125_C
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5-2
Notes:
a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 14 mW/_C above 75_C.
Document Number: 70066
S-00405—Rev. D, 21-Feb-00
DG506A_MIL/507A_MIL
Vishay Siliconix
Test Conditions
Unless Otherwise Specified
Parameter
A Suffix
–55 to 125_C
V+ = 15 V, V– = –15 V
VIN = 2.4 V, 0.8 Vf
Tempb
Mind
VANALOG
Full
–15
Symbol
Typc
Maxd
Unit
15
V
240
400
500
6
Analog Switch
Analog Signal Rangee
Drain-Source
On-Resistance
rDS(on)
VD = "10 V, IS = –200 mA
Room
Full
rDS(on) Matchingg
DrDS(on)
–10 V < VS < 10 V
Room
Source Off
Leakage Current
IS(off)
VS = "10 V, VD = #10 V
VEN = 0 V
Room
Full
–1
–50
1
50
Drain Off
Leakage Current
DG506A_MIL
ID(off)
Room
Full
–10
–300
10
300
DG507A_MIL
Room
Full
–5
–200
5
200
Drain On
Leakage Current
DG506A_MIL
ID(on)
Room
Full
–10
–300
10
300
DG507A_MIL
Room
Full
–5
–200
5
200
VA = 2.4 V
Room
Full
–10
–30
VA = 15 V
Room
Full
VD= #10 V
VS = "10 V
VEN = 0 V
VS = VD = "10 V
W
%
nA
A
Digital Control
g Input
p Current
Logic
Input
High
I
t Voltage
V lt
Hi h
IAH
Logic Input Current
Input Voltage Low
IAL
VEN = 0 V, 2.4 V, VA = 0 V
Room
Full
Transition Time
tTRANS
See Figure 2
Room
0.6
Break-Before-Make Time
tOPEN
See Figure 4
Room
0.2
Enable Turn-On Time
tON(EN)
Room
1
1.5
Enable Turn-Off Time
tOFF(EN)
Room
0.4
1.0
Room
6
pC
68
dB
10
30
mA
–10
–30
Dynamic Characteristics
Charge Injection
See Figure 3
Q
Off Isolationh
OIRR
VEN = 0 V, RL = 1 kW , CL = 15 pF
VS = 7 VRMS, f = 500 kHz
Room
Source Off Capacitance
CS(off)
VEN = 0 V, VS = 0 V, f = 140 kHz
Room
6
DG506A_MIL
Room
45
CD(off)
VEN = 0 V
VD = 0 V
f = 140 kHz
DG507A_MIL
Room
23
Drain Off Capacitance
1.0
ms
pF
p
F
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I–
VEN = 0 V, VA = 0 V
Room
Room
1.3
–1.5
–0.7
2.4
mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f.
VIN = input voltage to perform proper function.
r DS(on)MAX – r DS(on)MIN
g.
Dr DS(on) +
r DS(on)AVE
ǒ
h.
Off isolation + 20 log
Document Number: 70066
S-00405—Rev. D, 21-Feb-00
Ǔ
VD
VS
, VS + input to off switch, VD + output due to VS.
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5-3
DG506A_MIL/507A_MIL
Vishay Siliconix
_ Input Switching Threshold vs.
V+ and V– Supply Voltages
rDS(on) vs. VD and Power Supply
2.5
5 V
2.0
500
1.5
400
V T (V)
r DS(on)– Drain-Source On-Resistance ( W )
600
7.5 V
10 V
300
1.0
15 V
200
0.5
20 V
100
0
–20
–10
0
10
VD – Drain Voltage (V)
”15
”10
”20
V+, V– Positive and Negative Supplies (V)
rDS(on) vs. VD and Temperature
Charge Injection vs. Analog Voltage
400
r DS(on)– Drain-Source On-Resistance ( W )
16
V+ = 15 V
V– = –15 V
14
12
10
Q (pC)
”5
0
20
8
6
4
2
0
–15
V+ = 15 V
V– = –15 V
350
300
125_C
250
25_C
200
150
–55_C
100
50
0
–10
–5
0
5
10
–15
15
VS – Source Voltage (V)
–10
–5
0
5
10
15
VD – Drain Voltage (V)
Supply Current vs. Switching Frequency
Crosstalk vs. Frequency
6
0
V+ = 15 V
V– = –15 V
V+ = 15 V
V– = –15 V
ref. 0.0 dBm
–20
4
CerDIP
I+
–40
X TALK (dB)
I+, I– (mA)
2
0
I–
–60
–2
–80
–4
–100
–6
–120
10 k
100 k
f – Frequency (Hz)
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Plastic
1M
1k
10 k
100 k
1M
10 M
f – Frequency (Hz)
Document Number: 70066
S-00405—Rev. D, 21-Feb-00
DG506A_MIL/507A_MIL
Vishay Siliconix
_ Off Isolation vs. Frequency
Switching Time vs. Temperature
0
1000
V+ = 15 V
V– = –15 V
ref. 0 dBm
–20
V+ = 15 V
V– = –15 V
900
CerDIP
tRANS
t TRANS, t OPEN (ns)
800
OIRR (dB)
–40
Plastic
–60
–80
700
600
tOPEN
500
400
–100
300
–120
200
1k
10 k
100 k
1M
10 M
–55
–35
–15
5
f – Frequency (Hz)
Switching Time vs. Positive Supply Voltage
45
85
65
105
125
105
125
Leakages vs. Temperature
100 nA
1100
1000
V+ = 15 V
V– = –15 V
VD = 14 V
10 nA
900
800
700
Leakage Current
t TRANS, t OPEN (ns)
25
Temperature (_C)
tRANS
600
500
tOPEN
1 nA
ID(on), ID(off)
100 pA
IS(off)
10 pA
400
1 pA
300
0.1 pA
–55
200
10
12
14
16
18
20
22
–35 –15
V+ – Positive Supply (V)
25
45
65
85
Temperature (_C)
IS(off) vs. Analog Voltage
15
5
ID(on), ID(off) vs. Analog Voltage
20
V+ = 15 V
V– = –15 V
VS = –VD
TA = 25_C
10
V+ = 15 V
V– = –15 V
TA = 25_C
0
ID(on)
0
I D (pA)
I S (pA)
5
IS(off)
–20
ID(off)
–40
–5
–60
–10
–15
–80
–15
–10
–5
0
5
VS – Source Voltage (V)
Document Number: 70066
S-00405—Rev. D, 21-Feb-00
10
15
–15
–10
–5
0
5
10
15
VD – Drain Voltage (V)
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5-5
DG506A_MIL/507A_MIL
Vishay Siliconix
V+
S1
GND
V+
–
+
A0
V–
Sn
V–
V+
V+
Decode/
Drive
–
+
AX
V+
V–
V–
V–
V+
–
+
EN
V+
D
V–
FIGURE 1.
+15 V
+2.4 V
V+
EN
A2
"10 V
S1
A3
S2 – S15
DG506A_MIL
#10 V
A1
S16
A0
D
GND
Logic
Input
VO
50%
0V
V–
50 tr <20 ns
tf <20 ns
3V
35 pF
1M
VS1
–15 V
90%
Switch
Output
VO
0V
+15 V
+2.4 V
V+
EN
A2
90%
VS8
S1b
"10 V
tTRANS
S1 ON
*
DG507A_MIL
A1
S8b
A0
Db
GND
tTRANS
S8 ON
#10 V
VO
V–
50 1M
35 pF
–15 V
* = S1a – S8a, S2b – S7b, Da
FIGURE 2. Transition Time
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Document Number: 70066
S-00405—Rev. D, 21-Feb-00
DG506A_MIL/507A_MIL
Vishay Siliconix
+15 V
V+
A3
S1
A2
–5 V
S2 – S16
A1
A0 DG506A_MIL
EN
VO
D
GND
V–
35 pF
1k
50 –15 V
tr <20 ns
tf <20 ns
3V
Logic
Input
50%
0V
tON(EN)
tOFF(EN)
0V
10%
+15 V
Switch
Output
V+
A2
S1b
S1a – S8a
S2b – S8b
A1
A0
–5 V
VO
90%
VO
DG507A_MIL
Da and Db
EN
GND
VO
V–
35 pF
50 1k
–15 V
FIGURE 3. Enable Switching Time
+15 V
Logic
Input
V+
EN
+2.4 V
All S and Da
A3
+5 V
tr <20 ns
tf <20 ns
3V
50%
0V
A2 DG506A_MIL
DG507A_MIL
A1
A0
GND
1k
–15 V
80%
Switch
Output
V–
50 VS
VO
D,Db
35 pF
VO
0V
tOPEN
FIGURE 4. Break-Before-Make Interval
Document Number: 70066
S-00405—Rev. D, 21-Feb-00
www.vishay.com FaxBack 408-970-5600
5-7
DG506A_MIL/507A_MIL
Vishay Siliconix
V+
Positive Supply
Voltage
(V)
V–
Negative Supply
Voltage
(V)
VIN
Logic Input Voltage
VINH(min)/VINL(max)
(V)
VS or VD
Analog Voltage
Range
(V)
15b
–15
2.4/0.8
–15 to 15
12
–12
2.4/0.8
–12 to 12
10
–10
2.2/0.6
–10 to 10
8c
–8
2.0/0.5
–8 to 8
Notes:
a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
b. Electrical Parameter Chart based on V+ = 15 V, V– = –15 V.
c. Operation below "8 V is not recommended due to shift in VINL(MAX).
Overvoltage Protection
V+ v Vg vV–
+V
1N4148
A very convenient form of overvoltage protection consists of
adding two small signal diodes (1N4148, 1N914 type) in series
with the supply pins (see Figure 5). This arrangement
effectively blocks the flow of reverse currents. It also floats the
supply pin above or below the normal V+ or V– value. In this
case the overvoltage signal actually becomes the power
supply of the IC. From the point of view of the chip, nothing has
changed, as long as the difference between VS and the V– rail
doesn’t exceed +44 V. The addition of these diodes will reduce
the analog signal range to 1 V below V+ and 1 V above V–, but
it preserves the low channel resistance and low leakage
characteristics.
+V
SX
Internal
Junction
Internal
Junction DG506A_MIL
Vg
–V
DG507A_MIL
1N4148
–V
FIGURE 5. Overvoltage Protection Using Blocking Diodes
Channel 1
Channel 2
D
DG506A_MIL
#1
EN
Channel 16
A0 A1 A2 A3
A
Channel 17
Channel 18
D
S/H
A/D
Data
Bus
DG419
DG506A_MIL
#2
EN
Channel 32
A0 A1 A2 A3
Controller
FIGURE 6. A 32-Channel Data Acquisition System
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5-8
Document Number: 70066
S-00405—Rev. D, 21-Feb-00