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Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices. Renesas Technology Corp. Customer Support Dept. April 1, 2003 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5J167KT is a f amily of low v oltage 16Mbit static RAMs organized as 1048576-words by 16-bit / 2097152-words by 8-bit, f abricated by Mitsubishi's high-perf ormance 0.18µm CMOS technology . The M5M5J167KT is suitable f or memory applications where a simple interf acing , battery operating and battery backup are the important design objectiv es. The M5M5J167KT is made by stacked-micro-package technology and two chips of 8Mbits SRAMs are assembled in one package. By using this package technology , small package size can be achiev ed f or highdensity SRAM. The M5M5J167KT is packaged in a 52pin-µTSOP with the outline of 10.79mm x 10.49mm, and pin pitch of 0.40mm. It giv es the best solution f or a compaction of m ounting area as well as f lexibility of wiring pattern of printed circuit boards. The operating temperature range is -40 ~ +85°C FEATURES - Single 2.7~3.6V power supply Small stand-by current: 0.2µA (2.0V, ty p.) No clocks, No ref resh Data retention supply v oltage =2.0~3.6V All inputs and outputs are TTL compatible. Easy memory expansion by S1#, S2, BC1# and BC2# Common Data I/O Three-state outputs: OR-tie capability OE prev ents data contention in the I/O bus By te f unction (x8 mode) av ailable by By te# & A-1. Process technology : 0.18µm CMOS Package: 52pin 10.79mm x 10.49mm µTSOP [0.4mm pin pitch] Stand-by c urrent Operating temperature -40 ~ +85°C Part name Power Access time * Ty pical Ratings (max.) Supply max. 25ºC 40ºC 25ºC 40ºC 70ºC 85ºC M5M5J167KT -70HI 2.7 ~ 3.6V 70ns 2.0 2.4 10 PIN CONFIGURATION 16 40 Active current Icc1 (3.3V, Ty p.) 80 30mA (10MHz) 5mA (1MHz) * Typical parameter indicates the value for the center of distribution, and not 100% tested. A15 1 52 A14 2 51 BYTE# A13 3 50 BC2# A12 4 49 GND A11 5 48 A10 6 47 BC1# DQ16/A-1 A9 7 46 A8 8 45 DQ8 DQ15 A19 9 44 DQ7 S1# W# 10 43 DQ14 11 42 DQ6 NC 12 41 DQ13 A16 NC 13 40 DQ5 VCC 14 39 NC S2 15 38 NC 16 37 DQ12 DQ4 NC 17 36 DQ11 A18 18 35 DQ3 A17 A7 19 34 DQ10 20 33 DQ2 A6 21 32 DQ9 A5 22 31 DQ1 A0 ~ A18 Function Address input Address input A19 DQ1 ~ DQ16 Data input / output Chip select input 1 S1# S2 Chip select input 2 W# Write control input OE# BC1# Output enable input Lower By te (DQ1 ~ 8) BC2# Upper By te (DQ9 ~ 16) BYTE# By te (x8 mode) enable input OE# Vcc Power supply GND Ground supply 28 GND NC 27 A0 A4 23 30 A3 24 29 A2 25 A1 26 10.49mm Pin Outline: 52PTG-A N C : No Connection 1 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The M5M5J167KT is organized as 1048576-words by 16bit / 2097152-words by 8-bit. These dev ices operate on a single +2.7~3.6V power supply , and are directly TTL compatible to both input and output. Its f ully static circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1# , BC2# , S1#, S2 , W#, OE# and BY TE#. Each mode is summarized in the f unction table. The address select A19 can select either one 8MSRAM chip or another 8MSRAM chip. A write operation is executed whenev er the low lev el W# ov erlaps with the low lev el BC1# and/or BC2# and the low lev el S1# and the high lev el S2. The address (A-1~A19 : By te mode, A0~A19 : Word mode) must be set up bef ore the write cy c le and must be stable during the entire cy cle. A read operation is executed by s etting W# at a high lev el and OE# at a low lev el while BC1# and/or BC2# and S1#and S2 are in an activ e state (S1#=L, S2=H). When setting BYTE# at a low lev el, the f unction will be in the x8 mede, which is, DQ1-8 are av ailable and DQ9-16 are not av ailable. In the x8 mode, A-1 is used as the additional address. During the activ e f unction f or x8 mode, BC1# BC2# must be low lev el. When setting BC1# and BC2# at a high lev el or S1# at a high lev el or S2 at a low lev el, the chips are in a nonselectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1#, BC2# and S1#, S2. The power supply c urrent is reduced as low as 0.2µA (25°C, ty pical), and the memory data can be held at +2.0V power supply , enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. FUNCTION TABLE S1# S2 BYTE# BC1# BC2# W# OE# Mode DQ1~8 DQ9~15 DQ16 Icc H H X X X L X X X X X X X X Non selection High-Z High-Z High-Z Standby Non selection High-Z High-Z High-Z Standby X X H H H X X Non selection High-Z High-Z High-Z Standby L H H L H L X Write Din High-Z High-Z Active L L H H L H H H L H H L Read Dout High-Z High-Z Active H H ------- High-Z High-Z High-Z Active L H H H L L X Write High-Z Din Din Active L H H H L H L Read High-Z Dout Dout Active L H L H H H L H H ------- High-Z High-Z High-Z Active H L L L X Write Din Din Din Active L H H L L H L Read Dout Dout Dout Active L H H L L H H ------- High-Z High-Z High-Z Active L H L L L L X Write Din High-Z A-1 Active L H L L L H L Read Dout High-Z A-1 Active L H L L L H H ------- High-Z High-Z A-1 Active Note1 : "H" and "L" in this table mean VIH and VIL, respectiv ely . Note2 : "X" in this table should be "H" or "L". 2 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM BLOCK DIAGRAM 8MS(1) DQ1 A0 A 18 524288WORDS X 16 BITS or 1048576WORDS X 8 BITS DQ 8 DQ 9 S2 S1# CLOCK GENERATOR DQ 16 / A-1 BC1# BC2# x8/x16 Switching circuit VCC BYTE# GND W# OE# A 19 8MS(2) 3 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Ta T stg Parameter Conditions Supply v oltage Input v oltage With respect to GND Output v oltage With respect to GND Power dissipation Ta = 25°C With respect to GND Operating temperature Storage temperature Units Ratings - 0.3 * ~ +4.6 - 0.3 * ~ Vcc + 0.3 (max. 4.6V) 0 ~ Vcc 700 -40 ~ +85 - 65 ~ +150 V mW ºC ºC * -3.0V in case of AC (Pulse< =width DC ELECTRICAL CHARACTERISTICS Symbol (Ta=-40~85ºC Vcc=2.7V~3.6V,unless otherwise noted) Parameter Limits Conditions Min Ty p High-lev el input v oltage 2.2 Vcc+0.2V Low-lev el input v oltage - 0.2 * 2.4 0.6 Icc 1 Activ e supply c urrent ( AC,MOS lev el ) BC1# and BC2# < 0.2V, S1# < 0.2V, S2 >Vcc-0.2V other inputs < 0.2V or > Vcc-0.2V f = 10MHz Output - open (duty 100%) f = 1MHz BC1# and BC2#=V IL , S1#=V IL ,S2=V IH other pins =V IH or V IL Output - open (duty 100%) f = 10MHz Icc 2 Activ e supply c urrent ( AC,TTL lev el ) - f = 1MHz I OH= - 0.5mA Low-lev el output v oltage I OL= 2.0mA Input leakage current V I =0 ~ Vcc High-level output voltage BYTE# > Vcc - 0.2V or < 0.2V, other inputs = 0 ~ Vcc (2) S2 < 0.2V, Icc 3 Stand by s upply current ( AC,MOS lev el ) BYTE# > Vcc - 0.2V or < 0.2V, other inputs = 0 ~ Vcc (3) BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V BYTE# > Vcc - 0.2V or < 0.2V, A19 > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc Icc 4 Stand by s upply current ( AC,TTL lev el ) - 30 5 30 5 0.4 ±1 ±1 50 15 50 15 ~ +25°C - 2.0 10 ~ +40°C - 2.4 16 ~ +70°C - - 40 ~ +85°C - - 80 - - 2.0 BC1# and BC2#=VIH or S1#=VIH or S2=VIL or OE#=VIH, VI/O=0 ~ Vcc (1) S1# > Vcc - 0.2V and S2 > Vcc - 0.2V, BC1# and BC2# =VIH or S1# =VIH or S2=VIL BYTE# > Vcc - 0.2V or < 0.2V, A19 =V IH or V IL Other inputs= 0 ~ Vcc Note 3: Direction for current flowing into IC is indicated as positive (no mark) Note 4: Typical parameter indicates the value for the center of distribution at 3.0V, and not 100% tested. Units Max V IH V IL V OH V OL II IO Output leakage current 30ns) V µA mA µA mA * -1.0V in case of AC (Pulse width < = 30ns) CAPACITANCE (Ta=-40~+85ºC Vcc=2.7V~3.6V,unless otherwise noted) Symbol CI CO Parameter Conditions Min Limits Ty p Max Input capacitance V I =GND, VI =25mVrms, f =1MHz 20 Output capacitance V O = GND,VO =25mVrms, f =1MHz 20 Units pF 4 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM AC ELECTRICAL CHARACTERISTICS (Ta=-40~+85ºC, Vcc=2.7V~3.6V,unless otherwise noted) (1) TEST CONDITIONS 1TTL 2.7~3.6V Input pulse V IH=2.7V, V IL=0.2V Input rise time and f all time 5ns Supply v oltage DQ CL Transition is measured ±200mV from steady state voltage.(for ten,tdis) Ref erence lev el V OH=V OL=1.5V Output loads Fig.1,CL=30pF CL=5pF (for ten,tdis) Including scope and jig capacitance Fig.1 Output load (2) READ CYCLE t CR t a(A) t a(S1) t a(S2) t a(BC1) t a(BC2) t a(OE) t dis (S1) t dis (S2) t dis (BC1) t dis (BC2) t dis (OE) t en(S1) t en(S2) t en(BC1) t en(BC2) t en(OE) t V(A) Limits 70HI Parameter Symbol Read cy cle time Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time af t er S1# high Output disable time af t er S2 low Output disable time af t er BC1# high Output disable time af t er BC2# high Output disable time af t er OE# high Output enable time af ter S1# low Output enable time af ter S2 high Output enable time af ter BC1# low Output enable time af ter BC2# low Output enable time af ter OE# low Data v alid time after address Min 70 Units Max 70 70 70 70 70 35 25 25 25 25 25 10 10 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (3) WRITE CYCLE Symbol t CW t w(W) t su(A) t su(A-WH) t su(BC1) t su(BC2) t su(S1) t su(S2) t su(D) t h(D) t rec (W) t dis (W) t dis (OE) t en(W) t en(OE) Limits 70HI Parameter Write cy cle time Write pulse width Address setup time Address setup time with respect to W# By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W# low Output disable time f rom OE# high Output enable time f rom W# high Output enable time f rom OE# low Min 70 55 0 65 65 65 65 65 35 0 0 Max 25 25 5 5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM (4) Byte# function Limits Symbol tsu (BYTE) trec (BYTE) Parameter Test conditions Min / BYTE set up time Ty p Max 5 5 / BYTE recov ery time Units ms ms (5) TIMING DIAGRAMS BYTE# S2 S1# t su (BYTE) t rec (BYTE) BYTE# Read cycle t CR A 0~19 (Word Mode) A -1~19 t a(A) (Byte Mode) BC1#, BC2# t v (A) t a(BC1) or t a(BC2) (Note5) t dis (BC1) or t dis (BC2) (Note5) t a(S1) S1# (Note5) t dis (S1) (Note5) t dis (S2) (Note5) t a(S2) S2 (Note5) t a (OE) OE# (Note5) W# = "H" lev el DQ 1~16 (Word Mode) DQ 1~8 (Byte Mode) t en (OE) t en (BC1) t en (BC2) t en (S1) t en (S2) t dis (OE) (Note5) VALID DATA 6 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM Write cycle( W# control mode ) A 0~19 t CW (Word Mode) A -1~19 (Byte Mode) t su (BC1) or t su (BC2) BC1#, BC2# (Note5) (Note5) t su (S1) S1# (Note5) (Note5) S2 t su (S2) (Note5) (Note5) OE# t su (A) t su (A-WH) t w (W) t rec (W) t dis (W) W# t en (OE) t en (W) t dis (OE) DQ 1~16 (Word Mode) DATA IN STABLE DQ 1~8 (Byte Mode) t su (D) Write cycle (BC# control mode) A 0~19 (Word Mode) t h (D) t CW A -1~19 (Byte Mode) t su (A) BC1#, BC2# t su (BC1) or t su (BC2) t rec (W) S1# (Note5) (Note5) S2 (Note5) W# DQ 1~16 (Note5) (Note7) (Note6) (Note5) t su (D) t h (D) (Note5) (Word Mode) DQ 1~8 DATA IN STABLE (Byte Mode) Note 5: Hatching indicates the state is "don't care". Note 6: A Write occurs during S1# low, S2 high ov erlaps BC1# and/or BC2# low and W# low. Note 7: When the f alling edge of W# is simultaneously or prior to the f alling edge of BC1# and/or BC2# or the f alling edge of S1# or rising edge of S2, the outputs are maintained in the high impedance state. Note 8: Don't apply inv erted phase signal externally when DQ pin is in output mode. 7 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM Write cycle (S1# control mode) t CW A 0~19 (Word Mode) A -1~19 (Byte Mode) BC1#, BC2# (Note5) t su (A) t su (S1) t rec (W) (Note5) S1# S2 (Note5) (Note5) (Note7) W# (Note6) (Note5) t su (D) DQ 1~16 t h (D) (Note5) (Word Mode) DATA IN STABLE DQ 1~8 (Byte Mode) Write cycle (S2 control mode) A 0~19 t CW (Word Mode) A -1~19 (Byte Mode) BC1#, BC2# (Note5) t su (A) t su (S2) t rec (W) (Note5) S1# (Note5) (Note5) S2 (Note7) W# (Note6) (Note5) DQ 1~16 (Word Mode) t su (D) t h (D) (Note5) DATA IN STABLE DQ 1~8 (Byte Mode) 8 MITSUBISHI LSIs Jan.10,2003 Ver. 2.1 M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS (Ta=-40~85ºC, Vcc=2.7V~3.6V,unless otherwise noted) Symbol Vcc Parameter Test conditions Min (PD) Power down supply voltage V 2.0 V I (S1#) Chip select input S1# 2.0 V I (S2) Chip select input S2 Vcc=2.0V (1) S1# > Vcc - 0.2V, BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc (2) S2 < 0.2V , BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc (3) BC1# and BC2# > Vcc - 0.2V S1# < 0.2V, S2 > Vcc - 0.2V BYTE# > Vcc - 0.2V or < 0.2V other inputs = 0 ~ Vcc ~ +25°C - 0.2 3.0 ~ +40°C - 0.4 6.0 ~ +70°C - - 30 60 ~ +85°C µA Note 9: Typical parameter of Icc(PD) indicates the value for the center of distribution at 2.0V, and not 100% tested. (2) TIMING REQUIREMENTS t su (PD) t rec (PD) V 0.2 Power down supply c urrent Symbol Units V Byte control input BC1# & BC2# (PD) Max 2.0 V I (BC) Icc Limits Ty p Parameter Test conditions Min Limits Ty p Max 0 5 Power down set up time Power down recov ery t ime Units ns ms (3) TIMING DIAGRAM note10: On the BC# control mode, the lev el of S1# and S2 must be f ixed BC# control mode at S1#, S2, A19 > Vcc-0.2V or S2 <0.2V Vcc t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V BC1# BC2# BC1# , BC2# > Vcc - 0.2V note11: On the S1# control mode, the lev el of S2 must be f ixed S1# control mode Vcc at S2 > Vcc-0.2V or S2 <0.2V t su (PD) 2.7V 2.7V t rec (PD) 2.2V 2.2V S1# > Vcc - 0.2V S1# S2 control mode Vcc S2 t su (PD) 2.7V 2.7V t rec (PD) 0.2V 0.2V S2 < 0.2V 9 Jan.10,2003 Ver. 2.1 MITSUBISHI LSIs M5M5J167KT - 70HI 16777216-BIT (1048576-WORD BY 16-BIT / 2097152-WORD BY 8-BIT) CMOS STATIC RAM Keep safety first in your circuit designs! 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