RMBA09501A Cellular 2 Watt Linear GaAs MMIC Power Amplifier General Description Features The RMBA09501A is a high power, highly linear Power Amplifier. The two stage circuit uses our advanced 0.25µm pHEMT process. It is designed for use as a driver stage for Cellular base stations, or as the output stage for Micro- and Pico-Cell base stations. The amplifier has been optimized for high linearity requirements for CDMA operation. • 2 Watt Linear output power at 36dBc ACPR1 for CDMA operation • OIP3 ≥ 43dBc at 27 and 30dBm power output • Small Signal Gain of > 30dB • Small outline SMD package Device Absolute Ratings Symbol VDD VGS Pin TC TSTG Parameter Drain Supply Voltage1 Gate Supply Voltage RF Input Power (from 50Ω source) Case Operating Temperature Storage Temperature Range Value +10 -5 +5 -30 to +85 -40 to +100 Units V V dBm °C °C Note: 1. Only under quiescent conditions—no RF applied. ©2003 Fairchild Semiconductor Corporation RMBA09501A Rev. C RMBA09501A May 2004 Parameter Frequency Ranges Gain (Small Signal) Gain Variation: Over Frequency Range Over Temperature Range Noise Figure Output Power @ CDMA3 OIP34 Idd @ 33dBm Pout – 7V PAE @ 33dBm Pout Input VSWR (50Ω) Drain Voltage (VDD) Gate Voltages (VG1, VG2)5 Quiescent Currents (IDQ1, IDQ2)5 Thermal Resistance (Channel to Case) Rjc Min 869 30 Typ Max 894 35 ±1.5 ±2.5 6 33 43 dB dB dB dBm dBm A % 45 1.0 28.5 2:1 7.0 -2 -0.25 150, 400 11 Units MHz dB V V mA °C/W Notes: 2. VDD = 7.0V, TC = 25°C. Part mounted on evaluation board with input and output matching to 50Ω. 3. 9 Channel Forward Link QPSK Source; 1.23Mbps modulation rate. CDMA ACPR1 is measured using the ratio of the average power within the 1.23MHz channel at band center to the average power within a 30KHz bandwidth at an 885KHz offset. Minimum CDMA output power is met with ACPR1 > 36dBc. 4. OIP3 specifications are achieved for power output levels of 27 and 30 dBm per tone with tone spacing of 1.25MHz at bandcenter. 4. VG1 and VG2 must be individually adjusted to achieve IDQ1 and IDQ2. A single VGG bias supply adjusted to achieve IDQTOTAL = 550mA can be used with nearly equivalent performance. Values for IDQ1 and IDQ2 shown have been optimized for CDMA operation. IDQ1 and IDQ2 (or IDQTOTAL) can be adjusted to optimize the linearity of the amplifier for other modulation systems. The device requires external input and output matching to 50Ω as shown in Figure 3 and the Parts List. ©2003 Fairchild Semiconductor Corporation RMBA09501A Rev. C RMBA09501A Electrical Characteristics2 CAUTION: THIS IS AN ESD SENSITIVE DEVICE The following describes a procedure for evaluating the RMBA09501A, a monolithic high efficiency power amplifier, in a surface mount package, designed for use as a driver stage for Cellular Base stations, or as the final output stage for Microand Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional block diagram of the packaged product. The RMBA09501A requires external passive components for DC bias and RF input and output matching circuits as shown in Figure 3 and the Part List. A recommended schematic circuit is shown in Figure 3. The gate biases for the two stages of the amplifier may be set by simple resistive voltage dividers. Figure 4 shows a typical layout of an evaluation board, corresponding to the schematic circuits of Figure 3. The following designations should be noted: (1) Pin designations are as shown in Figure 1. (2) Vg1 and Vg2 are the Gate Voltages (negative) applied at the pins of the package. (3) Vgg1 and Vgg2 are the negative supply voltages at the evaluation board terminals. (4) Vd1 and Vd2 are the Drain Voltages (positive) applied at the pins of the package. (5) Vdd1 and Vdd2 are the positive supply voltages at the evaluation board terminals. Note: The 2 terminals of Vdd1 and Vdd2 may be tied together. The base of the package must be soldered on to a heat sink for proper operation. Top View Bottom View 0.200 SQ. 6 5 4 7 0.030 4 6 0.015 3 8 2 9 5 3 7 2 8 1 9 0.020 1 0.011 10 11 12 12 11 10 Plastic Lid 0.010 0.075 MAX 0.230 0.246 0.282 Side Section Dimensions in inches 0.041 Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 RF Out & Vd2 RF Out & Vd2 RF Out & Vd2 AC Ground (g2) GND AC Ground (g1) GND RF In GND Vd1 Vg2 Vg1 GND (Metal Base) Figure 1. Package Outline and Pin Designations ©2003 Fairchild Semiconductor Corporation RMBA09501A Rev. C RMBA09501A Application Information RMBA09501A Vd1 Pin# 10 A C Ground (g2) Ground Pin# 5, 7, 9, 13 Pin# 4 MMIC CHIP RF IN Pin# 8 RF OUT & Vd2 Pin# 1, 2, 3 AC Ground (g1) Pin# 6 Vg1 Pin# 12 Vg2 Pin# 11 Figure 2. Functional Block Diagram of Packaged Product C11 1000pF R1 10Ω C12 1000pF Z0 = 50Ω E = 4.8* @ 900MHz L1 4.7nH RFIN Z0 = 50Ω E = 3.4* @ 900MHz Z0 = 50Ω E = 8.1* @ 900MHz RFOUT P2 P1 C1 39pF RMBA09501A U1 C2 6.8pF P3 P3 13 Package Base S1 VG2 S2 VG1 C8 8.2pF C9 6.8pF C10 100pF L3 39nH C13 .1µF L2 22nH C14 .1µF VDD P3 C3 39pF C4 1000pF C5 1000pF + C6 4.7µF + C7 4.7µF Figure 3. Schematic of Application Circuit Showing External Components ©2003 Fairchild Semiconductor Corporation RMBA09501A Rev. C RMBA09501A Figure 4. Layout of Test Evaluation Board (RMBA09501A-TB, G657471) Test Procedure for the Evaluation Board (RMBA09501A-TB) CAUTION: LOSS OF GATE VOLTAGES (VG1, VG2) WHILE CORRESPONDING DRAIN VOLTAGES (Vdd) ARE PRESENT CAN DAMAGE THE AMPLIFIER. The following sequence must be followed to properly test the amplifier. (It is necessary to add a fan to provide air cooling across the heat sink of RMBA09500.) Note: Vdd1, 2 are tied together. Step 1: Turn off RF input power. Step 2: Use GND terminal of the evaluation board for the ground of the DC supplies. Slowly apply gate supply voltages to the board terminals Vgg1 and Vgg2. Step 3: Slowly apply drain supply voltages of +7.0V to the board terminals Vdd1, 2. Adjust Vgg to set the total quiescent current (with no RF applied) Idq as per supplied result sheet. Gate supply voltages (Vgg i.e., Vgg1, Vgg2) may be adjusted, only if quiescent current (Idq1 and Idq2) values desired are different from those noted on the data summary supplied with product samples. Step 4: After the bias condition is established, RF input signal may now be applied at the appropriate frequency band and appropriate power level. Step 5: Follow turn-off sequence of: (i) Turn off RF Input Power (ii) Turn down and off drain voltages Vdd1, 2. (iii) Turn down and off gate voltages Vgg1 and Vgg2. ©2003 Fairchild Semiconductor Corporation RMBA09501A Rev. C RMBA09501A Parts List for Test Evaluation Board (RMBA09501A-TB) Part C1, C3 C2, C9 C8 C4, C5, C11, C12 C6, C7 L1 L2 L3 R1 S1, S2 W1 U1 P3 P1, P2 Board C10 C13, C14 39pF 6.8pF 8.2pF 1000pF 4.7µF 4.7nH 22nH 39nH 10Ω Value Size (EIA) 0402 0402 0402 0402 3528 0603 0603 1008 0402 26AWG (0.015" dia) Wire RMBA09501A PA Right angle Pin Header Brass SMA Connectors FR4 100pF 1.0µF 0603 0805 Vendor(s) Murata, GRM36COG390J050 Murata, GRM36COG6R8B050 Murata, GRM36COG8R2B50 Murata, GRM36X7R102K050 TDK, C3216X7R102K050 Toko, LL1608-FH4N7S Toko, LL1608-FH22NK Coilcraft, 1008HQ-39NTKBC IMS, RCI-0402-10R0J Bar or Ni Ribbon Short Alpha, 2853/1 Fairchild Semiconductor 3M 2340-5211TN Johnson Components 142-0701-841 Raytheon Dwg# G654626, V1 Murata, GRM36COG101J50 Murata, GRM39Y5V104Z50 Thermal Considerations for Heat Sinking the RMBA09501A The PWB must be prepared with either an embedded copper slug in the board where the package is to be mounted or a heat sink should be attached to the backside of the PWB where the package is to be mounted on the front side. The slug or the heat sink should be made of a highly electrically and thermally conductive material such as copper or aluminum. The slug should be at least the same thickness as the PWB. In the case of the heat sink, a small pedestal should protrude through a hole in the PWB where the package bottom is directly soldered. In either ©2003 Fairchild Semiconductor Corporation configuration, the top surface of the slug or the pedestal should be made coplanar with the package lead mounting plane i.e., the top surface of the PWB. Use Sn96 solder (96.5% Sn and 3.5% Ag) at 220°C for 20 seconds or less to attach the heat sink to the backside of the PWB. Then, using Sn63, the package bottom should be firmly soldered to the slug or the pedestal while the pins are soldered to the respective pads on the front side of the PWB without causing any stress on the pins. Remove flux completely if used for soldering. RMBA09501A Rev. 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Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11