TI MC3486

MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MAY 1995
D
D
D
D
D
D OR N PACKAGE
(TOP VIEW)
Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B and
EIA/TIA-423-B and ITU Recommendations
V.10 and V.11
3-State, TTL-Compatible Outputs
Fast Transition Times
Operates From Single 5-V Supply
Designed to Be Interchangeable With
Motorola MC3486
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
3,4EN
3Y
3A
3B
description
The MC3486 is a monolithic quadruple differential line receiver designed to meet the specifications of ANSI
Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11. The MC3486 offers
four independent differential-input line receivers that have TTL-compatible outputs. The outputs utilize 3-state
circuitry to provide a high-impedance state at any output when the appropriate output enable is at a low logic
level.
The MC3486 is designed for optimum performance when used with the MC3487 quadruple differential line
driver. It is supplied in a 16-pin package and operates from a single 5-V supply.
The MC3486 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each receiver)
ENABLE
OUTPUT
Y
VID ≤ 0.2 V
– 0.2 V < VID < 0.2 V
H
H
H
?
VID ≤ – 0.2 V
Irrelevant
H
L
L
Z
Open
H
?
DIFFERENTIAL INPUTS
A–B
H = high level, L = low level, Z = high impedance (off),
? = indeterminate
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Motorola is a trademark of Motorola, Incorporated.
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MAY 1995
logic symbol†
1, 2EN
1A
1B
2A
2B
3, 4EN
3A
3B
4A
4B
4
logic diagram (positive logic)
1, 2EN
EN
2
3
1
6
5
7
12
1A
1Y
1B
2A
2Y
2B
3, 4EN
EN
10
11
9
14
13
15
3A
3B
3Y
4A
4Y
4B
4
2
3
1
6
5
7
1Y
2Y
12
10
9
14
15
11
13
3Y
4Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
EXCEPT OUTPUT ENABLE
VCC
VCC
16.8 kΩ
NOM
Input
EQUIVALENT OF OUTPUT ENABLE
960 Ω
NOM
85 Ω
NOM
8.3 kΩ
NOM
Output
Enable
VCC
4.9 kΩ
NOM
Output
960 Ω
NOM
2
TYPICAL OF ALL OUTPUTS
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• DALLAS, TEXAS 75265
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MAY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Input voltage, VI (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 15 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
Enable input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential-input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
D
950 mW
7.6 mW/°C
608 mW
N
1150 mW
9.2 mW/°C
736 mW
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
±7
V
±6
V
Common-mode input voltage, VIC
Differential input voltage, VID
High-level enable input voltage, VIH
2
Low-level enable input voltage, VIL
Operating free-air temperature, TA
0
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V
0.8
V
70
°C
3
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MAY 1995
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT +
VIT –
Differential input high-threshold voltage
Differential input low-threshold voltage
VO = 2.7 V,
VO = 0.5 V,
VIK
Enable-input clamp voltage
II = – 10 mA
VOH
High level output voltage
High-level
VID = 0.4 V,, IO = – 0.4 mA,,
See Note 3 and Figure 1
VOL
Low level output voltage
Low-level
VID = – 0.4 V,, IO = 8 mA,,
See Note 3 and Figure 1
IOZ
High impedance state output current
High-impedance-state
VIL = 0.8 V,
VIL = 0.8 V,
Differential input bias current
Differential-input
VCC = 0 V or 5.25 V,,
Other inputs at 0 V
IIH
High level enable input current
High-level
VI = 5.25 V
VI = 2.7 V
IIL
IOS
Low-level enable input current
IIB
VI = – 0.5 V
VID = 3 V,
Short-circuit output current
MIN
IO = – 0.4 mA
IO = – 8 mA
MAX
0.2
– 0.2†
27
2.7
40
– 40
VI = – 10 V
VI = – 3 V
V
µA
– 3.25
–1.5
VI = 3 V
VI = 10 V
1.5
mA
3.25
100
20
VO = 0,
V
V
05
0.5
VO = 2.7 V
VO = 0.5 V
V
V
– 1.5
VID = – 3 V,
VID = 3 V,
UNIT
See Note 4
– 15
µA
– 100
µA
– 100
mA
ICC
Supply current
VIL = 0
85
mA
† The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for threshold
voltages only.
NOTES: 3. Refer to ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B for exact conditions.
4. Only one output should be shorted at a time.
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER
TYP
MAX
28
35
ns
27
30
ns
Output enable time to high level
13
30
ns
Output enable time to low level
20
30
ns
26
35
ns
27
35
ns
tPHL
tPLH
Propagation delay time, high- to low-level output
tPZH
tPZL
tPHZ
tPLZ
Output disable time from high level
4
Propagation delay time, low- to high-level output
TEST CONDITIONS
See Figure 2
See Figure 3
Output disable time from low level
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MIN
UNIT
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MAY 1995
PARAMETER MEASUREMENT INFORMATION
500 Ω
VID
500 Ω
VOH
IOL
(+)
IOH
(–)
VOL
2V
Figure 1. VOH, VOL
3V
Generator
(see Note A)
Output
51 Ω
1.5 V
Input 1.5 V
0V
CL = 15 pF
(see Note B)
tPLH
tPHL
VOH
1.5 V
1.3 V
Output
1.3 V
2V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 6 ns,
tf ≤ 6 ns.
B. CL includes probe and stray capacitance.
Figure 2. Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MAY 1995
PARAMETER MEASUREMENT INFORMATION
– 1.5 V
1.5 V
SW1
Output
SW2
2 kΩ
5 kΩ
See Note C
CL = 15 pF
(see Note B)
Generator
(see Note A)
5V
SW3
51 Ω
TEST CIRCUIT
tPZH
Input
SW1 to 1.5 V
1.5 V SW2 Open
SW3 Closed
0V
1.5 V
Input
VOH
1.5 V
tPZL
4.5 V
Output
1.5 V
VOL
1.3 V
tPHZ
tPLZ
3V
Input
0V
SW1 to 1.5 V
SW2 Closed
SW3 Closed
1.5 V
Input
0V
tPHZ
3V
SW1 to – 1.5 V
SW2 Closed
SW3 Closed
tPLZ
VOH
Output
SW1 to – 1.5 V
SW2 Closed
SW3 Open
0V
tPZH
Output
3V
tPZL
3V
0.5 V
1.3 V
Output
0.5 V
VOL
1.3 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 6 ns,
tf ≤ 6 ns.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or equivalent.
Figure 3. Test Circuit and Voltage Waveforms
6
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