LTC485 Low Power RS485 Interface Transceiver U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Low Power: ICC = 300µA Typ Designed for RS485 Interface Applications Single 5V supply – 7V to 12V Bus Common-Mode Range Permits ±7V Ground Difference Between Devices on the Bus Thermal Shutdown Protection Power-Up/Down Glitch-Free Driver Outputs Permit Live Insertion or Removal of Transceiver Driver Maintains High Impedance in Three-State or with the Power Off Combined Impedance of a Driver Output and Receiver Allows Up to 32 Transceivers on the Bus 70mV Typical Input Hysteresis 30ns Typical Driver Propagation Delays with 5ns Skew Pin Compatible with the SN75176A, DS75176A and µA96176 UO APPLICATI ■ The CMOS design offers significant power savings over its bipolar counterpart without sacrificing ruggedness against overload of ESD damage. The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common-mode range. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. The receiver has a fail-safe feature which guarantees a high output state when the inputs are left open. The LTC485 is fully specified over the commercial and extended industrial temperature range. Low Power RS485/RS422 Transceiver Level Translator UO ■ S The LTC485 is a low power differential bus/line transceiver designed for multipoint data transmission standard RS485 applications with extended common-mode range (12V to – 7V). It also meets the requirements of RS422. TYPICAL APPLICATI Driver Outputs RO1 R VCC1 RE1 Rt A DE1 DI1 D GND1 Rt RO2 R VCC2 RE2 DE2 DI2 D B GND2 LTC485 • TA01 LTC485 • TA02 1 LTC485 U U RATI GS W W W W AXI U U ABSOLUTE PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage ....................................................... 12V Control Input Voltages ................... – 0.5V to VCC + 0.5V Driver Input Voltage ....................... – 0.5V to VCC + 0.5V Driver Output Voltage ........................................... ±14V Receiver Input Voltage.......................................... ±14V Receiver Output Voltages .............. – 0.5V to VCC + 0.5V Operating Temperature Range LTC485I...................................... – 40°C ≤ TA ≤ 85°C LTC485C.......................................... 0°C ≤ TA ≤ 70°C LTC485M.................................. – 55°C ≤ TA ≤ 125°C Lead Temperature (Soldering, 10 sec)................. 300°C ELECTRICAL CHARACTERISTICS ORDER PART NUMBER TOP VIEW RO 1 R RE 2 DE 3 DI 4 D J8 PACKAGE 8-LEAD CERAMIC DIP 8 VCC 7 B 6 A 5 GND N8 PACKAGE 8-LEAD PLASTIC DIP S8 PACKAGE 8-LEAD PLASTIC SOIC TJMAX = 155°C, θJA = 100°C/ W (J) TJMAX = 100°C, θJA = 130°C/ W (N) TJMAX = 100°C, θJA = 170°C/ W (S) LTC485CJ8 LTC485CN8 LTC485CS8 LTC485IN8 LTC485IS8 LTC485MJ8 S8 PART MARKING 485 485I VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3) SYMBOL PARAMETER CONDITIONS MIN VOD1 Differential Driver Output Voltage (Unloaded) IO = 0 ● VOD2 Differential Driver Output Voltage (with Load) R = 50Ω (RS422) R = 27Ω (RS485), Figure 1 ● ● TYP 2 1.5 MAX UNITS 5 V 5 V V 0.2 V ∆VOD Change in Magnitude of Driver DifferentialOutput Voltage for Complementary States R = 27Ω or R = 50Ω, Figure 1 ● VOC Driver Common-Mode Output Voltage R = 27Ω or R = 50Ω, Figure 1 ● 3 V ∆VOC Change in Magnitude of Driver Common-Mode Output Voltage for Complementary States R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V VIH Input High Voltage DE, DI, RE ● VIL Input Low Voltage DE, DI, RE ● 0.8 V IIN1 Input Current DE, DI, RE ● ±2 µA IIN2 Input Current (A, B) DE = 0, VCC = 0V or 5.25V 2 V VIN = 12V ● ±1 mA VIN = – 7V ● – 0.8 mA 0.2 V VTH Differential Input Threshold Voltage for Receiver – 7V ≤ VCM ≤ 12V ● ∆VTH Receiver Input Hysteresis VCM = 0V ● VOH Receiver Output High Voltage IO = – 4mA, VID = 200mV ● VOL Receiver Outpu Low Voltage IO = 4mA, VID = – 200mV ● 0.4 V IOZR Three-State (High Impedance) Output Current at Receiver VCC = Max, 0.4V ≤ VO ≤ 2.4V ● ±1 µA RIN Receiver Input Resistance – 7V ≤ VCM ≤ 12V ● ICC Supply Current No Load, Pins 2, 3, 4 = 0V or 5V – 0.2 70 mV 3.5 V 12 kΩ Outputs Enabled ● 500 900 µA Outputs Disabled ● 300 500 µA IOSD1 Driver Short-Circuit Current, VOUT = HIGH VO = – 7V ● 35 100 250 mA IOSD2 Driver Short-Circuit Current, VOUT = LOW VO = 10V ● 35 100 250 mA IOSR Receiver Short-Circuit Current 0V ≤ VO ≤ VCC ● 7 85 mA 2 LTC485 U SWITCHI G CHARACTERISTICS VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX tPLH Driver Input to Output tPHL Driver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, (Figures 3 and 5) ● 10 30 50 ns ● 10 30 50 ns tSKEW Driver Output to Output 5 10 ns tr, tf Driver Rise or Fall Time 15 25 ns tZH Driver Enable to Output High CL = 100pF (Figures 4 and 6) S2 Closed ● 40 70 ns tZL Driver Enable to Output Low CL = 100pF (Figures 4 and 6) S1 Closed ● 40 70 ns tLZ Driver Disable Time from Low CL = 15pF (Figures 4 and 6) S1 Closed ● 40 70 ns tHZ Driver Disable Time from High CL = 15pF (Figures 4 and 6) S2 Closed ● 40 70 ns tPLH Receiver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, (Figures 3 and 7) ● 30 90 200 ns ● 30 90 200 ● 3 ● tPHL tSKD tPLH – tPHL Differential Receiver Skew tZL Receiver Enable to Output Low tZH tLZ tHZ UNITS ns ● 13 CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns Receiver Enable to Output High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns Receiver Disable from Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns Receiver Disable from High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute maximum ratings are those beyond which the safety of the device cannot be guaranteed. Note 2: All currents into device pins are positive; all currents out ot device pins are negative. All voltages are referenced to device ground unless otherwise specified. ns Note 3: All typicals are given for VCC = 5V and TA = 25°C. Note 4: The LTC485 is guaranteed by design to be functional over a supply voltage range of 5V ±10%. Data sheet parameters are guaranteed over the tested supply voltage range of 5V ±5%. TEST CIRCUITS A 1k RECEIVER OUTPUT VOD R S1 TEST POINT R VCC CRL 15pF VOC 1k S2 LTC485 • F02 B LTC485 • F01 Figure 1. Driver DC Test Load Figure 2. Receiver Timing Test Load 3V DE A DI CL1 RDIFF B S1 A RO B CL2 OUTPUT UNDER TEST VCC 500Ω S2 RE 15pF CL LTC485 • F02 LTC485 • F03 Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load #2 3 LTC485 U W W SWITCHI G TI E WAVEFOR S 3V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V DI 1.5V 0V t PLH 1/2 VO t PLH B VO A tSKEW 1/2 VO VO 0V –VO t SKEW 90% 80% VDIFF = V(A) – V(B) 10% 20% tr LTC485 • F05 tf Figure 5. Driver Propagation Delays 3V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V DI 1.5V 0V 5V t ZL t LZ A, B 2.3V OUTPUT NORMALLY LOW 0.5V 2.3V OUTPUT NORMALLY HIGH 0.5V VOL VOH A, B 0V t HZ t ZH LTC485 • F06 Figure 6. Driver Enable and Disable Times VOH 1.5V R VOL f = 1MHz, t r ≤ 10ns, t f ≤ 10ns t PHL VOD2 A, B –VOD2 0V 1.5V OUTPUT t PLH INPUT LTC485 • F07 Figure 7. Receiver Propagation Delays 3V 1.5V RE f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V 0V 5V t ZL R R t LZ 1.5V OUTPUT NORMALLY LOW 0.5V 1.5V OUTPUT NORMALLY HIGH 0.5V 0V t ZH t HZ Figure 8. Receiver Enable and Disable Times 4 LTC485 • F08 LTC485 U U FU CTIO TABLES U U U PI FU CTIO S LTC485 Transmitting INPUTS OUTPUTS RE DE DI LINE CONDITION B A X 1 1 No Fault 0 1 X 1 0 No Fault 1 0 X 0 X X Z Z X 1 X Fault Z Z PIN # NAME 1 RO 2 RE 3 DE 4 DI 5 6 7 8 GND A B VCC Receiver Output. If the receiver output is enabled (RE low), then if A > B by 200mV, RO will be high. If A < B by 200mV, then RO will be low. Receiver Output Enable. A low enables the receiver output, RO. A high input forces the receiver output into a high impedance state. Driver Outputs Enable. A high on DE enables the driver output. A and B, and the chip will function as a line driver. A low input will force the driver outputs into a high impedance state and the chip will function as a line receiver. Driver Input. If the driver outputs are enabled (DE high), then a low on DI forces the outputs A low and B high. A high on DI with the driver outputs enabled will force A high and B low. Ground Connection. Driver Output/Receiver Input. Driver Output/Receiver Input. Positive Supply; 4.75 < VCC < 5.25 LTC485 Receiving INPUTS OUTPUTS RE DE A–B R 0 0 ≥0.2V 1 0 0 ≤ – 0.2V 0 0 0 Inputs Open 1 1 0 X Z DESCRIPTION U W TYPICAL PERFOR A CE CHARACTERISTICS Receiver Output Low Voltage vs Output Current Receiver Output High Voltage vs Output Current 36 –18 TA = 25°C 4.8 TA = 25°C –16 OUTPUT CURRENT (mA) 28 24 20 16 12 8 4 0 4.6 –14 –12 –10 –8 –6 0.5 1.5 1.0 OUTPUT VOLTAGE (V) 2.0 LTC485 • TPC01 4.2 4.0 3.8 3.6 –4 3.4 –2 3.2 0 0 I = 8mA 4.4 OUTPUT VOLTAGE (V) 32 OUTPUT CURRENT (mA) Receiver Output High Voltage vs Temperature 5 4 3 OUTPUT VOLTAGE (V) 2 LTC485 • TPC02 3.0 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC03 5 LTC485 U W TYPICAL PERFOR A CE CHARACTERISTICS Receiver Output Low Voltage vs Temperature Driver Differential Output Voltage vs Output Current 0.9 72 I = 8mA OUTPUT CURRENT (mA) 0.7 OUTPUT VOLTAGE (V) 2.4 TA = 25°C 64 0.6 0.5 0.4 0.3 0.2 0.1 56 48 40 32 24 16 2.1 2.0 1.9 1.8 1.7 1.6 0 25 50 0 75 TEMPERATURE (°C) –25 100 125 1 0 3 2 OUTPUT VOLTAGE (V) LTC485 • TPC03 1.5 –50 4 40 30 20 10 –84 –72 –60 –48 –36 –24 3 2 OUTPUT VOLTAGE (V) 4 1.61 1.60 1.59 1.58 1.57 1.55 –50 0 1 0 1.62 1.56 –12 0 1.63 INPUT THRESHOLD VOLTAGE (V) OUTPUT CURRENT (mA) 50 1 0 3 2 OUTPUT VOLTAGE (V) LTC485 • TPC07 4 Driver Skew vs Temperature 4.8 580 6.5 4.2 520 6.0 3.6 3.0 2.4 1.8 4.0 1.2 3.5 0.6 3.0 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC10 6 SUPPLY CURRENT (µA) 7.0 TIME (ns) 640 4.5 0 –50 100 125 Supply Current vs Temperature 5.4 5.0 25 50 0 75 TEMPERATURE (°C) LTC485 • TPC09 7.5 5.5 –25 LTC485 • TPC08 Receiver tPLH – tPHL vs Temperature 125 1.64 TA = 25°C –96 60 100 TTL Input Threshold vs Temperature –108 TA = 25°C 70 25 50 0 75 TEMPERATURE (°C) LTC485 • TPC06 Driver Output High Voltage vs Output Current 90 80 –25 LTC485 • TPC05 Driver Output Low Voltage vs Output Current OUTPUT CURRENT (mA) 2.2 8 0 –50 RI = 54Ω 2.3 DIFFERENTIAL VOLTAGE (V) 0.8 TIME (ns) Driver Differential Output Voltage vs Temperature DRIVER ENABLED 460 400 340 DRIVER DISABLED 280 220 160 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC11 100 –50 –25 25 50 0 75 TEMPERATURE (°C) 100 125 LTC485 • TPC12 LTC485 U U W U APPLICATIO S I FOR ATIO Basic Theory of Operation Previous RS485 transceivers have been designed using bipolar technology because the common-mode range of the device must extend beyond the supplies and the device must be immune to ESD damage and latchup. Unfortunately, the bipolar devices draw a large amount of supply current, which is unacceptable for the numerous applications that require low power consumption. The LTC485 is the first CMOS RS485/RS422 transceiver which features ultra-low power consumption without sacrificing ESD and latchup immunity. The LTC485 uses a proprietary driver output stage, which allows a common-mode range that extends beyond the power supplies while virtually eliminating latchup and providing excellent ESD protection. Figure 9 shows the LTC485 output stage while Figure 10 shows a conventional CMOS output stage. When the conventional CMOS output stage of Figure 10 enters a high impedance state, both the P-channel (P1) and the N-channel (N1) are turned off. If the output is then driven above VCC or below ground, the P + /N-well diode (D1) or the N + /P-substrate diode (D2) respectively will turn on and clamp the output to the supply. Thus, the output stage is no longer in a high impedance state and is not able to meet the RS485 common-mode range requirement. In addition, the large amount of current flowing through either diode will induce the well known CMOS latchup condition, which could destroy the device. The LTC485 output stage of Figure 9 eliminates these problems by adding two Schottky diodes, SD3 and SD4. The Schottky diodes are fabricated by a proprietary modification to the standard N-well CMOS process. When the output stage is operating normally, the Schottky diodes are forward biased and have a small voltage drop across them. When the output is in the high impedance state and is driven above VCC or below ground, the parasitic diodes D1 or D2 still turn on, but SD3 or SD4 will reverse bias and prevent current from flowing into the N-well or the substrate. Thus, the high impedance state is maintained even with the output voltage beyond the supplies. With no minority carrier current flowing into the N-well or substrate, latchup is virtually eliminated under power-up or power-down conditions. VCC VCC SD3 P1 P1 D1 D1 OUTPUT LOGIC SD4 N1 D2 LTC485 • F09 Figure 9. LTC485 Output Stage OUTPUT LOGIC N1 D2 LTC485 • F10 Figure 10. Conventional CMOS Output Stage 7 LTC485 U U W U APPLICATIO S I FOR ATIO The LTC485 output stage will maintain a high impedance state until the breakdown of the N-channel or P-channel is reached when going positive or negative respectively. The output will be clamped to either VCC or ground by a Zener voltage plus a Schottky diode drop, but this voltage is way beyond the RS485 operating range. This clamp protects the MOS gates from ESD voltages well over 2000V. Because the ESD injected current in the N-well or substrate consists of majority carriers, latchup is prevented by careful layout techniques. Propagation Delay Many digital encoding schemes are dependent upon the difference in the propagation delay times of the driver and the receiver. Using the test circuit of Figure 13, Figures 11 and 12 show the typical LTC485 receiver propagation delay. The receiver delay times are: tPLH – tPHL = 9ns Typ, VCC = 5V The driver skew times are: Skew = 5ns Typ, VCC = 5V 10ns Max, VCC = 5V, TA = – 40°C to 85°C A A DRIVER OUTPUTS DRIVER OUTPUTS B B RECEIVER OUTPUT RECEIVER OUTPUT RO RO LTC485 • F11 LTC485 • F12 Figure 11. Receiver tPHL Figure 12. Receiver tPLH 100pF TTL IN t r, t f < 6ns D BR R R 100Ω RECEIVER OUT LTC485 • F13 100pF Figure 13. Receiver Propagation Delay Test Circuit 8 LTC485 U U W U APPLICATIO S I FOR ATIO LTC485 Line Length vs Data Rate The maximum line length allowable for the RS422/RS485 standard is 4000 feet. Figures 17 and 18 show that the LTC485 is able to comfortably drive 4000 feet of wire at 110kHz. RO 100Ω C A LTC485 D B TTL IN NOISE GENERATOR LTC485 TTL OUT COMMON-MODE VOLTAGE (A + B)/2 4000 FT 26AWG TWISTED PAIR DI LTC485 • F17 Figure 14. Line Length Test Circuit Figure 17. System Common-Mode Voltage at 110kHz Using the test circuit in Figure 14, Figures 15 and 16 show that with ~ 20VP-P common-mode noise injected on the line, The LTC485 is able to reconstruct the data stream at the end of 4000 feet of twisted pair wire. RO COMMON-MODE VOLTAGE (A – B) RO DI COMMON-MODE VOLTAGE (A + B)/2 LTC485 • F18 Figure 18. System Differential Voltage at 110kHz DI LTC485 • F15 When specifying line length vs maximum data rate the curve in Figure 19 should be used: Figure 15. System Common-Mode Voltage at 19.2kHz CABLE LENGTH (FT) 10k RO DIFFERENTIAL VOLTAGE A – B DI 1k 100 10 10k LTC485 • F16 Figure 16. System Differential Voltage at 19.2kHz 100k 1M 2.5M MAXIMUM DATA RATE 10M LTC485 • F19 Figure 19. Cable Length vs Maximum Data Rate 9 LTC485 U TYPICAL APPLICATIO S Typical RS485 Network Rt Rt LTC485 • TA03 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. J8 Package 8-Lead Ceramic DIP 0.005 (0.127) MIN 0.405 (10.287) MAX 8 7 6 5 0.025 (0.635) RAD TYP 0.220 – 0.310 (5.588 – 7.874) 1 CORNER LEADS OPTION (4 PLCS) 0.023 – 0.045 (0.584 – 1.143) HALF LEAD OPTION 0.045 – 0.068 (1.143 – 1.727) FULL LEAD OPTION 2 3 4 0.200 (5.080) MAX 0.290 – 0.320 (7.366 – 8.128) 0.015 – 0.060 (0.381 – 1.524) 0.008 – 0.018 (0.203 – 0.457) 0.385 ± 0.025 (9.779 ± 0.635) NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP OR TIN PLATE LEADS. 0° – 15° 0.045 – 0.068 (1.143 – 1.727) 0.014 – 0.026 (0.360 – 0.660) 0.125 3.175 0.100 ± 0.010 MIN (2.540 ± 0.254) J8 0293 10 LTC485 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead Plastic DIP 0.400 (10.160) MAX 8 7 6 5 0.250 ± 0.010 (6.350 ± 0.254) 1 0.300 – 0.320 (7.620 – 8.128) ( 8.255 +0.635 –0.381 ) 4 3 0.130 ± 0.005 (3.302 ± 0.127) 0.045 – 0.065 (1.143 – 1.651) 0.065 (1.651) TYP 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 2 0.125 (3.175) MIN 0.045 ± 0.015 (1.143 ± 0.381) 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 0.020 (0.508) MIN N8 0392 S8 Package 8-Lead Plastic SOIC 0.189 – 0.197 (4.801 – 5.004) 8 7 6 5 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157 (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0°– 8° TYP 0.016 – 0.050 0.406 – 1.270 0.014 – 0.019 (0.355 – 0.483) 0.050 (1.270) BSC Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 0392 11 LTC485 U.S. Area Sales Offices NORTHEAST REGION Linear Technology Corporation One Oxford Valley 2300 E. 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Iidabashi, Chiyoda-Ku Tokyo, 102 Japan Phone: 81-3-3237-7891 FAX: 81-3-3237-8010 World Headquarters Linear Technology Corporation 1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507 06/24/93 12 Linear Technology Corporation LT/GP 0294 5K REV E • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7487 (408) 432-1900 ● FAX: (408) 434-0507 ● TELEX: 499-3977 LINEAR TECHNOLOGY CORPORATION 1994