CYDC128B16 1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuMoBL Dual-Port Static RAM Features ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ Full asynchronous operation ■ 4/8/16 K × 16 and 8/16 K × 8 organization ■ Pin select for master or slave ■ High speed access: 40 ns ■ Expandable data bus to 32 bits with master/slave chip select when using more than one device ■ Ultra low operating power ❐ Active: ICC = 15 mA (typical) at 55 ns ❐ Active: ICC = 25 mA (typical) at 40 ns ❐ Standby: ISB3 = 2 A (typical) ■ On-chip arbitration logic ■ On-chip semaphore logic ■ Input read registers (IRR) and output drive registers (ODR) ■ Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os ■ INT flag for port-to-port communication ■ Pb-free 14 × 14 × 1.4 mm 100-pin Thin Quad Flat Pack (TQFP) Package ■ Separate upper byte and lower byte control ■ Commercial and industrial temperature ranges Selection Guide for VCC = 1.8 V Description Port I/O Voltages (P1-P2) CYDC128B16 –40 CYDC128B16 –55 1.8 V-1.8 V 1.8 V-1.8 V Unit Maximum Access Time 40 55 ns Typical Operating Current 25 15 mA Typical Standby Current for ISB1 2 2 A Typical Standby Current for ISB3 2 2 A CYDC128B16 –40 CYDC128B16 –55 Unit 2.5 V-2.5 V 2.5 V-2.5 V Selection Guide for VCC = 2.5 V Description Port I/O Voltages (P1-P2) Maximum Access Time 40 55 ns Typical Operating Current 39 28 mA Typical Standby Current for ISB1 6 6 A Typical Standby Current for ISB3 4 4 A CYDC128B16 –40 CYDC128B16 –55 Unit 3.0 V-3.0 V 3.0 V-3.0 V Selection Guide for VCC = 3.0 V Description Port I/O Voltages (P1-P2) Maximum Access Time 40 55 ns Typical Operating Current 49 42 mA Typical Standby Current for ISB1 7 7 A Typical Standby Current for ISB3 6 6 A Cypress Semiconductor Corporation Document Number: 001-01638 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 408-943-2600 Revised March 7, 2014 CYDC128B16 Top Level Block Diagram[1, 2] I/O[15:0]R I/O[15:0]L UBR UBL LBL LBR IO Control IO Control 16K X 16 Dual Ported Array Address Decode Address Decode A[13:0]L CE L A [13:0]R CE R Interrupt Arbitration Semaphore OE L R/W L SEML BUSY L INTL IRR0 ,IRR1 Mailboxes INTR CEL OEL R/WL OE R R/W R SEMR BUSY R M/S Input Read Register and Output Drive Register CE R OE R R/W R ODR0 - ODR4 SFEN Notes 1. A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices. 2. BUSY is an output in master mode and an input in slave mode. Document Number: 001-01638 Rev. *I Page 2 of 31 CYDC128B16 Contents Pin Configurations .............................................................4 Pin Definitions ....................................................................5 Functional Description .......................................................6 Power Supply ................................................................6 Write Operation .............................................................6 Read Operation .............................................................6 Interrupts .......................................................................6 Busy ..............................................................................6 Master/Slave .................................................................6 Input Read Register ......................................................7 Output Drive Register ....................................................7 Semaphore Operation ...................................................7 Architecture ........................................................................8 Maximum Ratings .............................................................10 Operating Range ...............................................................10 Electrical Characteristics for VCC = 1.8 V ......................10 Electrical Characteristics for VCC = 2.5 V ......................12 Electrical Characteristics for 3.0 V .................................13 Capacitance ......................................................................14 AC Test Loads and Waveforms .......................................14 Document Number: 001-01638 Rev. *I Switching Characteristics for VCC = 1.8V ......................15 Switching Characteristics for VCC = 2.5 V .....................17 Switching Characteristics for VCC = 3.0 V .....................19 Switching Waveforms ......................................................21 CEL Valid First[65] ........................................................25 Left Address Valid First ..............................................25 Ordering Information ........................................................27 8 K × 16 1.8 V Asynchronous Dual-Port SRAM ..........27 Ordering Code Defintions ............................................27 Package Diagram ..............................................................28 Acronyms ..........................................................................29 Document Conventions ...................................................29 Units of Measure .........................................................29 Document History Page ...................................................30 Sales, Solutions, and Legal Information ........................31 Worldwide Sales and Design Support .........................31 Products ......................................................................31 PSoC® Solutions ........................................................31 Cypress Developer Community ...................................31 Technical Support .......................................................31 Page 3 of 31 CYDC128B16 Pin Configurations A3R A2R A1R A0R UBR LBR OER R/WR VSS ODR4 ODR3 ODR2 VSS ODR1 ODR0 VSS SFEN R/WL OEL LBL UBL A0L A1L A2L A3L Figure 1. 100-Pin TQFP pinout (Top View) [3] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A4L 1 75 A4R A5L 2 74 A5R A6L 3 73 A6R A7L 4 72 A7R A8L 5 71 A8R CEL 6 70 CER SEML 7 69 SEMR INTL 8 68 INTR BUSYL 9 67 BUSYR A9L 10 66 A9R A10L 11 65 A10R VSS 12 64 VSS VCC 13 63 VCC A11L 14 62 A11R A12L[3] 15 61 A12R[3] IRR0[5] 16 60 IRR1[6] M/S 17 59 NC[7] VDDIOL 18 58 VDDIOR I/O0L 19 57 I/O15R I/O1L 20 56 I/O14R I/O2L 21 55 I/O13R VSS 22 54 VSS I/O3L 23 53 I/O12R I/O4L 24 52 I/O11R I/O5L 25 51 I/O10R CYDC128B16 I/O9R I/O8R VDDIOR I/O7R I/O6R I/O5R VSS I/O4R I/O3R I/O2R I/O1R I/O0R NC[7] I/O15L I/O14L I/O13L I/O12L I/O11L VSS I/O10L I/O9L I/O8L VDDIOL I/O7L I/O6L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note 3. Leave this pin unconnected. No trace or power component can be connected to this pin. Document Number: 001-01638 Rev. *I Page 4 of 31 CYDC128B16 Pin Definitions Left Port Right Port Description CEL CER Chip enable R/WL R/WR Read/write enable OEL OER Output enable A0L–A13L A0R–A13R Address (A0–A11 for 4k devices; A0–A12 for 8k devices; A0–A13 for 16k devices). I/O0L–I/O15L I/O0R–I/O15R Data bus input/output for x16 devices; I/O0–I/O7 for x8 devices. SEML SEMR Semaphore enable UBL UBR Upper byte select (I/O8–I/O15 for x16 devices; Not applicable for x8 devices). LBL LBR Lower byte select (I/O0–I/O7 for x16 devices; Not applicable for x8 devices). INTL INTR Interrupt flag BUSYL BUSYR Busy flag IRR0, IRR1 ODR0-ODR4 Input read register (IRR) for CYDC128B16. Output drive register; these outputs are Open Drain. SFEN Special function enable M/S Master or slave select VCC Core power GND Ground VDDIOL Left port I/O voltage VDDIOR Right port I/O voltage NC Document Number: 001-01638 Rev. *I No connect. Leave this pin unconnected. Page 5 of 31 CYDC128B16 Functional Description The CYDC128B16 is a low power complementary metal oxide semiconductor (CMOS) 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAM. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Enable (CE) pin. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (1FFF for the CYDC128B16) is the mailbox for the right port and the second highest memory location (1FFE for the CYDC128B16) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. On power up, an initialization program should be run and the interrupts for both ports must be read to reset them. The operation of the interrupts and their interaction with Busy are summarized in Table 2. The CYDC128B16 are available in 100-pin TQFP packages. Busy Power Supply Each port can operate on independent I/O voltages. This is determined by what is connected to the VDDIOL and VDDIOR pins. The supported I/O standards are 1.8-V/2.5-V LVCMOS and 3.0-V LVTTL. The CYDC128B16 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port gets that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Write Operation Master/Slave Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 6 on page 22) or the CE pin (see Figure 7 on page 22). Required inputs for non-contention operations are summarized in Table 1. A M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. The core voltage (VCC) can be 1.8 V, 2.5 V or 3.0 V, as long as it is lower than or equal to the I/O voltage. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Document Number: 001-01638 Rev. *I Page 6 of 31 CYDC128B16 Input Read Register The Input Read Register (IRR) captures the status of two external input devices that are connected to the Input Read pins. The contents of the IRR read from address x0000 from either port. During reads from the IRR, DQ0 and DQ1 are valid bits and DQ<15:2> are don’t care. Writes to address x0000 are not allowed from either port. Address x0000 is not available for standard memory accesses when SFEN = VIL. When SFEN = VIH, address x0000 is available for memory accesses. The inputs will be 1.8-V/2.5-V LVCMOS or 3.0-V LVTTL, depending on the core voltage supply (VCC). Refer to Table 3 for Input Read Register operation. Output Drive Register The Output Drive Register (ODR) determines the state of up to five external binary state devices by providing a path to VSS for the external circuit. These outputs are Open Drain. The five external devices can operate at different voltages (1.5 V VDDIO 3.5 V) but the combined current cannot exceed 40 mA (8 mA max for each external device). The status of the ODR bits are set using standard write accesses from either port to address x0001 with a “1” corresponding to on and “0” corresponding to off. The status of the ODR bits can be read with a standard read access to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for memory accesses. When SFEN = VIH, the ODR is inactive and address x0001 can be used for standard accesses. During reads and writes to ODR DQ<4:0> are valid and DQ<15:5> are don’t care. Refer to Table 4 for Output Drive Register operation. Semaphore Operation The CYDC128B16 provides eight semaphore latches that are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. Document Number: 001-01638 Rev. *I For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 5 shows sample semaphore operations. When reading a semaphore, all 16/8 data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side controls the semaphore. On power up, both ports should write “1” to all eight semaphores. Page 7 of 31 CYDC128B16 Architecture port-to-port communication. Two Semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the device can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The device also has an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. The CYDC128B16 consists of an array of 4k, 8k, or 16k words of 16 dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be used for Table 1. Non-Contending Read/Write Outputs[4] Inputs UB LB SEM I/O8–I/O15 Operation CE R/W OE I/O0–I/O7 H X X X X H High Z High Z Deselected: power down X X X H H H High Z High Z Deselected: power down L L X L H H Data In High Z Write to upper byte only L L X H L H High Z Data In Write to lower byte only L L X L L H Data In Data In Write to both bytes L H L L H H Data Out High Z Read upper byte only L H L H L H High Z Data Out Read lower byte only L H L L L H Data Out Data Out Read both bytes X X H X X X High Z High Z Outputs disabled H H L X X L Data Out Data Out Read data in semaphore flag X H L H H L Data Out Data Out Read data in semaphore flag H X X X L Data In Data In Write DIN0 into semaphore flag X X H H L Data In Data In Write DIN0 into semaphore flag L X X L X L Not allowed L X X X L L Not allowed Table 2. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH) [5] Function Left Port R/WL CEL Right Port OEL A0L–13L INTL R/WR CER OER A0R–13R INTR X X X X X L[7] X L L 3FFF[6] H[8] X X Set right INTR flag L L X 3FFF[6] Reset right INTR flag X X X X X X X L[8] L L X 3FFE[6] L 3FFE[6] H[7] X X X X Set left INTL flag Reset left INTL flag X X X L Notes 4. This column applies to x16 devices only. 5. See Interrupts Functional Description for specific highest memory locations by device. 6. See Functional Description for specific addresses by device. 7. If BUSYL = L, then no change. 8. If BUSYR = L, then no change. Document Number: 001-01638 Rev. *I Page 8 of 31 CYDC128B16 Table 3. Input Read Register Operation[9, 10] SFEN H L CE L L R/W OE H UB L H LB L L ADDR L I/O0–I/O1 I/O2–I/O15 [11] VALID[11] [12] X x0000-Max VALID X L x0000 UB LB ADDR VALID Mode Standard memory access IRR read Table 4. Output Drive Register [13] SFEN CE R/W OE X [14] L [11] I/O0–I/O4 I/O5–I/O15 Mode [11] [11] x0000-Max VALID VALID Standard memory access [11] L H L H L L L X X L x0001 VALID[12] X ODR write[13, 15] L L H L X L x0001 VALID[12] X ODR read[13] Table 5. Semaphore Operation Example Function I/O0–I/O15 Left I/O0–I/O15 Right No action 1 1 Status Semaphore-free Left port writes 0 to semaphore 0 1 Left port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore-free Notes 9. SFEN = VIL for IRR reads. 10. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH. 11. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid. 12. LB must be active (LB = VIL) for these bits to be valid. 13. SFEN = VIL for ODR reads and writes. 14. Output enable must be low (OE = VIL) during reads for valid data to be output. 15. During ODR writes data will also be written to the memory. Document Number: 001-01638 Rev. *I Page 9 of 31 CYDC128B16 Maximum Ratings Output current into outputs (LOW) .............................. 90 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.[16] Storage temperature .................................. –65°C to +150°C Static discharge voltage.......................................... > 2000 V Latch up current..................................................... > 200 mA Operating Range Ambient temperature with power applied ............................................. –55°C to +125°C Range Ambient Temperature VCC 0°C to +70°C 1.8 V ± 100 mV 2.5 V ± 100 mV 3.0 V ± 300 mV –40°C to +85°C 1.8 V ± 100 mV 2.5 V ± 100 mV 3.0 V ± 300 mV Commercial Supply voltage to ground potential ...............–0.5 V to +3.3 V DC voltage applied to outputs in High-Z State ........................ –0.5 V to VCC + 0.5 V Industrial DC input voltage[17] ............................. –0.5 V to VCC + 0.5 V Electrical Characteristics for VCC = 1.8 V Over the Operating Range Parameter VOL VOL ODR VIH VIL IOZ ICEX ODR CYDC128B16 -40 -55 Description P1 I/O Voltage VOH CYDC128B16 P2 I/O Voltage Min Typ Max Min Unit Typ Max Output HIGH voltage (IOH = –100 A) 1.8 V (any port) VDDIO – 0.2 VDDIO – 0.2 V Output HIGH voltage (IOH = –2 mA) 2.5 V (any port) 2.0 2.0 V Output HIGH voltage (IOH = –2 mA) 3.0 V (any port) 2.1 2.1 V Output LOW voltage (IOL = 100 A 1.8 V (any port) 0.2 0.2 V Output HIGH voltage (IOL = 2 mA) 2.5 V (any port) 0.4 0.4 V Output HIGH voltage (IOL = 2 mA) 3.0 V (any port) 0.4 0.4 V ODR Output LOW voltage| (IOL = 8 mA 1.8 V (any port) 0.2 0.2 V 2.5 V (any port) 0.2 0.2 V 3.0 V (any port) 0.2 0.2 V Input HIGH voltage Input LOW voltage Output leakage current ODR output leakage current. VOUT = VDDIO 1.8 V (any port) 1.2 VDDIO + 0.2 1.2 VDDIO + 0.2 V 2.5 V (any port) 1.7 VDDIO + 0.3 1.7 VDDIO + 0.3 V 3.0 V (any port) 2.0 VDDIO + 0.2 2.0 VDDIO + 0.2 V 1.8 V (any port) –0.2 0.4 –0.2 0.4 V 2.5 V (any port) –0.3 0.6 –0.3 0.6 V 3.0 V (any port) –0.2 0.7 –0.2 0.7 V 1.8 V 1.8 V –1 1 –1 1 A 2.5 V 2.5 V –1 1 –1 1 A 3.0 V 3.0 V –1 1 –1 1 A 1.8 V 1.8 V –1 1 –1 1 A 2.5 V 2.5 V –1 1 –1 1 A 3.0 V 3.0 V –1 1 –1 1 A Notes 16. The voltage on any input or I/O pin can not exceed the power pin during power-up. 17. Pulse width < 20 ns. Document Number: 001-01638 Rev. *I Page 10 of 31 CYDC128B16 Electrical Characteristics for VCC = 1.8 V (continued) Over the Operating Range Parameter IIX Description Input leakage current P1 I/O Voltage P2 I/O Voltage Min 1.8 V 1.8 V –1 CYDC128B16 CYDC128B16 -40 -55 Typ Unit Max Min Typ Max 1 –1 1 A 2.5 V 2.5 V –1 1 –1 1 A 3.0 V 3.0 V –1 1 –1 1 A ICC Operating current (VCC Industrial = Max, IOUT = 0 mA) Outputs Disabled 1.8 V 1.8 V 25 40 15 25 mA ISB1 Standby current (both Ports TTL Level) CEL and CER VCC – 0.2, SEML = SEMR = VCC – 0.2, f = fMAX Industrial 1.8 V 1.8 V 2 6 2 6 A ISB2 Standby current (one port TTL level) CEL | CER VIH, f = fMAX Industrial 1.8 V 1.8 V 8.5 18 8.5 14 mA ISB3 Standby current (both Industrial ports CMOS level) CEL and CER VCC 0.2V, SEML and SEMR > VCC – 0.2V, f = 0 1.8 V 1.8 V 2 6 2 6 A ISB4 Standby current (one Industrial port CMOS level) CEL | [18] CER VIH, f = fMAX 1.8 V 1.8 V 8.5 18 8.5 14 mA Note 18. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 001-01638 Rev. *I Page 11 of 31 CYDC128B16 Electrical Characteristics for VCC = 2.5 V Over the Operating Range Parameter VOL VOL ODR VIH VIL IOZ ICEX ODR IIX CYDC128B16 -40 -55 Description P1 I/O Voltage VOH CYDC128B16 P2 I/O Voltage Min Typ Max Min Typ Unit Max Output HIGH voltage (IOH = –2 mA) 2.5 V (any port) 2.0 2.0 Output HIGH voltage (IOH = –2 mA) 3.0 V (any port) 2.1 2.1 Output LOW voltage (IOL = 2 mA 2.5 V (any port) 0.4 0.4 V Output LOW voltage (IOL = 2 mA 3.0 V (any port) 0.4 0.4 V ODR Output LOW voltage (IOL = 8 mA 2.5 V (any port) 0.2 0.2 V 3.0 V (any port) 0.2 0.2 V Input HIGH voltage Input LOW voltage Output leakage current ODR output leakage current. VOUT = VCC Input leakage current V V 2.5 V (any port) 1.7 VDDIO + 0.3 1.7 VDDIO + 0.3 V 3.0 V (any port) 2.0 VDDIO + 0.2 2.0 VDDIO + 0.2 V 2.5 V (any port) –0.3 0.6 –0.3 0.6 V 3.0 V (any port) –0.2 0.7 –0.2 0.7 V 2.5 V 2.5 V –1 1 –1 1 A 3.0 V 3.0 V –1 1 –1 1 A 2.5 V 2.5 V –1 1 –1 1 A 3.0 V 3.0 V –1 1 –1 1 A 2.5 V 2.5 V –1 1 –1 1 A 3.0 V 3.0 V –1 1 –1 1 A ICC Operating current (VCC = Max, IOUT = 0 mA) Outputs disabled Industrial 2.5 V 2.5 V 39 55 28 40 mA ISB1 Standby current (both ports TTL Industrial level) CEL and CER VCC – 0.2, SEM L= SEMR = VCC – 0.2, f=fMAX 2.5 V 2.5 V 6 8 6 8 A ISB2 Standby current (one port TTL level) CEL | CER VIH, f = fMAX Industrial 2.5 V 2.5 V 21 30 18 25 mA ISB3 Standby current (both ports CMOS level) CEL and CER VCC 0.2V, SEML and SEMR > VCC – 0.2V, f = 0 Industrial 2.5 V 2.5 V 4 6 4 6 A ISB4 Standby current (one port CMOS Industrial level) CEL | CER VIH, f = fMAX[19] 2.5 V 2.5 V 21 30 18 25 mA Note 19. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 001-01638 Rev. *I Page 12 of 31 CYDC128B16 Electrical Characteristics for 3.0 V Over the Operating Range Parameter Description CYDC128B16 CYDC128B16 -40 -55 P1 I/O P2 I/O Voltage Voltage Min 2.1 VOH Output HIGH voltage (IOH = –2 mA) 3.0 V (any port) VOL Output LOW voltage (IOL = 2 mA) 3.0 V (any port) Typ Max Min Typ Unit Max 2.1 V 0.4 0.2 0.4 V VOL ODR ODR output LOW voltage (IOL = 8 mA 3.0 V (any port) 0.2 V VIH Input HIGH voltage 3.0 V (any port) 2.0 VDDIO + 0.2 2.0 VDDIO + 0.2 V VIL Input LOW voltage 3.0 V (any port) –0.2 0.7 –0.2 0.7 V IOZ Output leakage current 3.0 V 3.0 V –1 1 –1 1 A ICEX ODR ODR output leakage current. VOUT = VCC 3.0 V 3.0 V –1 1 –1 1 A IIX Input leakage current 3.0V 3.0 V –1 1 –1 1 A ICC Operating current (VCC = Max, Industrial IOUT = 0 mA) Outputs disabled 3.0V 3.0 V 49 70 42 60 mA ISB1 Standby current (both ports TTL Industrial Level) CEL and CER VCC – 0.2, SEML = SEMR = VCC – 0.2, f = fMAX 3.0 V 3.0 V 7 10 7 10 A ISB2 Standby current (one port TTL Industrial Level) CEL | CER VIH, f = fMAX 3.0 V 3.0 V 28 40 25 35 mA ISB3 Standby current (both ports Industrial CMOS Level) CEL and CER VCC 0.2V, SEML and SEMR > VCC – 0.2V, f = 0 3.0 V 3.0 V 6 8 6 8 A ISB4 Standby current (one port Industrial CMOS Level) CEL | CER VIH, f = fMAX[20] 3.0 V 3.0 V 28 40 25 35 mA Note 20. MAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document Number: 001-01638 Rev. *I Page 13 of 31 CYDC128B16 Capacitance Parameter[21] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.0V Max Unit 9 pF 10 pF AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms 3.0 V/2.5 V/1.8 V 3.0V/2.5V/1.8V R1 RTH = 6 k OUTPUT OUTPUT R1 OUTPUT C = 30 pF C = 30 pF R2 VTH = 0.8 V (a) Normal Load (Load 1) 3.0V/2.5V 1.8V R1 1022 13500 R2 792 10800 (b) Thévenin Equivalent (Load 1) GND 10% 90% 3 ns R2 (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig) ALL INPUT PULSES 1.8V C = 5 pF 90% 10% 3 ns Note 21. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-01638 Rev. *I Page 14 of 31 CYDC128B16 Switching Characteristics for VCC = 1.8V Over the Operating Range [22] CYDC128B16 Parameter Description CYDC128B16 -40 Min -55 Max Min Unit Max Read Cycle tRC Read cycle time tAA Address to data valid tOHA Output hold from address change tACE[23] CE LOW to data valid 40 55 ns tDOE OE LOW to data valid 25 30 ns 25 ns tLZOE [24, 25, 26] OE Low to Low Z tHZOE[24, 25, 26] OE HIGH to High Z tLZCE[24, 25, 26] CE LOW to Low Z tHZCE[24, 25, 26] tPU[26] tPD[26] tABE[23] CE HIGH to High Z CE LOW to power up 40 55 40 5 ns 55 5 5 5 15 5 ns 5 15 0 ns ns ns 25 0 ns ns CE HIGH to power down 40 55 ns Byte enable access time 40 55 ns Write Cycle tWC Write cycle time 40 55 ns tSCE[23] CE LOW to write end 30 45 ns tAW Address valid to write end 30 45 ns tHA Address hold from write end 0 0 ns tSA[23] Address setup to write start 0 0 ns tPWE Write pulse width 25 40 ns tSD Data setup to write end 20 30 ns tHD Data hold from write end 0 0 ns tHZWE[25, 26] tLZWE[25, 26] tWDD[27] tDDD[27] R/W LOW to High Z R/W HIGH to Low Z 15 0 25 0 ns ns Write pulse to data delay 55 80 ns Write data valid to read data valid 55 80 ns Notes 22. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOI/IOH and 30-pF load capacitance. 23. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 24. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 25. Test conditions used are Load 3. 26. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 27. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document Number: 001-01638 Rev. *I Page 15 of 31 CYDC128B16 Switching Characteristics for VCC = 1.8V (continued) Over the Operating Range [22] Parameter CYDC128B16 CYDC128B16 -40 -55 Description Min Max Min Unit Max Busy Timing[28] tBLA BUSY LOW from address match 30 45 ns tBHA BUSY HIGH from address mismatch 30 45 ns tBLC BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tPS[29] Port setup for priority 5 5 ns tWB R/W HIGH after BUSY (Slave) 0 0 ns tWH R/W HIGH after BUSY HIGH (Slave) 20 tBDD[30] BUSY HIGH to data valid 35 ns 30 40 ns Interrupt Timing[28] tINS INT set time 35 45 ns tINR INT reset time 35 45 ns Semaphore Timing tSOP SEM flag update pulse (OE or SEM) 10 15 ns tSWRD SEM flag write to read time 10 10 ns tSPS SEM flag contention window 10 tSAA SEM address access time 10 40 ns 55 ns Notes 28. Test conditions used are Load 2. 29. Add 2ns to this value when the I/O ports are operating at different voltages. 30. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document Number: 001-01638 Rev. *I Page 16 of 31 CYDC128B16 Switching Characteristics for VCC = 2.5 V Over the Operating Range Parameter CYDC128B16 CYDC128B16 -40 -55 Description Min Max Min Unit Max Read Cycle tRC Read cycle time tAA Address to data valid tOHA Output hold from address change tACE[31] CE LOW to data valid 40 55 ns tDOE OE LOW to data valid 25 30 ns tLZOE[32, 33, 34] OE LOW to low Z tHZOE[32, 33, 34] tLZCE[32, 33, 34] tHZCE[32, 33, 34] tPU[34] tPD[34] tABE[31] OE HIGH to high Z CE LOW to low Z 40 40 5 ns 55 5 2 2 ns 15 2 15 0 ns ns 2 15 CE HIGH to high Z CE LOW to power up 55 ns ns 15 0 ns ns CE HIGH to power down 40 55 ns Byte enable access time 40 55 ns Write Cycle tWC Write cycle time 40 55 ns tSCE[31] CE LOW to write end 30 45 ns tAW Address valid to write end 30 45 ns tHA Address hold from write end 0 0 ns tSA[31] Address setup to write start 0 0 ns tPWE Write pulse width 25 40 ns tSD Data setup to write end 20 30 ns tHD Data hold from write end 0 0 ns tHZWE[33, 34] tLZWE[33, 34] tWDD[35] tDDD[35] R/W LOW to high Z R/W HIGH to low Z 15 0 25 0 ns ns Write pulse to data delay 55 80 ns Write data valid to read data valid 55 80 ns Notes 31. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 32. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 33. Test conditions used are Load 3. 34. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 35. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document Number: 001-01638 Rev. *I Page 17 of 31 CYDC128B16 Switching Characteristics for VCC = 2.5 V (continued) Over the Operating Range CYDC128B16 Parameter Description CYDC128B16 -40 Min -55 Max Min Unit Max Busy Timing[36] tBLA BUSY LOW from address match tBHA BUSY HIGH from address mismatch 30 45 ns tBLC BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tPS[37] Port set up for priority tWB R/W HIGH after BUSY (Slave) tWH R/W HIGH after BUSY HIGH (Slave) tBDD[38] 30 5 45 ns 5 ns 0 0 ns 20 35 ns BUSY HIGH to data valid 30 40 ns [36] Interrupt Timing tINS INT set time 35 45 ns tINR INT reset time 35 45 ns Semaphore Timing tSOP SEM flag update pulse (OE or SEM) 10 15 ns tSWRD SEM flag write to read time 10 10 ns tSPS SEM Flag Contention Window 10 10 ns tSAA SEM Address Access Time 40 55 ns Notes 36. Test conditions used are Load 2. 37. Add 2ns to this value when the I/O ports are operating at different voltages. 38. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document Number: 001-01638 Rev. *I Page 18 of 31 CYDC128B16 Switching Characteristics for VCC = 3.0 V Over the Operating Range Parameter CYDC128B16 CYDC128B16 -40 -55 Description Min Max Min Unit Max Read Cycle tRC Read cycle time tAA Address to data valid tOHA Output hold from address change tACE[39] CE LOW to data valid tDOE OE LOW to data valid tLZOE[40, 41, 42] OE Low to low Z tHZOE[40, 41, 42] tLZCE[40, 41, 42] tHZCE[40, 41, 42] tPU[42] tPD[42] tABE[39] OE HIGH to high Z CE LOW to low Z 40 5 ns 55 5 40 25 1 1 55 ns 30 ns ns 15 1 15 0 ns ns 1 15 CE HIGH to high Z CE LOW to power up 55 40 ns ns 15 0 ns ns CE HIGH to power down 40 55 ns Byte enable access time 40 55 ns Write Cycle tWC Write cycle time 40 55 ns tSCE[39] CE LOW to write end 30 45 ns tAW Address valid to write end 30 45 ns tHA Address hold from write end 0 0 ns tSA[39] Address setup to write start 0 0 ns tPWE Write pulse width 25 40 ns tSD Data setup to write end 20 30 ns tHD Data hold from write end 0 tHZWE[41, 42] R/W LOW to high Z tLZWE[41, 42] R/W HIGH to low Z tWDD[43] tDDD[43] Write pulse to data delay 55 80 ns Write data valid to read data valid 55 80 ns 0 15 0 ns 25 0 ns ns Notes 39. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 40. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 41. Test conditions used are Load 3. 42. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 43. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document Number: 001-01638 Rev. *I Page 19 of 31 CYDC128B16 Switching Characteristics for VCC = 3.0 V (continued) Over the Operating Range CYDC128B16 Parameter Description -40 Min Busy Timing CYDC128B16 Unit -55 Max Min Max [44] tBLA BUSY LOW from address match tBHA BUSY HIGH from address mismatch 30 45 ns tBLC BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tPS[45] Port set up for priority tWB R/W HIGH after BUSY (Slave) tWH R/W HIGH after BUSY HIGH (Slave) tBDD[46] 30 5 45 ns 5 ns 0 0 ns 20 35 ns BUSY HIGH to data valid 30 40 ns [44] Interrupt Timing tINS INT set time 35 45 ns tINR INT reset time 35 45 ns Semaphore Timing tSOP SEM flag update pulse (OE or SEM) 10 15 ns tSWRD SEM flag write to read time 10 10 ns tSPS SEM flag contention window 10 10 ns tSAA SEM address access time 40 55 ns Notes 44. Test conditions used are Load 2. 45. Add 2ns to this value when the I/O ports are operating at different voltages. 46. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document Number: 001-01638 Rev. *I Page 20 of 31 CYDC128B16 Switching Waveforms Figure 3. Read Cycle No.1 (Either Port Address Access)[47, 48, 49] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No.2 (Either Port CE/OE Access)[47, 50, 51] tACE CE and LB or UB tHZCE tDOE OE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU CURRENT tPD ICC ISB Figure 5. Read Cycle No. 3 (Either Port)[47, 49, 52, 53] tRC ADDRESS tAA tOHA UB or LB tHZCE tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 47. R/W is HIGH for read cycles. 48. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 49. OE = VIL. 50. Address valid prior to or coincident with CE transition LOW. 51. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 52. R/W must be HIGH during all address transitions. 53. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. Document Number: 001-01638 Rev. *I Page 21 of 31 CYDC128B16 Switching Waveforms (continued) Figure 6. Write Cycle No.1: R/W Controlled Timing[52, 53, 54, 55, 56, 57] tWC ADDRESS tHZOE [58] OE tAW CE [56, 57] tPWE[55] tSA tHA R/W tHZWE[58] DATA OUT tLZWE NOTE 59 NOTE 59 tSD tHD DATA IN Figure 7. Write Cycle No. 2: CE Controlled Timing[52, 53, 54, 59] tWC ADDRESS tAW CE [56, 57] tSA tSCE tHA R/W tSD tHD DATA IN Notes 54. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 55. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 56. To access RAM, CE = VIL, SEM = VIH. 57. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 58. Transition is measured 0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 59. During this period, the I/O pins are in the output state, and input signals must not be applied. Document Number: 001-01638 Rev. *I Page 22 of 31 CYDC128B16 Switching Waveforms (continued) Figure 8. Semaphore Read After Write Timing, Either Side[60, 61] tSAA A0–A2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Figure 9. Timing Diagram of Semaphore Contention[62, 63] A0L–A2L MATCH R/WL SEML tSPS A0R–A2R MATCH R/WR SEMR Notes 60. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 61. CE = HIGH for the duration of the above timing (both write and read cycle). 62. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 63. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document Number: 001-01638 Rev. *I Page 23 of 31 CYDC128B16 Switching Waveforms (continued) Figure 10. Timing Diagram of Read with BUSY (M/S=HIGH)[64] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATAOUTL VALID tWDD Figure 11. Write Timing with Busy Input (M/S = LOW) tPWE R/W BUSY tWB tWH Note 64. CEL = CER = LOW. Document Number: 001-01638 Rev. *I Page 24 of 31 CYDC128B16 Switching Waveforms (continued) Figure 12. Busy Timing Diagram No.1 (CE Arbitration) CEL Valid First[65] ADDRESSL,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First ADDRESS L,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Figure 13. Busy Timing Diagram No.2 (Address Arbitration)[65] Left Address Valid First tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Note 65. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document Number: 001-01638 Rev. *I Page 25 of 31 CYDC128B16 Switching Waveforms (continued) Figure 14. Interrupt Timing Diagrams Left Side Sets INTR: ADDRESSL tWC WRITE 1FFF (OR 1/3FFF) tHA[66] CEL R/WL INTR tINS [67] Right Side Clears INTR: tRC READ 1FFF (OR 1/3FFF) ADDRESSR CER tINR [67] R/WR OER INTR Right Side Sets INTL: ADDRESSR tWC WRITE 1FFE (OR 1/3FFE) tHA[66] CER R/WR INTL [67] tINS Left Side Clears INTL: tRC READ 1FFE OR 1/3FFE) ADDRESSR CEL tINR[67] R/WL OEL INTL Notes 66. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 67. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document Number: 001-01638 Rev. *I Page 26 of 31 CYDC128B16 Ordering Information 8 K × 16 1.8 V Asynchronous Dual-Port SRAM Speed (ns) 55 Ordering Code CYDC128B16-55AXI Package Name AZ0AB Package Type 100-pin Pb-free TQFP Operating Range Industrial Ordering Code Defintions Document Number: 001-01638 Rev. *I Page 27 of 31 CYDC128B16 Package Diagram Figure 15. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline, 51-85048 51-85048 *I Document Number: 001-01638 Rev. *I Page 28 of 31 CYDC128B16 Acronyms Document Conventions Acronym Description CE chip enable CMOS complementary metal oxide semiconductor I/O input/output IRR input read registers ODR output drive registers OE output enable SEM semaphore SRAM Units of Measure Symbol Unit of Measure °C degree Celsius Hz hertz kHz kilohertz k kilohm MHz megahertz A microampere F microfarad static random access memory s microsecond TQDP thin quad flat pack mA milliampere WE write enable mm millimeter ms millisecond mV millivolt ns nanosecond ohm % percent pF picofarad V volt W watt Document Number: 001-01638 Rev. *I Page 29 of 31 CYDC128B16 Document History Page Document Title: CYDC128B16 1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuMoBL Dual-Port Static RAM Document Number: 001-01638 Revision ECN Submission Date Orig. of Change Description of Change ** 385185 SEE ECN YDT New data sheet *A 396697 SEE ECN KGH Updated ISB2 and ISB4 typo to mA. Updated tINS and tINR for -55 to 31ns. *B 404777 SEE ECN KGH Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and VOL Replaced -35 speed bin with -40 Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V Included note 34 *C 463014 SEE ECN HKH Changed spec title to from “Consumer Dual-Port” to “ConsuMoBL Dual-Port” Cypress Internet Release *D 505803 SEE ECN HKH Corrected typo in Features and Ordering Info sections. Cypress external web release. *E 735537 SEE ECN HKH Corrected typo in Pg5 power supply section Updated tDDD timing value to be consistent with tWDD *F 2905507 04/06/2010 YDT Removed parts CYDC064B08-55AXI, CYDC064B16-55AXI. Updated package diagram. *G 2930445 05/11/2010 AVF Removed references to inactive parts from the data sheet. Updated template. *H 3183900 02/28/11 ESH Added ordering code definitions. *I 4301267 03/07/2014 HBM Updated Package Diagram: spec 51-85048 – Changed revision from *E to *I. Updated in new template. Completing Sunset Review. Document Number: 001-01638 Rev. *I Page 30 of 31 CYDC128B16 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers Wireless/RF psoc.cypress.com/solutions cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2014. 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Document Number: 001-01638 Rev. *I Revised March 7, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 31 of 31