TC74HC40105AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC40105AP,TC74HC40105AF 4 Bit × 16 Word FIFO Register The TC74HC40105A is a high speed CMOS 4 bit × 16 word first-in, first-out (FIFO) Strage Register fabricated with silicon gate C2MOS technology. It achieves the high speed operation while maintaining the CMOS low power dissipation. The device is capable of handling 16 four-bit words and it is possible to handle the input and output data at different shifting rates. When the DATA-IN-READY (DIR) is high, data is written into the registers by a low to high transition of the SHIFT IN (SI) input. And when DATA-OUT-READY (DOR) is high, data is read out of the registers by a high to low transition of the SHIFT OUT ( SO ) input. If the MASTER RESET (MR) is high, the DIR goes high and DOR goes low. The data in the internal registers are not changed but are declared invalid. The TC74HC40105A can be cascaded to form longer registers or wider words. The DATA OUTPUTs (Qn) are 3-State Outputs. When OUTPUT ENABLE ( OE ) is held high, the Qn’s are in high impedance state. All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC40105AP TC74HC40105AF Weight DIP16-P-300-2.54A SOP16-P-300-1.27A : 1.00 g (typ.) : 0.18 g (typ.) Features • High speed: fmax 25 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads for DIR, DOR 15 LSTTL loads for Q0 to Q3 • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) for DIR, DOR |IOH| = IOL = 6 mA (min) • for Q0 to Q3 ∼ tpHL Balanced propagation delays: tpLH − • Wide operating voltage range: VCC (opr) = 2 to 6 V 1 2007-10-01 TC74HC40105AP/AF Pin Assignment IEC Logic Symbol System Diagram 2 2007-10-01 TC74HC40105AP/AF Timing Chart Z: High impedance Block Diagram 3 2007-10-01 TC74HC40105AP/AF Functional Description (1) (2) (3) (4) Writing data Data can be written into the FIFO whenever DIR is high and a low to high transition occurs on the SI pin. DIR will toggle momentarily until the data has been transferred to the second word register. SI must be toggled before the next 4-bit word can be written. The first and subsequent words will automatically ripple to the output end of the device even if there is not a full 16 words of input data. When all 16 words are filled with data, DIR will go low and additional data cannot be written into the device. Reading data When a data word appears in the sixteenth data register (just before the output buffer), DOR goes high and, if OE is low, data can be output on the high to low transition of SO . The data remaining in the registers now ripples to the next higher word position opening the first word position for new data. DIR goes high and additional data can be written in. During the output of data, DOR toggles momentarily after each read. When the data registers become empty, DOR goes low and SO is ignored. Master rest When a high is input to MR, the internal control logic is initialized. This causes DIR to go high and DOR to go low. The contents of the data registers are not changed, but are invalid and will be written over when the first word is loaded. Cascading The TC74HC40105A can be cascaded to form longer registers simply by connecting DOR of the first device to SI of the second and DIR of the second device to SO of the first. Additional devices may be cascaded by repeating the above. Of course, the Qn outputs of the first device must be connected to the Dn inputs of the second. In this mode, an MR pulse must be applied after the supply voltage is turned on. For words wider than 4-bits, the DIR and DOR outputs from each FIFO must be ANDed respectively and the SI and SO inputs must each be paralleled. Absolute Maximum Ratings (Note 1) Characteristics Symbol Rating Unit Supply voltage range VCC −0.5 to 7 V DC input voltage VIN −0.5 to VCC + 0.5 V VOUT −0.5 to VCC + 0.5 V Input diode current IIK ±20 mA Output diode current IOK ±20 mA DC output voltage DC output current (DIR, DOR) (Q0 to Q3) ±25 IOUT ±35 mA DC VCC/ground current ICC ±75 mA Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW Storage temperature Tstg −65 to 150 °C Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C shall be applied until 300 mW. 4 2007-10-01 TC74HC40105AP/AF Operating Ranges (Note) Characteristics Symbol Rating Unit Supply voltage VCC 2 to 6 V Input voltage VIN 0 to VCC V VOUT 0 to VCC V −40 to 85 °C Output voltage Operating temperature Topr 0 to 1000 (VCC = 2.0 V) Input rise and fall time 0 to 500 (VCC = 4.5 V) tr, tf ns 0 to 400 (VCC = 6.0 V) Note: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Electrical Characteristics DC Characteristics Characteristics High-level input voltage Low-level input voltage Symbol ⎯ VIH VIN = VIH or VIL High-level output voltage VOH (DIR DOR) (Q0 to Q3) VIN = VIH or VIL Low-level output voltage VOL VCC (V) Min Typ. Max Min Max 2.0 1.50 ⎯ ⎯ 1.50 ⎯ 4.5 3.15 ⎯ ⎯ 3.15 ⎯ 6.0 4.20 ⎯ ⎯ 4.20 ⎯ 2.0 ⎯ ⎯ 0.50 ⎯ 0.50 4.5 ⎯ ⎯ 1.35 ⎯ 1.35 6.0 ⎯ ⎯ 1.80 ⎯ 1.80 2.0 1.9 2.0 ⎯ 1.9 ⎯ 4.5 4.4 4.5 ⎯ 4.4 ⎯ 6.0 5.9 6.0 ⎯ 5.9 ⎯ IOH = −4 mA 4.5 4.18 4.31 ⎯ 4.13 ⎯ IOH = −5.2 mA 6.0 5.68 5.80 ⎯ 5.63 ⎯ IOH = −6 mA 4.5 4.18 4.31 ⎯ 4.13 ⎯ IOH = −7.8 mA 6.0 5.68 5.80 ⎯ 5.63 ⎯ 2.0 ⎯ 0.0 0.1 ⎯ 0.1 4.5 ⎯ 0.0 0.1 ⎯ 0.1 6.0 ⎯ 0.0 0.1 ⎯ 0.1 ⎯ VIL Ta = −40 to 85°C Ta = 25°C Test Condition IOH = −20 μA IOL = 20 μA Unit V V V (DIR DOR) IOL = 4 mA 4.5 ⎯ 0.17 0.26 ⎯ 0.33 IOL = 5.2 mA 6.0 ⎯ 0.18 0.26 ⎯ 0.33 (Q0 to Q3) IOL = 6 mA 4.5 ⎯ 0.17 0.26 ⎯ 0.33 IOL = 7.8 mA 6.0 ⎯ 0.18 0.26 ⎯ 0.33 6.0 ⎯ ⎯ ±0.5 ⎯ ±5.0 μA VIN = VIH or VIL V 3-state output off-state current IOZ Input leakage current IIN VIN = VCC or GND 6.0 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA Quiescent supply current ICC VIN = VCC or GND 6.0 ⎯ ⎯ 4.0 ⎯ 40.0 μA VOUT = VCC or GND 5 2007-10-01 TC74HC40105AP/AF Timing Requirements (input: tr = tf = 6 ns) Characteristics Symbol Limit Limit 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 75 95 4.5 ⎯ 15 19 6.0 ⎯ 13 16 2.0 ⎯ 0 0 4.5 ⎯ 0 0 6.0 ⎯ 0 0 2.0 ⎯ 100 125 4.5 ⎯ 20 25 6.0 ⎯ 17 21 2.0 ⎯ 50 65 4.5 ⎯ 10 13 6.0 ⎯ 9 11 2.0 ⎯ 3 2.4 4.5 ⎯ 15 12 6.0 ⎯ 18 13 Test Condition Min Typ. Max Unit ⎯ ⎯ 4 8 ns tpHL ⎯ ⎯ 22 39 ns tpLH ⎯ ⎯ 242 365 ns tpLH ⎯ ⎯ 187 300 ns tpHL ⎯ ⎯ 22 35 ns ⎯ ⎯ 25 39 ns (SI) tW (H) Minimum pulse width tW (L) ( SO ) tW (H) Minimum pulse width tW (L) (MR) tW (H) Minimum hold time (DATA-SI) Minimum removal time (MR-SI) Clock frequency Unit Typ. tW (L) (DATA-SI) Ta = −40 to 85°C VCC (V) Minimum pulse width Minimum set-up time Ta = 25°C Test Condition ⎯ ⎯ ⎯ ⎯ ts ⎯ th ⎯ trem ⎯ f ns ns ns ns ns ns MHz AC Characteristics (CL = 15 pF, VCC = 5 V, Ta = 25°C, input: tr = tf = 6 ns) Characteristics Symbol Output transition time tTLH (DIR, DOR) tTHL Propagation delay time ( SO , MR-DOR) Propagation delay time ( SO -DIR) Propagation delay time (SI-DOR) Propagation delay time (SI-DIR) Propagation delay time tpLH (MR-DIR) tpHL 6 2007-10-01 TC74HC40105AP/AF AC Characteristics (input: tr = tf = 6 ns) Symbol Ta = −40 to 85°C Ta = 25°C Test Condition Characteristics VCC (V) Min Typ. Max Min Max 2.0 ⎯ 21 60 ⎯ 75 4.5 ⎯ 7 12 ⎯ 15 6.0 ⎯ 6 10 ⎯ 13 2.0 ⎯ 24 75 ⎯ 95 4.5 ⎯ 8 15 ⎯ 19 6.0 ⎯ 7 13 ⎯ 16 2.0 ⎯ 84 225 ⎯ 280 4.5 ⎯ 28 45 ⎯ 56 ( SO , MR-DOR) 6.0 ⎯ 24 38 ⎯ 48 Propagation delay time 2.0 ⎯ 798 2000 ⎯ 2500 Output transition time tTLH (Q0 to Q3) tTHL Output transition time tTLH (DIR, DOR) tTHL Propagation delay time CL (pF) ⎯ 50 ⎯ 50 ⎯ tpHL 50 ⎯ 4.5 ⎯ 266 400 ⎯ 500 ( SO -DIR) 6.0 ⎯ 226 340 ⎯ 425 Propagation delay time 2.0 ⎯ 624 1650 ⎯ 2060 tpLH 50 ⎯ 4.5 ⎯ 208 330 ⎯ 412 (SI-DOR) 6.0 ⎯ 177 280 ⎯ 350 Propagation delay time 2.0 ⎯ 78 200 ⎯ 250 4.5 ⎯ 26 40 ⎯ 50 6.0 ⎯ 22 34 ⎯ 43 2.0 ⎯ 156 400 ⎯ 500 4.5 ⎯ 52 80 ⎯ 100 6.0 ⎯ 44 68 ⎯ 85 2.0 ⎯ 171 440 ⎯ 550 4.5 ⎯ 57 88 ⎯ 110 6.0 ⎯ 48 75 ⎯ 94 2.0 ⎯ 612 1500 ⎯ 1875 4.5 ⎯ 204 300 ⎯ 375 6.0 ⎯ 173 255 ⎯ 319 2.0 ⎯ 627 1540 ⎯ 1925 4.5 ⎯ 209 308 ⎯ 385 6.0 ⎯ 178 262 ⎯ 327 2.0 ⎯ 87 225 ⎯ 280 4.5 ⎯ 29 45 ⎯ 56 tpLH 50 ⎯ tpHL 50 (SI-DIR) 50 Propagation delay time tpLH ( SO -Qn) tpHL ⎯ 150 50 Propagation delay time tpLH (SI-Qn) tpHL ⎯ 150 Propagation delay time tpLH (MR-DIR) tpHL ⎯ 50 50 Output enable time tpZL tpZH RL = 1 kΩ 150 Output disable time tpLZ tpHZ RL = 1 kΩ 50 7 6.0 ⎯ 25 38 ⎯ 48 2.0 ⎯ 45 125 ⎯ 155 4.5 ⎯ 15 25 ⎯ 31 6.0 ⎯ 13 21 ⎯ 26 2.0 ⎯ 60 165 ⎯ 205 4.5 ⎯ 20 33 ⎯ 41 6.0 ⎯ 17 28 ⎯ 35 2.0 ⎯ 32 125 ⎯ 155 4.5 ⎯ 16 25 ⎯ 31 6.0 ⎯ 14 21 ⎯ 26 Unit ns ns ns ns ns ns ns ns ns ns ns 2007-10-01 TC74HC40105AP/AF Characteristics Symbol CL (pF) 50 Maximum clock frequency fmax ⎯ 150 Output pulse width tw (H) (DIR) tw (L) Output pulse width tw (H) (DOR) tw (L) Input capacitance Output capacitance Power dissipation capacitance Note: ⎯ 50 ⎯ Ta = −40 to 85°C Ta = 25°C Test Condition 50 VCC (V) Min Typ. Max Min Max 2.0 3 7 ⎯ 2.4 ⎯ 4.5 15 22 ⎯ 12 ⎯ 6.0 18 26 ⎯ 14 ⎯ 2.0 2.6 6 ⎯ 2 ⎯ 4.5 13 20 ⎯ 10 ⎯ 6.0 15 24 ⎯ 12 ⎯ 2.0 ⎯ 95 ⎯ ⎯ ⎯ 4.5 ⎯ 25 ⎯ ⎯ ⎯ 6.0 ⎯ 21 ⎯ ⎯ ⎯ 2.0 ⎯ 95 ⎯ ⎯ ⎯ 4.5 ⎯ 25 ⎯ ⎯ ⎯ 6.0 ⎯ 21 ⎯ ⎯ ⎯ Unit MHz ns ns CIN ⎯ ⎯ 5 10 ⎯ 10 pF COUT ⎯ ⎯ 10 ⎯ ⎯ ⎯ pF ⎯ 300 ⎯ ⎯ ⎯ pF CPD (Note) CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) = CPD･VCC･fIN + ICC 8 2007-10-01 TC74HC40105AP/AF Package Dimensions Weight: 1.00 g (typ.) 9 2007-10-01 TC74HC40105AP/AF Package Dimensions Weight: 0.18 g (typ.) 10 2007-10-01 TC74HC40105AP/AF RESTRICTIONS ON PRODUCT USE 20070701-EN GENERAL • The information contained herein is subject to change without notice. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. 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Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 11 2007-10-01