TI TPS3618

TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
BATTERY-BACKUP SUPERVISOR FOR RAM RETENTION
FEATURES
•
•
•
•
•
•
•
•
•
•
DESCRIPTION
Supply Current of 40 µA (Max)
Battery Supply Current of 100 nA (Max)
Precision 5-V Supply Voltage Monitor, Other
Voltage Options on Request
Backup-Battery Voltage Can Exceed VDD
Watchdog Timer With 800-ms Time-Out
Power-On Reset Generator With Fixed 100-ms
Reset Delay Time
Voltage Monitor for Power-Fail or Low-Battery
Monitoring
Battery Freshness Seal (TPS3617 Only)
8-Pin MSOP Package
Temperature Range: -40°C to 85°C
APPLICATIONS
•
•
•
•
•
•
•
•
•
Fax Machines
Set-Top Boxes
Advanced Voice Mail Systems
Portable Battery Powered Equipment
Computer Equipment
Advanced Modems
Automotive Systems
Portable Long-Time Monitoring Equipment
Point-of-Sale Equipment
MSOP (DGK) Package
(TOP VIEW)
VOUT
VDD
GND
PFI
VBAT
RESET
WDI
PFO
Power
Supply
The TPS3617 and TPS3618 are battery-backup
supervisors that monitor 5 V supplies. They provide a
battery-backup function ideal for applications that
require data retention of CMOS RAM during fault
conditions. When the voltage at VDD drops below a
preset threshold (VIT), the active low push-pull
RESET output asserts, and VOUT switches from VDD
to VBAT. When VDD rises above the trip threshold,
VOUT switches immediately from VBAT to VDD.
The RESET output remains low until the delay time
(td) expires. During power on, RESET is asserted
when the supply voltage (VDD or VBAT) goes higher
than 1.1 V.
The PFI and PFO pins are provided if additional
voltage monitoring is needed. If the voltage at PFI is
less than 1.15 V, the push-pull PFO pin will assert
low. When the voltage at PFI exceeds the threshold
voltage, PFO will go high.
These devices also feature a watchdog timer pin
(WDI) that monitors processor activity and asserts
RESET if the the processor is inactive longer than the
watchdog timeout period. If the watchdog timer is not
used, the WDI pin should be left floating.
The TPS3617 and TPS3618 are available in an 8-pin
MSOP package and are characterized for operation
over a temperature range of -40°C to 85°C.
TPS3617
TPS3618
0.1 µF
VBAT
VDD
External
Source
Microcontroller
or
Microprocessor
RESET
RESET
Rx
WDI
PFI
ACTUAL SIZE
3,05 mm x 4,98 mm
Backup
Battery
I/O
I/O
PFO
Switchover
Capacitor
Ry
VOUT
GND
0.1 µF
VCC
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2004, Texas Instruments Incorporated
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGE INFORMATION (1)
PRODUCT
NOMINAL
SUPPLY
VOLTAGE
THRESHOLD
VOLTAGE (VIT) (2)
SPECIFIED
TEMPERATURE
RANGE
TPS3617-50
ASD
5V
4.55V
-40°C to +125°C
TPS3618-50
(1)
(2)
PACKAGE
MARKING
ANK
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
TPS3617-50DGK
Tube, 80
TPS3617-50DGKR
Tape and Reel, 2500
TPS3618-50DGKT
Tape and Reel, 250
TPS3618-50DGKR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or refer to our
web site at www.ti.com.
For other threshold votages, contact the local TI sales office for availability and lead time.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
Input voltage range, VDD
Input voltage range, PFI pin
Continuous output current at VOUT, IO
TPS3617, TPS3618
UNIT
-0.3 to 7
V
-0.3 to (VDD + 0.3)
V
400
mA
±10
mA
Operating junction temperature range, TJ (2)
-40 to +85
°C
Storage temperature range, TSTG
-65 to +150
°C
+260
°C
All other pins, IO
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
Continuous total power dissipation
(1)
(2)
See Dissipation Rating Table
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Due to the low dissipated power in this device, it is assumed that TJ = TA.
DISSIPATION RATING TABLE
2
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGK
470 mW
3.76 mW/°C
301 mW
241 mW
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
1.65 V ≤ VDD≤ 5.5 V, RLRESET = 1 MΩ, CLRESET = 50 pF, over operating temperature range (TJ = -40°C to +85°C), unless
otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
VDD
Input supply range
IDD
VDD supply current
VBAT
Battery supply range
IBAT
TEST CONDITIONS
MIN
TYP
1.65
40
40
1.5
5.5
-0.1
0.1
VOUT = VBAT
0.5
Input volrage, any input
0
RESET
VOH
High-level output voltage
PFO
VOL
Low-level output voltage
VRES
Power-up reset voltage
RESET PFO
(1)
Normal mode
VOUT
Battery-backup mode
RDS(on)
IO
VDD = 1.8 V, IOH = -400 µA
VDD - 0.2
VDD = 3.3 V, IOH = -2 mA,
VDD = 5 V, IOH = -3 mA
VDD - 0.4
VDD = 1.8 V, IOH = -20 µA
VDD - 0.3
VDD = 3.3 V, IOH = -80 µA,
VDD = 5 V, IOH = -120 µA
VDD - 0.4
VBAT > 1.1 V, or VDD > 1.1 V,
IOL = 20 µA
0.4
VDD - 0.150
IO = 200 mA,VDD = 5 V, VBAT = 0 V
VDD - 0.200
IO = 0.5 mA,VBAT = 1.5 V, VDD = 0 V
VBAT - 0.200
IO = 7.5 mA,VBAT = 3.3 V, VDD = 0 V
VBAT - 0.113
VDD = 5 V
VBAT to VOUT on-resistance
VBAT = 3.3 V
Negative-going input
threshold voltage (2)
VPFI
PFI
VIT hysteresis
VHYS
VIL
WDI low-level input voltage
IIH
WDI high-level input current
IIL
WDI low-level input current
8
15
1.13
1.15
1.65 V < VIT < 2.5 V
20
2.5 V < VIT < 3.5 V
40
3.5 V < VIT < 5.5 V
60
Ω
mA
V
1.17
V
mV
55
0.7 x VDD
0.3 x VDD
(4)
(4)
WDI = VDD = 5 V
150
WDI = 0 V, VDD = 5 V
-150
µA
100
ns/V
25
nA
WDI input transition rise and fall rate, ∆t/∆V
(1)
(2)
(3)
(4)
1
4.55
VDD = 1.8 V
WDI high-level input voltage
IOS
V
12
(3)
VIH
II
0.6
300
TA = -40°C to 85°C
V
V
4.46
PFI hysteresis
VBSW hysteresis
V
0.4
VDD to VOUT on-resistance
TPS3617-50
V/µs
VDD = 3.3 V, IOL = 2 mA,
VDD = 5 V, IOL = 3 mA
VDD - 0.050
µA
1
0.2
IO = 125 mA,VDD = 3.3 V, VBAT = 0 V
V
VDD + 0.3
VDD = 1.8 V, IOL = 400 µA
IO = 8.5 mA,VDD = 1.8 V, VBAT = 0 V
µA
V
Continuous output current at VOUT
VIT
V
VOUT = VBAT
Slew rate at VDD or VBAT
VI
UNIT
5.5
VOUT = VDD
VOUT = VDD
VBAT supply current
MAX
PFI input current
PFO short-circuit current
PFI voltage < VDD
-25
PFO = 0 V, VDD = 1.8 V
-0.3
PFO = 0 V, VDD = 3.3 V
-1.1
PFO = 0 V, VDD = 5 V
-2.4
µA
mA
The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals.
For VDD < 1.6 V, VOUT switches to VBAT regardless of VBAT.
For details on how to optimize current consumption when using WDI, refer to the Watchdog section of this data sheet.
3
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS (continued)
1.65 V ≤ VDD≤ 5.5 V, RLRESET = 1 MΩ, CLRESET = 50 pF, over operating temperature range (TJ = -40°C to +85°C), unless
otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
Ci
TEST CONDITIONS
Input capacitance, any input
MIN
TYP
VI = 0 V to 5 V
MAX
UNIT
5
pF
VDD
VIH = VIT + 0.2 V, VIL = VIT - 0.2 V
6
µs
WDI
VDD > VIT + 0.2 V, VIL = 0.3 x VDD,
VIH = 0.7 x VDD
100
ns
tw
Pulse Width
td
Delay time
VDD ≥ VIT + 0.2 V,
See timing diagram
60
100
140
ms
t(tout)
Watchdog time-out
VDD > VIT + 0.2 V,
See timing diagram
0.48
0.8
1.12
s
tPHL
Propagation (delay) time,
high-to-low-level output
Transition time
VDD to RESET
VIL = VIT - 0.2 V,
VIH = VIT + 0.2 V
2
5
PFI to PFO
VIL = VPFI - 0.2 V,
VIH = VPFI + 0.2 V
3
5
µs
VDD to VBAT
3
µs
TIMING DIAGRAM
VBAT
VDD
VIT
t
VOUT
t
RESET
td
td
t
FUNCTION TABLE
4
VDD > VIT
VDD > VBAT
VOUT
RESET
0
0
VBAT
0
0
1
VDD
0
1
0
VDD
1
1
1
VDD
1
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
PFO FUNCTION TABLE
PFI > VPFI
PFO
0
0
1
1
CONDITION: VDD > VDD(MIN)
TERMINAL FUNCTIONS
TERMINAL
NO.
I/O
GND
NAME
3
I
DESCRIPTION
Ground
PFI
4
I
Power-fail comparator input
PFO
5
O
Power-fail comparator output; asserts low when PFI < 1.15 V
RESET
7
O
Active-low push-pull reset output
VBAT
8
I
Backup-battery input
VDD
2
I
Input supply voltage
VOUT
1
O
Supply output
WDI
6
I
Watchdog input. Should be left floating if not used.
FUNCTIONAL BLOCK DIAGRAM
TPS3617
TPS3618
VBAT
+
_
Switch
Control
VOUT
VDD
Reference
Voltage
or 1.15 V
+
_
RESET
Logic
+
Timer
RESET
GND
Oscillator
−
WDI
PFO
+
PFI
Transition
Detector
Watchdog
Logic
+
Control
40 kΩ
5
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Static drain-source on-state resistance (VDD to VOUT)
vs Output current
3
Static drain-source on-state resistance (VBAT to VOUT)
vs Output current
4
IDD
Supply current
vs Supply voltage
5
VIT
Input threshold voltage at RESET
vs Free-air temperature
rDS(on)
High-level output voltage at RESET
VOH
vs High-level output current
High-level output voltage at PFO
VOL
vs Low-level output current
Minimum pulse duration at VDD
vs Threshold voltage overdrive at VDD
13
Minimum pulse duration at PFI
vs Threshold voltage overdrive at PFI
14
− Static Drain-Source On-State Resistance − Ω
1000
VDD = 3.3 V
VBAT = GND
900
TA = 85°C
800
TA = 25°C
700
TA = 0°C
TA = −40°C
600
500
50
75
100
125
150
IO − Output Current − mA
Figure 1.
175
200
11, 12
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VBAT to VOUT)
vs
OUTPUT CURRENT
r DS(on)
− Static Drain-Source On-State Resistance − m Ω
r DS(on)
9, 10
Low-level output voltage at RESET
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
(VDD to VOUT)
vs
OUTPUT CURRENT
6
6
7, 8
20
VBAT = 3.3 V
17.5
15
TA = 85°C
12.5
TA = 25°C
TA = 0°C
10
7.5
5
2.5
TA = −40°C
4.5
6.5
8.5
10.5
12.5
IO − Output Current − mA
Figure 2.
14.5
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
SUPPLY CURRENT
vs
SUPPLE VOLTAGE
INPUT THRESHOLD VOLTAGE AT RESET
vs
FREE-AIR TEMPERATURE
1.001
30
20
or
TA = 25°C
TA = 0°C
TA = 85°C
15
TA = −40°C
10
5
0
1
2
3
4
VDD − Supply Voltage − V
5
1
0.999
0.998
0.997
0.996
0.995
−40 −30 −20 −10 0 10 20 30 40 50 60 70 80
0
6
TA − Free-Air Temperature − °C
Figure 3.
Figure 4.
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
6
VOH − High-Level Output Voltage at RESET − V
I DD − Supply Current − µ A
25
VDD Mode
VBAT = GND
VIT − Input Threshold Voltage at RESET − V
VBAT Mode
VBAT = 2.6 V
VDD = 5 V
VBAT = GND
5
TA = −40°C
TA = 25°C
4
TA = 0°C
3
TA = 85°C
2
1
0
−35
−30
−25
−20
−15
−10
−5
0
IOH − High-Level Output Current − mA
Figure 5.
7
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
HIGH-LEVEL OUTPUT VOLTAGE AT RESET
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
HIGH-LEVEL OUTPUT CURRENT
6
VOH − High-Level Output Voltage at PFO − V
VOH − High-Level Output Voltage at RESET − V
5.1
Expanded View
5
TA = −40°C
4.9
TA = 25°C
TA = 0°C
4.8
4.7
TA = 85°C
4.6
VDD = 5 V
VBAT = GND
4.5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
5
TA = 25°C
4
TA = 0°C
3
Figure 7.
HIGH-LEVEL OUTPUT VOLTAGE AT PFO
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
VOL − Low-Level Output Voltage at RESET − V
VOH − High-Level Output Voltage at PFO − V
−2
−1.5
−1
−0.5
IOH − High-Level Output Current − mA
Figure 6.
Expanded View
5.50
TA = −40°C
5.45
TA = 25°C
TA = 0°C
5.35
5.30
TA = 85°C
5.20
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
5.15
5.10
−200 −180 −160 −140 −120 −100 −80 −60 −40 −20
IOH − High-Level Output Current − µA
Figure 8.
8
VDD = 5.5 V
PFI = 1.4 V
VBAT = GND
1
0
−2.5
0
5.55
5.25
TA = 85°C
2
IOH − High-Level Output Current − mA
5.40
TA = −40°C
0
3.5
VDD = 3.3 V
VBAT = GND
3
2.5
TA = 0°C
2
TA = 25°C
1.5
TA = 85°C
1
TA = −40°C
0.5
0
0
0
5
10
15
20
IOL − Low-Level Output Current − mA
Figure 9.
25
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
LOW-LEVEL OUTPUT VOLTAGE AT RESET
vs
LOW-LEVEL OUTPUT CURRENT
MINIMUM PULSE DURATION AT VDD
vs
THRESHOLD VOLTAGE OVERDRIVE AT VDD
10
Expanded View
9
400
Minimum Pulse Duration at VDD − µ s
TA = 85°C
VDD = 3.3 V
VBAT = GND
TA = 25°C
300
TA = 0°C
200
TA = −40°C
100
8
7
6
5
4
3
2
1
0
0
1
2
3
4
IOL − Low-Level Output Current − mA
0
0
5
0.1
0.2
0.3
0.4 0.5
0.6
0.7 0.8 0.9
1
Threshold Voltage Overdrive at VDD − V
Figure 10.
Figure 11.
MINIMUM PULSE DURATION AT PFI
vs
THRESHOLD VOLTAGE OVERDRIVE AT PFI
5
4.6
Minimum Pulse Duration at PFI − µ s
VOL − Low-Level Output Voltage at RESET − mV
500
VDD = 1.65 V
4.2
3.8
3.4
3
2.6
2.2
1.8
1.4
1
0.6
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Threshold Voltage Overdrive at PFI − V
1
Figure 12.
9
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
DETAILED DESCRIPTION
BATTERY FRESHNESS SEAL (TPS3617 Only)
The battery freshness seal of the TPS3617 family disconnects the backup battery from the internal circuitry until
it is needed. This ensures that the backup battery connected to VBAT should be fresh when the final product is
put to use. The following steps explain how to enable the freshness seal mode:
1. Connect VBAT (VBAT> VBAT(min)).
2. Ground PFO.
3. Connect PFI to VDD (PFI = VDD).
4. Connect VDD to power supply (VDD > VIT) and keep connected for 5 ms < t < 35 ms.
The battery freshness seal mode is disabled by the positive-going edge of RESET when VDD is applied.
POWER-FAIL COMPARATOR (PFI AND PFO)
An additional comparator monitors voltages other than the nominal supply voltage. The power-fail-input (PFI) can
be compared with an internal voltage reference of 1.15 V. If the input voltage falls below the power-fail threshold
(V(PFI)) of 1.15 V typical, the power-fail output (PFO) goes low. If it goes above V(PFI) plus about 12-mV
hysteresis, the output returns to high. By connecting two external resistors it is possible to supervise any voltages
above V(PFI). The sum of both resistors should be about 1 MΩ, to minimize power consumption and also to
ensure that the current in the PFI pin can be neglected compared with the current through the resistor network.
The tolerance of the external resistors should be not more than 1% to ensure minimal variation of the sensed
voltage. If the power-fail comparator is unused, connect PFI to ground and leave the PFO unconnected.
WATCHDOG
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also
important to ensure correct program execution. The task of a watchdog is to ensure that the program is not
stalled in an indefinite loop. The microprocessor, microcontroller, or DSP has to toggle the watchdog input within
0.8 s typically, to avoid a timeout from occurring. Either a low-to-high or a high-to-low transition resets the
internal watchdog timer. If the input is unconnected, the watchdog is disabled and should be retriggered
internally. See Figure 13 for the watchdog timing diagram.
VOUT
VIT
WDI
t(tout)
RESET
td
td
Undefined
Figure 13. Watchdog Timing
10
td
TPS3617
TPS3618
www.ti.com
SLVS339C – DECEMBER 2000 – REVISED NOVEMBER 2004
DETAILED DESCRIPTION (continued)
SAVING CURRENT WHILE USING THE WATCHDOG
The watchdog input is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily
pulses high, resetting the watchdog counter. For minimum watchdog input current (minimum overall power
consumption), leave WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within
7/8 of the watchdog time-out period to reset the watchdog timer. If instead, WDI is externally driven high for the
majority of the time-out period, a current of e.g. 5.0 V/40 kΩ ≈ 125 µA can flow into WDI.
BACKUP-BATTERY SWITCHOVER
In case of a brownout or power failure, it may be necessary to preserve the contents of RAM. If a backup battery
is installed at VBAT, the device automatically switches the connected RAM to backup power when VDD fails. In
order to allow the backup battery (e.g., a 3.6-V lithium cell) to have a higher voltage than VDD, these supervisors
should not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω
switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either
until VDD crosses VBAT, or until VDD rises above the reset threshold VIT. VOUT connects to VDD through a 1-Ω
(max) PMOS switch when VDD crosses the reset threshold.
FUNCTION TABLE
VDD> VIT
VOUT
1
1
VDD
1
0
VDD
0
1
VDD
0
0
VBAT
VDD – Normal Supply Voltage
VDD> VBAT
VDD – Mode
VIT Hysteresis
VBAT – Mode
VBSW Hysteresis
Undefined
VBAT – Backup-Battery Supply Voltage
Figure 14. VDD - VBAT Switchover
11
PACKAGE OPTION ADDENDUM
www.ti.com
8-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPS3617-50DGK
ACTIVE
MSOP
DGK
8
80
None
CU NIPDAU
Level-1-220C-UNLIM
TPS3617-50DGKR
ACTIVE
MSOP
DGK
8
2500
None
CU NIPDAU
Level-1-220C-UNLIM
TPS3618-50DGKR
ACTIVE
MSOP
DGK
8
2500
None
CU NIPDAU
Level-1-220C-UNLIM
TPS3618-50DGKT
ACTIVE
MSOP
DGK
8
250
None
CU NIPDAU
Level-1-220C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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