SGLS241A − MARCH 2004 − REVISED JUNE 2006
D Qualification in Accordance With
D
D
D
D
D
D
D
D
D
D
D
D
D
AEC-Q100†
Qualified for Automotive Applications
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
Dual Supervisory Circuits With Power Fail
for DSP and Processor-Based Systems
Voltage Monitor for Power Fail or
Low-Battery Warning
Watchdog Timer With 0.8-s Time-Out
Power-On Reset Generator With Integrated
100-ms Delay Time
Open-Drain Reset and Power-Fail Output
Supply Current of 15 µA (Typ)
Supply Voltage Range . . . 2.7 V to 6 V
Defined RESET Output From VDD ≥ 1.1 V
SO-8 Package
Temperature Range . . . −40°C to 125°C
Applications Include:
− Multivoltage DSPs and Processors
− Portable Battery-Powered Equipment
− Embedded Control Systems
− Intelligent Instruments
− Automotive Systems
D PACKAGE
(TOP VIEW)
SENSE1
SENSE2
PFI
GND
† Contact Texas Instruments for details. Q100 qualification data
available on request.
1
8
2
7
3
6
4
5
VDD
WDI
PFO
RESET
description
The TPS3306 family is a series of supervisory circuits designed for circuit initialization, which require two supply
voltages, primarily in DSP and processor-based systems.
The product spectrum of the TPS3306-xx is designed for monitoring two independent supply voltages of
3.3 V/1.5 V, 3.3 V/1.8 V, 3.3 V/2 V, 3.3 V/2.5 V, or 3.3 V/5 V.
TYPICAL OPERATING CIRCUIT
3.3 V
1.5 V
AVDD
TPS3306−15
R1
1%
R4
CVDD
SENSE1
VDD
DVDD
SENSE2
WDI
B_XF
PFO
A_XF
PFI
R2
1%
R3
GND
TMS320
VC5441
RESET
RESET
VSS
VSSA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2006 Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SGLS241A − MARCH 2004 − REVISED JUNE 2006
description (continued)
The various supervisory circuits are designed to monitor the nominal supply voltage, as shown in the following
supply-voltage monitoring table.
SUPPLY-VOLTAGE MONITORING
NOMINAL SUPERVISED VOLTAGE
DEVICE
THRESHOLD VOLTAGE (TYP)
SENSE1
SENSE2
SENSE1
SENSE2
TPS3306-15
3.3 V
1.5 V
2.93 V
1.4 V
TPS3306-18
3.3 V
1.8 V
2.93 V
1.68 V
TPS3306-20
3.3 V
2V
2.93 V
1.85 V
TPS3306-25
3.3 V
2.5 V
2.93 V
2.25 V
TPS3306-33
5V
3.3 V
4.55 V
2.93 V
During power on, RESET is asserted when the supply voltage, VDD, becomes higher than 1.1 V. Thereafter, the
supervisory circuits monitor the SENSEn inputs and keep RESET active as long as SENSEn remains below
the threshold voltage, VIT.
An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset.
The delay time, td(typ) = 100 ms, starts after SENSE1 and SENSE2 inputs have risen above VIT. When the
voltage at SENSE1 or SENSE2 input drops below the VIT, the output becomes active (low) again.
The integrated power-fail (PFI) comparator with separate open-drain (PFO) output can be used for low-battery
detection, power-fail warning, or for monitoring a power supply other than the main supply.
The TPS3306-xx devices integrate a watchdog timer that is periodically triggered by a positive or negative
transition of the watch-dog timer (WDI). When the supervising system fails to retrigger the watchdog circuit
within the time-out interval, tt(out) = 0.50 s, RESET becomes active for the time period td . This event also
reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog.
The TPS3306-xx devices are available in standard 8-pin SO packages.
The TPS3306-xxQ family is characterized for operation over a temperature range of −40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40_C
125_C
−40
C to 125
C
2
SMALL OUTLINE (D)
TOP-SIDE
MARKING
Tape and reel
TPS3306-15QDRQ1
615Q1
Tape and reel
TPS3306-18QDRQ1
618Q1
Tape and reel
TPS3306-20QDRQ1
620Q1
Tape and reel
TPS3306-25QDRQ1
625Q1
Tape and reel
TPS3306-33QDRQ1
633Q1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS241A − MARCH 2004 − REVISED JUNE 2006
FUNCTION/TRUTH TABLES
SENSE1 > VIT1
SENSE2 > VIT2
RESET
0
0
L
0
1
L
1
0
L
1
1
H
PFI > VIT
PFO
TYPICAL DELAY
0→1
L→H
0.5 µs
1→0
H→L
0.5 µs
functional block diagram
TPS3306
SENSE 1
R1
VDD
+
_
SENSE 2
R3
R2
R4
RESET
RESET
Logic + Timer
+
_
GND
Reference
Voltage
of 1.25 V
Oscillator
PFO
_
+
PFI
WDI
Transition
Detection
Watchdog
Logic + Timer
40 kΩ
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SGLS241A − MARCH 2004 − REVISED JUNE 2006
timing diagram
SENSEn
V(nom)
VIT
1.1 V
t
WDI
1
tt(out)
0
t
RESET
1
Undefined
Behavior
Undefined
Behavior
0
t
td
td
td
Reset Due to
Power Down
Reset Due to WDI
Reset Due to Power Drop Below VIT−
Reset Due to Power Up
Terminal Functions
TERMINAL
NAME
NO.
GND
4
PFI
PFO
I/O
DESCRIPTION
I
Ground
3
I
Power-fail comparator input
6
O
Power-fail comparator output, open drain
RESET
5
O
Active-low reset output, open drain
SENSE1
1
I
Sense voltage 1
SENSE2
2
I
Sense voltage 2
WDI
7
I
Watchdog timer input
VDD
8
I
Supply voltage
detailed description
watchdog
In a microprocessor- or DSP-based system, it is not only important to supervise the supply voltage, it is also important
to ensure correct program execution. The task of a watchdog is to ensure that the program is not stalled in an indefinite
loop. The microprocessor, microcontroller, or DSP has to typically toggle the watchdog input (WDI) within 0.8 s to
avoid a time-out occurring. Either a low-to-high or a high-to-low transition resets the internal watchdog timer. If the
input is unconnected or tied with a high-impedance driver, the watchdog is disabled and is retriggered internally.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS241A − MARCH 2004 − REVISED JUNE 2006
saving current while using the watchdog
WDI is internally driven low during the first 7/8 of the watchdog time-out period, then momentarily pulses high,
resetting the watchdog counter. For minimum watchdog input current (minimum overall power consumption), leave
WDI low for the majority of the watchdog time-out period, pulsing it low-high-low once within 7/8 of the watchdog
time-out period to reset the watchdog timer. If, instead, WDI is externally driven high for the majority of the time-out
period, a current of 5 V/40 kΩ ≈ 125 µA can flow into WDI.
VDD
VIT
t
WDI
t(tout)
t
RESET
td
td
t
Figure 1. Watchdog Timing
power-fail comparator (PFI and PFO)
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail-input
(PFI) is compared with an internal voltage reference of 1.25 V. If the input voltage falls below the power-fail threshold
(VPFI) of 1.25 V (typ), the power-fail output (PFO) goes low. If PFO goes above 1.25 V plus about 10−mV hysteresis,
the output returns to high. By connecting two external resistors, it is possible to supervise any voltages above 1.25 V.
The sum of both resistors should be approximately 1 MΩ, to minimize power consumption and also to ensure that the
current in the PFI pin can be neglected compared with the current through the resistor network. The tolerance of the
external resistors should be not more than 1% to ensure minimal variation of sensed voltage. If the power-fail
comparator is unused, connect PFI to ground and leave PFO unconnected.
VPFI,trip = 1.25 V ×
R1 + R2
R2
V(SENSE)
R1
1%
VCC
PFI
R2
1%
POST OFFICE BOX 655303
PFO
TPS3306
GND
• DALLAS, TEXAS 75265
5
SGLS241A − MARCH 2004 − REVISED JUNE 2006
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note1): VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Maximum low output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, IOH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5 mA
Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND. For reliable operation, the device must not be operated at 7 V for more than t = 1000 h
continuously.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
377 mW
recommended operating conditions at specified temperature range
MIN
MAX
2.7
6
V
Input voltage at WDI and PFI, VI
0
0
VDD + 0.3
(VDD + 0.3)VIT/1.25 V
V
Input voltage at SENSE1 and SENSE2, VI
Supply voltage, VDD
0.7 × VDD
High-level input voltage at WDI, VIH
Low-level input voltage at WDI, VIL
Operating free-air temperature range, TA
6
−40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
V
V
0.3 × VDD
V
125
°C
SGLS241A − MARCH 2004 − REVISED JUNE 2006
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOL
TEST CONDITIONS
RESET,
PFO
Low-level output voltage
Power-up reset voltage (see Note 2)
VIT
Negative-going input threshold voltage
(see Note 3)
VSENSE1,
VSENSE2
MIN
Vhys
Hysteresis
VSENSEn
MAX
VDD = 2.7 V to 6 V, IOL = 20 µA
0.2
VDD = 3.3 V,
IOL = 2 mA
0.4
VDD = 6 V,
IOL = 3 mA
0.4
VDD ≥ 1.1 V,
IOL = 20 µA
0.4
VDD = 2.7 V to 6 V,
TA = −40°C to 125°C
1.35
1.4
1.44
1.62
1.68
1.74
1.79
1.85
1.91
2.18
2.25
2.34
2.84
2.93
3.04
4.44
4.55
4.68
1.2
1.25
1.3
PFI
PFI
TYP
VIT = 1.25 V
VIT = 1.4 V
10
VIT = 1.68 V
VIT = 1.86 V
15
VIT = 2.25 V
VIT = 2.93 V
20
VIT = 4.55 V
WDI = VDD = 6 V,
Time average (dc = 88%)
40
UNIT
V
V
V
15
20
mV
30
100
150
µA
WDI = 0 V,
VDD = 6 V,
Time average (dc = 12%)
−15
−20
µA
WDI
WDI = VDD = 6 V
120
170
SENSE1
5
10
SENSE2
VSENSE1 = VDD = 6 V
VSENSE2 = VDD = 6 V
6
10
WDI = 0 V,
−120
−170
µA
30
nA
40
µA
IH(AV)
Average high-level input current
WDI
IL(AV)
Average low-level input current
WDI
IH
High-level input current
IL
II
Low-level input current
WDI
Input current
PFI
IDD
Ci
Supply current
VDD = 6 V
VDD = 6 V, 0 V ≤ VI ≤ VDD
−30
15
µA
Input capacitance
VI = 0 V to VDD
10
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic 0.1 µF) should be placed close to the supply terminals.
timing requirements at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER
tw
Pulse width
SENSEn
WDI
TEST CONDITIONS
VSENSEnL = VIT − 0.2 V,
VIH = 0.7 × VDD,
POST OFFICE BOX 655303
VSENSEnH = VIT + 0.2 V
VIL = 0.3 × VDD
• DALLAS, TEXAS 75265
MIN
MAX
UNIT
6
µs
100
ns
7
SGLS241A − MARCH 2004 − REVISED JUNE 2006
switching characteristics at VDD = 2.7 V to 6 V, RL = 1 MΩ, CL = 50 pF, TA = 25°C
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tt(out)
Watchdog time-out
VI(SENSEn) ≥ VIT + 0.2 V,
See timing diagram
0.5
0.8
1.2
s
td
Delay time
VI(SENSEn) ≥ VIT + 0.2 V,
See timing diagram
70
100
140
ms
tPHL
Propagation (delay) time,
high- to low-level output
1
5
µs
tPHL
Propagation (delay) time,
high- to low-level output
Propagation (delay) time,
low- to high-level output
0.5
1
µss
tPLH
SENSEn
RESET
PFI
PFO
VIH = VIT + 0.2 V,
VIL = VIT − 0.2 V
NORMALIZED SENSE THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
1.005
18
VDD = 6 V
1.004
16
14
1.003
12
I DD − Supply Current − µ A
Normalized Input Threshold Voltage — VIT(TA), VIT (255C)
TYPICAL CHARACTERISTICS
1.002
1.001
1
0.999
0.998
0.997
10
8
6
4
2
0
−2
−4
−15
10
35
60
85
−8
−10
−0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
TA − Free-Air Temperature − °C
VDD − Supply Voltage − V
Figure 2
8
SENSEn = VDD
TA = 25°C
−6
0.996
0.995
−40
TPS3306-33
Figure 3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SGLS241A − MARCH 2004 − REVISED JUNE 2006
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
2.8
6.5
VOL − Low-Level Output Voltage − V
2
1.6
1.2
VDD = 6 V
6
2.4
85°C
0.8
−40°C
0.4
5.5
5
4.5
4
3.5
3
85°C
2.5
2
1.5
−40°C
1
0.5
0
0
1
0
2 3 4 5 6 7 8 9 10 11 12 13
IOL − Low-Level Output Current − mA
0
10 15 20 25 30 35 40 45 50 55 60
5
IOL − Low-Level Output Current − mA
Figure 4
Figure 5
MINIMUM PULSE DURATION AT SENSE
vs
THRESHOLD OVERDRIVE
10
tw − Minimum Pulse Duration at Vsense − µ s
VOL − Low-Level Output Voltage − V
VDD = 2.7 V
VDD = 6 V
9
8
7
6
5
4
3
2
1
0
0
100 200 300 400 500 600 700 800 900 1000
SENSE − Threshold Overdrive − mV
Figure 6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3306-15QDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR
TPS3306-18QDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR
TPS3306-20QDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR
TPS3306-25QDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR
TPS3306-33QDRQ1
ACTIVE
SOIC
D
8
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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