DG528/529 Vishay Siliconix Latchable Single 8-Ch/Differential 4-Ch Analog Multiplexers Low rDS(on): 270 44-V Power Supply Rating On-Board Address Latches Break-Before-Make Low Leakage—ID(on): 30 pA Improved System Accuracy Microporcessor Bus Compatible Easily Interfaced Reduced Crosstalk Data Acquisition Systems Automatic Test Equipment Avionics and Military Systems Medical Instrumentation applications. Break-before-make switching action protects against momentary shorting of the input signals. The DG528/529 are built on the improved PLUS-40 CMOS process. A buried layer prevents latchup. The DG528 is an 8-channel single-ended analog multiplexer designed to connect one of eight inputs to a common output as determined by a 3-bit binary address (A0, A1, A2). DG529, a 4-channel dual analog multiplexer, is designed to connect one of four differential inputs to a common differential output as determined by its 2-bit binary address (A0, A1) logic. The on chip TTL-compatible address latches simplify digital interface design and reduce board space in data acquisition systems, process controls, avionics, and ATE. These analog multiplexers have on-chip address and control latches to simplify design in microprocessor based S3 S4 D 3 Latches 16 4 Decoders/Drivers 15 14 5 6 13 7 12 8 11 9 10 A2 GND V+ S5 RS 3 2 1 20 19 A1 NC A1 WR 17 EN 4 Latches V– 5 Decoders/Drivers S8 A0 17 GND S1 6 16 V+ S2 7 15 S5 S3 8 14 S6 S6 S7 WR 18 A2 EN V– S1a S2a S3a 9 10 11 12 13 S7 S2 2 RS DG529 Dual-In-Line S8 S1 18 NC V– 1 D EN PLCC A0 A0 DG528 S4 WR DG528 Dual-In-Line S4a Da 1 18 2 17 3 Latches 16 4 Decoders/Drivers 15 5 14 6 13 7 12 8 11 9 10 RS A1 GND V+ S1b S2b S3b S4b Db Top View Top View Document Number: 70068 P-32167—Rev. C, 15-Nov-93 Top View www.vishay.com FaxBack 408-970-5600 5-1 DG528/529 Vishay Siliconix TRUTH TABLES AND ORDERING INFORMATION A2 A1 TRUTH TABLE Ċ DG528 TRUTH TABLE Ċ DG529 8-Channel Single-Ended Multiplexer Differential 4-Channel Multiplexer A0 EN WR RS On Switch Latching X X EN WR RS On Switch 1 Maintains previous switch condition 0 None (latches cleared) Latching X X 1 Maintains previous switch condition Reset X A0 X X Reset X X X X 0 None (latches cleared) Transparent Operation X X X Transparent Operation X X X 0 0 1 None X 0 0 1 None 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 1 2 1 1 0 1 2 0 1 0 1 0 1 3 0 1 0 1 3 0 1 1 1 0 1 4 1 1 0 1 4 1 0 0 1 0 1 5 1 0 1 1 0 1 6 1 1 0 1 0 1 7 1 1 1 1 0 1 8 ORDERING INFORMATION Ċ DG528 Temp Range 0 to 70_C Package Part Number Logic “0” = VAL 0.8 V Logic “1” = VAH 2.4 V X = Don’t Care ORDERING INFORMATION Ċ DG529 Temp Range Package 18-Pin Plastic DIP DG528CJ 0 to 70_C 18-Pin Plastic DIP Part Number 20-Pin PLCC DG528DN –25 to 85_C DG529CJ DG529BK 18-Pin CerDIP –25 to 85_C DG528BK 18 Pi C 18-Pin CerDIP DIP –55 125_C 55 to 125 C –55 to 125_C DG529AK/883 DG528AK DG528AK/883 5962-8768901VA ABSOLUTE MAXIMUM RATINGS Voltage Referenced to V– V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V Digital Inputsa, VS, VD . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) +2 V or 30 mA, whichever occurs first Current (Any Terminal Except S or D) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Storage Temperature (AK, BK Suffix) . . . . . . . . . . . . . . –65 to 150_C (CJ, DN Suffix) . . . . . . . . . . . . . . –65 to 125_C www.vishay.com S FaxBack 408-970-5600 5-2 Power Dissipation (Package)b 18-Pin Plastic DIPc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW 18-Pin CerDIPd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW 20-Pin PLCCe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW Notes: a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads soldered or welded to PC board. c. Derate 6.3 mW/_C above 75_C. d. Derate 1.2 mW/_C above 75_C. e. Derate 10 mW/_C above 75_C. Document Number: 70068 P-32167—Rev. C, 15-Nov-93 DG528/529 Vishay Siliconix Test Conditions Unless Otherwise Specified A Suffix –55 to 125_C B, C, D Suffix –40 to 85_C V+ = 15 V, V– = –15 V, WR = 0 RS = 2.4 V, VIN = 2.4 V, 0.8 mFf Tempb VANALOG Full rDS(on) VD = 10 V, IS = –200 mA Room Full 270 DrDS(on) –10 V < VS < 10 V Room 6 Source Off Leakage Current IS(off) VEN = 0 V, VS = "10 V VD = #10 V Room Full "0.005 –1 –50 1 50 –5 –50 5 50 Drain Off L k Leakage Current C t VEN = 0 V VD = "10 V VS = #10 V DG528 Room Full "0.015 ID(off) –10 –200 10 200 –20 –200 20 200 DG529 Room Full "0.008 –10 –100 10 100 –20 –100 20 100 DG528 Room Full "0.03 –10 –200 10 200 –20 –200 20 200 DG529 Room Full "0.015 –10 –100 10 100 –20 –100 20 100 VA = 2.4 V Room Hot –0.002 –10 –30 VA = 15 V Room Hot 0.006 IAL VEN = 0 V, 2.4 V, VA = 0 V RS = 0 V, WR = 0 V Room Hot –0.002 Transition Time tTRANS See Figure 5 Room 0.6 Break-Before-Make Interval tOPEN See Figure 4 Room 0.2 EN and WR Turn-On Time tON(EN, WR) See Figures 6 and 7 Room 1 1.5 EN and WR Turn-Off Time tOFF(EN, WR) See Figures 6 and 8 Room 0.4 1 Q VS = 0 V, Ry = 0 W CL = 10 mF Room 4 pC CL = 15 pF VS = 7 VRMS, f = 500 kHz Room 68 dB Cin f = 1 MHz Room 2.5 CS(off) VEN = 0 V, VS = 0 V f = 140 kHz Room 5 DG528 Room 25 DG529 Room 12 Parameter Symbol Typc Mind Maxd Mind Maxd Unit Analog Switch Analog Signal Rangee Drain-Source On-Resistance Greatest Change in rDS(on) Between Channelsf Drain On L k Leakage Current C t ID(on) VS = VD = 10 V VEN = 2 2.4 4V –15 15 –15 400 500 15 V 450 550 W % nA A Digital Control Logic Input Current IAH Input Voltage High Logic Input Current Input Voltage Low –10 –30 10 30 –10 –30 10 30 mA A –10 –30 Dynamic Characteristics Charge Injection Ą 1 ms VEN = 0 V, RL = 1 kW Off Isolation Logic Input Capacitance Source Off Capacitance Drain Off Capacitance OIRR CD(off) VEN = 0 V VD = 0 V f = 140 kHz pF F Minimum Input Timing Requirements Write Pulse Width tW Full 300 300 AX , EN Setup Time tS Full 180 180 AX , EN Hold Time tH Full 30 30 Reset Pulse Width tRS Full 500 500 Document Number: 70068 P-32167—Rev. C, 15-Nov-93 VS = 5 V, See Figure 3 ns www.vishay.com S FaxBack 408-970-5600 5-3 DG528/529 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter V+ = 15 V, V– = –15 V, WR = 0 RS = 2.4 V, VIN = 2.4 V, 0.8 mFf Symbol B, C, D Suffix A Suffix –55 to 125_C Tempb Typc Mind Maxd –40 to 85_C Mind Maxd Unit Power Supplies Positive Supply Current I+ Negative Supply Current I– Room VEN = 0 V, VA = 0 2.5 Room –1.5 2.5 –1.5 mA Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) rDS(on) vs. VD and Power Supply Leakage Currents vs. Analog Voltage TA = 25_C ID(on) 0 400 IS(off) 7.5 V 300 I S, I D (pA) r DS(on)– Drain-Source On-Resistance ( W ) 500 10 V ID(off) –40 15 V 200 –20 15 V Supplies TA = 25_C 20 V 100 –60 –20 –15 –10 –5 0 5 10 15 20 –15 –10 –5 0 5 10 VD – Drain Voltage (V) VANALOG – Analog Voltage (V) Input Switching Threshold vs. V+ and V– Supply Voltages Supply Currents vs. Toggle Frequency 15 2.5 TA = 25_C 4 2.0 I+, I– (mA) V T (V) 3 1.5 1.0 1 0.5 I– 0 0 0 5 10 15 V+, V– Positive and Negative Supplies (V) www.vishay.com S FaxBack 408-970-5600 5-4 I+ 2 20 1k 10 k 100 k 1M Toggle Frequency (Hz) Document Number: 70068 P-32167—Rev. C, 15-Nov-93 DG528/529 Vishay Siliconix V+ GND S1 VREF V+ DO QO EN V+ Sn V– V+ V– V– Dn Qn AX V+ V– V+ V– WR Level Shift Latches Decode V+ V– V+ D V+ V– CLK RESET RS V– FIGURE 1. The internal structure of the DG528/DG529 includes a 5-V logic interface with input protection circuitry followed by a latch, level shifter, decoder and finally the switch constructed with parallel n- and p-channel MOSFETs (see Figure 1). Following the latches the QX signals are level shifted and decoded to provide proper drive levels for the CMOS switches. This level shifting insures full on/off switch operation for any analog signal present between the V+ and V– supply rails. The logic interface circuit compares the TTL input signal against a TTL threshold reference voltage. The output of the comparator feeds the data input of a D type latch. The level sensitive D latch continuously places the DX input signal on the QX output when the WR input is low, resulting in transparent latch operation. As soon as WR returns high, the latches hold the data last present on the DX input, subject to the minimum input timing requirements. The EN pin is used to enable the address latches during the WR pulse. It can be hard-wired to the logic supply or to V+ if one of the channels will always be used (except during a reset) or it can be tied to address decoding circuitry for memory mapped operation. The RS pin is used as a master reset. All latches are cleared regardless of the state of any other latch or control line. The WR pin is used to transfer the state of the address control lines to their latches, except during a reset or when EN is low (see Truth Tables). 3V WR 3V RS 50% 0 50% 0 tRS tW tS 3V A0, A1, (A2) EN 80% 80% 0 Switch Output VO 80% 0 FIGURE 2. Document Number: 70068 P-32167—Rev. C, 15-Nov-93 tOFF (RS) tH FIGURE 3. www.vishay.com FaxBack 408-970-5600 5-5 DG528/529 Vishay Siliconix +15 V +2.4 V V+ RS EN Logic Input All S and Da +5 V tr <20 ns tf <20 ns 3V 50% 0V DG528 DG529 A0, A1, (A2) Db, D WR GND 50 VO VS V– –15 V 300 35 pF 80% Switch Output VO tOPEN 0V FIGURE 4. Break-Before-Make +15 V RS +2.4 V V+ S1 "10 V EN S2 – S7 A0 A1 A2 GND DG528 WR S8 #10 V VO D V– 50 Logic Input tr <20 ns tf <20 ns 3V 50% 0V 300 35 pF –15 V VS1 90% Switch Output +15 V RS +2.4 V EN A0 A1 GND VO V+ S1b 10% #10 V VS8 S1a – S4a, Da S2b and S3b S4b DG529 WR V– Db 50 300 0V tTRANS S1 ON "10 V tTRANS S8 ON VO 35 pF –15 V FIGURE 5. Transition Time www.vishay.com FaxBack 408-970-5600 5-6 Document Number: 70068 P-32167—Rev. C, 15-Nov-93 DG528/529 Vishay Siliconix +15 V V+ +2.4 V RS EN S1 –5V DG528 S2 – S8 A0 A1 A2 GND WR 50 VO D V– 300 35 pF Logic Input tr <20 ns tf <20 ns 3V 50% 0V –15 V tON(EN) tOFF(EN) 0V +15 V Switch Output V+ +2.4 V RS S1b EN –5V VO DG529 A0 A1 GND WR Db VO V– 50 90% VO S1a – S4a, Da S2b – S4b 300 35 pF –15 V FIGURE 6. Enable tON/tOFF Time +15 V +2.4 V EN A0, A1, (A2) V+ S1 or S1b +5 V 3 V WR Remaining Switches RS VO DG528 DG529 WR GND 50% 0 V Db, D VO V– 300 W tON(WR) Switch Output 35 pF 20% 0V –15 V FIGURE 7. Write Turn-On Time tON(WR) Document Number: 70068 P-32167—Rev. C, 15-Nov-93 www.vishay.com FaxBack 408-970-5600 5-7 DG528/529 Vishay Siliconix +15 V +2.4 V EN A0, A1, (A2) V+ S1 or S1b 3 V +5 V RS Remaining Switches RS GND DG528 DG529 tOFF(RS) VO Db, D WR 50% 0 V 80% VO Switch Output V– 35 pF 300 W 0V –15 V FIGURE 8. Reset Turn-Off Time tOFF(RS) +15 V 15 V Analog Inputs V+ S1 A0, A1, A2 , EN Data Bus Processor System Bus DG528 RS RESET +5 V WRITE WR S8 Address Bus Address Decoder D Analog Output V– – 15 V FIGURE 9. Bus Interface www.vishay.com FaxBack 408-970-5600 5-8 Document Number: 70068 P-32167—Rev. C, 15-Nov-93 DG528/529 Vishay Siliconix V+ Positive Supply Voltage (V) V– Negative Supply Voltage (V) VIN Logic Input Voltage VINH(min)/VINL(max) (V) VS or VD Analog Voltage Range (V) 20 –20 2.4/0.8 20 15b –15 2.4/0.8 15 8c –8 (min) 2.4/0.8 8 Notes: a. Application Hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. b. Electrical Parameter Chart based on V+ = 15 V, VL = 5 V, VR = GND. c. Operation below 8 V is not recommended. The DG528/DG529 minimize the amount of interface hardware between a microprocessor system bus and the analog system being controlled or measured. The internal TTL compatible latches give these multiplexers write-only memory, that is, they can be programmed to stay in a particular switch state (e.g., switch 1 on) until the microprocessor determines it is necessary to turn different switches on or turn all switches off (see Figure 9). The input latches become transparent when WR is held low; therefore, these multiplexers operate by direct command of the coded switch state on A2, A1, A0. In this mode the DG528 is identical to the popular DG508A. The same is true of the DG529 versus the popular DG509A. Document Number: 70068 P-32167—Rev. C, 15-Nov-93 During system power-up, RS would be low, maintaining all eight switches in the off state. After RS returned high the DG528 maintains all switches in the off state. When the system program performs a write operation to the address assigned to the DG528, the address decoder provides a CS active low signal which is gated with the WRITE (WR) control signal. At this time the data on the DATA BUS (that will determine which switch to close) is stabilizing. When the WR signal returns to the high state, (positive edge) the input latches of the DG528 save the data from the DATA BUS. The coded information in the A0, A1, A2 and EN latches is decoded and the appropriate switch is turned on. The EN latch allows all switches to be turned off under program control. This becomes useful when two or more DG528s are cascaded to build 16-line and larger multiplexers. www.vishay.com FaxBack 408-970-5600 5-9 Legal Disclaimer Notice Vishay Notice Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale. Document Number: 91000 Revision: 08-Apr-05 www.vishay.com 1