DG535/536 Vishay Siliconix 16-Channel Wideband Video Multiplexers FEATURES BENEFITS D D D D D D D D High Video Quality D Reduced Insertion Loss D Reduced Input Buffer Requirements D Minimizes Power Consumption D Simplifies Bus Interface Crosstalk: –100 dB @ 5 MHz 300 MHz Bandwidth Low Input and Output Capacitance Low Power: 75 W Low rDS(on): 50 On-Board Address Latches Disable Output APPLICATIONS D D D D D D Video Switching/Routing High Speed Data Routing RF Signal Multiplexing Precision Data Acquisition Crosspoint Arrays FLIR Systems DESCRIPTION The DG535/536 are 16-channel multiplexers designed for routing one of 16 wideband analog or digital input signals to a single output. They feature low input and output capacitance, low on-resistance, and n-channel DMOS “T” switches, resulting in wide bandwidth, low crosstalk and high “off” isolation. In the on state, the switches pass signals in either direction, allowing them to be used as multiplexers or as demultiplexers. On-chip address latches and decode logic simplify microprocessor interface. Chip Select and Enable inputs simplify addressing in large matrices. Single-supply operation and a low 75-W power consumption vastly reduces power supply requirements. Theses devices are built on a proprietary D/CMOS process which creates low-capacitance DMOS FETs and high-speed, low-power CMOS logic on the same substrate. For more information please refer to Vishay Siliconix Application Note AN501 (FaxBack document number 70608). FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG536 S6 4 25 S12 S5 5 24 S13 S4 6 23 S14 S3 7 22 S15 S2 8 21 S16 S1 9 20 D DIS 10 19 V+ CS 11 18 ST CS 12 17 A3 16 A2 15 A1 Top View Dual-In-Line Document Number: 70070 S-02315—Rev. D, 05-Oct-00 39 S6 8 38 GND CS 9 37 S7 EN 10 36 GND A0 11 35 S8 34 GND 33 S9 GND Latches/ Decoders/ Drivers A1 12 A2 13 A3 14 32 ST 15 31 S10 V+ 16 30 GND D 17 29 S11 GND 14 7 CS GND S12 A0 DIS S14 GND S13 13 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 Latches/Decoders/Drivers EN 6 5 4 3 2 GND S11 GND S5 26 GND S4 3 S3 S7 GND S10 S2 27 GND 2 S15 GND S8 S1 S9 GND 28 S16 GND 1 PLCC/Cerquad GND GND DG535 Top View www.vishay.com 5-1 DG535/536 Vishay Siliconix TRUTH TABLES AND ORDERING INFORMATION ORDERING INFORMATION Temperature Range –40 to 85_C _ Package DG535DJ 44-Pin PLCC DG536DN 28-Pin Sidebraze –55 to 125 125_C C Part Number 28-Pin Plastic DIP 44-Pin Cerquad DG535AP DG535AP/883 DG536AM/883 TRUTH TABLE EN CS CS 0 X X X 0 X X X 1 1 X 1 X 0 X STa A3 A2 A1 A0 Channel Selected Disableb 1 X X X X None High Z 0 0 0 0 S1 0 0 0 1 S2 0 0 1 0 S3 0 0 1 1 S4 0 1 0 0 S5 0 1 0 1 S6 0 1 1 0 S7 0 1 1 1 S8 1 0 0 0 S9 1 0 0 1 S10 1 0 1 0 S11 1 0 1 1 S12 1 1 0 0 S13 1 1 0 1 S14 1 1 1 0 S15 1 1 1 1 S16 X X X X Maintains previous switch condition 1 0 Low Z High Z or Low Z Logic “0” = VAL v 4.5 V Logic “1” = VAH w 10.5 V X = Don’t Care Notes: a. Strobe input (ST) is level triggered. b. Low Z, High Z = impedance of Disable Output to GND. Disable output sinks current when any channel is selected. ABSOLUTE MAXIMUM RATINGS V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . (GND – 0.3 V) to (V+ plus 2 V ) or 20 mA, whichever occurs first 28-Pin Sidebrazec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW 44-Pin PLCCd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW 44-Pin Cerquade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND – 0.3 V) to V+ plus 2 V) or 20 mA, whichever occurs first Current (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Current (S or D) Pulsed 1 ms 10% duty cycle . . . . . . . . . . . . . . . . . . . . 40 mA Storage Temperature (A Suffix) . . . . . . . . . . . . . . . . . . . . –65 to 150_C (D Suffix) . . . . . . . . . . . . . . . . . . . . –65 to 125_C Power Dissipation (Package)a 28-Pin Plastic DIPb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mW www.vishay.com 5-2 Notes: a. All leads soldered or welded to PC board. b. Derate 8.6 mW/_C above 75_C. c. Derate 16 mW/_C above 75_C. d. Derate 6 mW/_C above 75_C. e. Derate 11 mW/_C above 75_C. Document Number: 70070 S-02315—Rev. D, 05-Oct-00 DG535/536 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Symbol V+ = 15 V, ST, CS = 10.5 V CS = 4.5 V, VA = 4.5 or 10.5 Vf Tempb Typc A Suffix D Suffix –55 to 125_C –40 to 85_C Minc Maxc Minc Maxc Unit 0 10 0 10 V Analog Switch Analog Signal Rangee VANALOG Drain-Source On-Resistance Room Full 55 90 120 90 120 9 9 Resistance Match rDS(on) IS = –1 mA, VD = 3 V EN = 10.5 V Sequence Each Switch On Source Off Leakage Current IS(off) VS = 3 V, VD = 0 V, EN = 4.5 V Room Full –10 –100 10 100 –10 –100 10 100 Drain On Leakage Current ID(on) VS = VD = 3 V, EN = 10.5 V Room Full –10 –1000 10 1000 –10 –100 –10 –100 RDISABLE IDISABLE = 1 mA, EN = 10.5 V Room Full Disable Output rDS(on) Full Room 100 200 250 200 250 nA Digital Control Input Voltage High VAIH Full Input Voltage Low VAIL Full Address Input Current IAI Address Input Capacitance CA VA = GND or V+ 10.5 10.5 4.5 Room Full <0.01 Full 5 –1 –100 1 100 V 4.5 –1 –100 1 100 A pF Dynamic Characteristics On State Input Capacitancee Off State Input Capacitancee Off State Output Capacitancee Multiplexer Switching Time Break-Before-Make Interval CS(on) CS(off) CD(off) VD = VS = 3 V VS = 3 V VD = 3 V PLCC Room 32 Cerquad Room 35 45 DIP Room 40 55 55 PLCC Room 2 8 8 Cerquad Room 5 DIP Room 3 PLCC Room 8 Cerquad Room 12 DIP Room 9 tTRANS tOPEN 45 pF Full See Figure 4 Full 20 20 300 300 25 25 ns EN, CS, CS, ST, tON tON See Figure 2 and 3 Full 300 300 EN, CS, CS, ST, tOFF tOFF See Figure 2 Full 150 150 Q See Figure 5 Charge Injection Single-Channel Crosstalk Chip Disabled Crosstalk Document Number: 70070 S-02315—Rev. D, 05-Oct-00 XTALK(SC) XTALK(CD) RIN = 75 RL = 75 f = 5 MHz See Figure 9 RIN = RL = 75 f = 5 MHz EN = 4.5 V See Figure 8 Room –35 PLCC Room –100 Cerquad Room –93 DIP Room –60 PLCC Room –85 Cerquad Room –84 DIP Room –60 pC dB www.vishay.com 5-3 DG535/536 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter V+ = 15 V, ST, CS = 10.5 V CS = 4.5 V, VA = 4.5 or 10.5 Vf Symbol Tempb Typc PLCC Room –92 Cerquad Room –87 DIP Room –72 PLCC Room –74 Cerquad Room –74 DIP Room –60 A Suffix D Suffix –55 to 125_C –40 to 85_C Minc Maxc Minc Maxc Unit Dynamic Characteristics (Cont’d) Adjacent Input Crosstalk RIN = 10 RL = 10 k f = 5 MHz See Figure 10 XTALK(AI) All Hostile Crosstalke RIN = 10 RL = 10 k f = 5 MHz See Figure 7 XTALK(AH) BW RL = 50 , See Figure 6 Room 500 Positive Supply Current I+ Any One Channgel Selected with All Logic Inputs at GND or V+ Room Full 5 Supply Voltage Range V+ Bandwidth –60 dB –60 MHz Power Supplies 50 100 Full 10 16.5 10 Full 200 200 Full 100 100 Full 50 50 50 100 A 16.5 V Minimum Input Timing Requirements Strobe Pulse Width tSW A0, A1, A2, A3 CS, CS, EN Data Valid to Strobe tDW A0, A1, A2, A3 CS, CS, EN Data Valid after Strobe tWD See Figure 1 ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VA = input voltage to perform proper function. TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) rDS(on) vs. VD and Temperature V+ = +15 V GND = 0 V 360 320 280 125_C 240 200 160 120 25_C 80 –55_C 40 0 GND = 0 V TA = 25_C 270 240 210 8V 180 12 V 150 15 V 120 90 60 30 0 0 2 4 6 VD – Drain Voltage (V) www.vishay.com 5-4 rDS(on) vs. VD and Power Supply Voltage 300 r DS(on)– Drain-Source On-Resistance ( ) r DS(on)– Drain-Source On-Resistance ( ) 400 8 10 0 2 4 6 8 10 VD – Drain Voltage (V) Document Number: 70070 S-02315—Rev. D, 05-Oct-00 DG535/536 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Logic Input Switching Threshold vs. Supply Voltage (V+) Supply Current vs. Supply Voltage and Temperature 14 10 9 GND = 0 V TA = 25_C 8 GND = 0 V 12 7 10 6 8 I+ ( A) V th (V) 125_C 5 4 3 25_C 6 4 –55_C 2 2 1 0 0 8 10 12 14 16 18 10 11 12 V+ – Positive Supply (V) ID(on) vs. Temperature 14 15 16 17 18 Leakage Current vs. Temperature 1 A V+ = +15 V GND = 0 V VD = VS = 3 V 100 nA V+ = +15 V GND = 0 V 100 nA 10 nA I S, I D – Leakage I D(on) – Leakage 13 V+ – Positive Supply (V) 1 nA 100 pA 10 pA ID(off) 10 nA IS(off) 1 nA 100 pA 10 pA 1 pA 1 pA –55 –35 –15 5 25 45 65 85 105 125 –55 –35 –15 5 Temperature (_C) 25 45 65 85 105 125 Temperature (_C) Adjacent Input Crosstalk vs. Frequency –3 dB Bandwidth Insertion Loss vs. Frequency 0 –120 DG536 RIN = 10 –100 –4 Insertion Loss (dB) X TALK(AI) (dB) DG536 –80 DG536 RIN = 75 –60 DG535 RIN = 10 –40 –8 –3 dB Points –12 Test Circuit See Figure 6 RL = 50 –16 –20 DG535 Test Circuit See Figure 10 –20 0 0.1 1 10 f – Frequency (MHz) Document Number: 70070 S-02315—Rev. D, 05-Oct-00 100 1 10 100 1000 f – Frequency (MHz) www.vishay.com 5-5 DG535/536 Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Chip Disable Crosstalk vs. Frequency All Hostile Crosstalk vs. Frequency –160 –160 Test Circuit See Figure 8 –140 DG536 RIN = 10 RL = 10 k –120 –100 DG536 RL = 75 –80 X TALK(AH) (dB) –120 X TALK(CD) (dB) Test Circuit See Figure 7 –140 DG536 RL = 50 DG535 RL = 75 –60 –100 DG536 RIN = 75 RL = 75 –80 –60 –40 –40 –20 –20 DG535 RIN = 10 RL = 10 k 0 0 0.1 1 10 100 0.1 1 f – Frequency (MHz) tON, tOFF and Break-Before-Make vs. Temperature Test Circuit See Figures 2, 3, 4 Single Channel Crosstalk vs. Frequency tON –120 X TALK(SC) (dB) 120 Switching Time (ns) Test Circuit See Figure 9 RIN = 75 RL = 75 –140 100 tBBM 80 60 tOFF 40 100 –160 160 140 10 f – Frequency (MHz) –100 DG536 –80 –60 DG535 –40 –20 20 0 0 –55 –35 –15 5 25 45 65 85 105 125 0.1 1 10 100 f – Frequency (MHz) Temperature (_C) INPUT TIMING REQUIREMENTS 15 V ST 7.5 V 0V tSW tDW tWD 15 V 10.5 V 10.5 V 4.5 V 4.5 V CS, A0, A1, A2, A3 CS, EN 0V FIGURE 1. www.vishay.com 5-6 Document Number: 70070 S-02315—Rev. D, 05-Oct-00 DG535/536 Vishay Siliconix TEST CIRCUITS +15 V +15 V V+ ST A0 A1 A2 A3 Logic Input Address Logic Input tr <20 ns tf <20 ns CS 15 V 50% EN or CS 0V +3 V S16 S1 – S15 90% EN or CS CS GND VO D 1 k Signal Output 35 pF tON tOFF FIGURE 2. EN, CS, CS, Turn On/Off Time +15 V +15 V Address Logic Input tr <20 ns tf <20 ns V+ EN, CS A1, A2, A3 S2 – S15 Address Input 15 V 50% 0V +3 V S1 15 V 0V A0 ST Logic Input VO D GND CS 1 k tON(ST) VOUT 90% 35 pF 0V FIGURE 3. Strobe ST Turn On Time +15 V +15 V +3 V Address Logic Input tr <20 ns tf <20 ns V+ EN CS ST A0 A1 A2 A3 S1 S16 S2 thru S15 15 V 50% 0V Switch Output 90% S1 Turning Off D GND S16 Turning On VO tBBM CS 1 k 35 pF tTRANS FIGURE 4. Transition Time and Break-Before-Make Interval Document Number: 70070 S-02315—Rev. D, 05-Oct-00 www.vishay.com 5-7 DG535/536 Vishay Siliconix TEST CIRCUITS +15 V +15 V +15 V V+ A0, A1, A2, A3 ST EN S16 +3 V Logic Input D VO +15 V CL 1000 pF CS GND +15 V CS EN CS ST V+ S2 thru S15 S1 CS Signal Generator (75 ) VOUT VOUT GND D CS VO A0 to A3 RL 50 W VOUT is the measured voltage error due to charge injection. The charge injection in Coulombs is Q = CL x VOUT FIGURE 5. Charge Injection FIGURE 6. Bandwidth Channel 1 On All Channels Off S1 S1 RIN S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S7 S7 S8 S8 VO S9 S10 S10 S11 S12 S13 S13 S14 S14 S15 S15 S16 S16 X TALK(AH) + 20 log 10 VO V FIGURE 7. All Hostile Crosstalk www.vishay.com 5-8 S11 RL S12 V VO S9 V RL X TALK(CD) + 20 log10 VO V FIGURE 8. Chip Disabled Crosstalk Document Number: 70070 S-02315—Rev. D, 05-Oct-00 DG535/536 Vishay Siliconix TEST CIRCUITS Channel 1 On S1 S2 S3 RIN S4 RIN 10 S5 S6 VSn–1 Sn–1 S7 VSn S8 S9 Sn VO S10 VSn+1 S11 V RL Sn+1 RIN 10 S12 RL 10 k S13 S14 S15 X TALK(AI) + 20 log10 S16 V Sn – 1 V Sn or 20 log10 V Sn ) 1 V Sn Notes: 1. Any individual channel between S2 and S16 can be selected 2. X TALK(SC) + 20 log10 VO V is scanned sequentially from S 2 to S 16 FIGURE 9. Single Channel Crosstalk FIGURE 10. Adjacent Input Crosstalk PIN DESCRIPTION Symbol S1 thru S16 D DIS CS, CS, EN A0 thru A3 Description Analog inputs/outputs Multiplexer output/demultiplexer input Open drain low impedance to analog ground when any channel is selected Logic inputs to selected desired multiplexer(s) when using several multiplexers in a system Binary address inputs to determine which channel is selected ST Strobe input that latches A0, A1, A2, A3, CS, CS, EN V+ Positive supply voltage input GND Document Number: 70070 S-02315—Rev. D, 05-Oct-00 Analog signal ground and most negative potential All ground pins should be connected externally to ensure dynamic performance www.vishay.com 5-9 DG535/536 Vishay Siliconix DETAILED DESCRIPTION The DG535/536 are 16-channel single-ended multiplexers with on-chip address logic and control latches. Signal IN SW1 The multiplexer connects one of sixteen inputs (S1, S2 through S16) to a common output (D) under the control of a 4-bit binary address (A0 to A3). The specific input channel selected for each address is given in the Truth Table. All four address inputs have on-chip data latches which are controlled by the Strobe (ST) input. These latches are transparent when Strobe is high but they maintain the chosen address when Strobe goes low. To facilitate easy microprocessor control in large matrices a choice of three independent logic inputs (EN, CS and CS) are provided on chip. These inputs are gated together (see Figure 11) and only when EN = CS = 1 and CS = 0 can an output switch be selected. This necessary logic condition is then latched-in when Strobe (ST) goes low. Signal OUT SW3 SW2 Signal GND FIGURE 12. “T” Switch Arrangement The two second level series switches further improve crosstalk and help to minimize output capacitance. The DIS output can be used to signal external circuitry. DIS is a high impedance to GND when no channel is selected and a low impedance to GND when any one channel is selected. CS Latch CS A1 Latch EN A2 Latch Decode Logic A0 Latch A3 Latch ST The DG535/536 have extensive applications where any high frequency video or digital signals are switched or routed. Exceptional crosstalk and bandwidth performance is achieved by using n-channel DMOS FETs for the “T” and series switches. ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Gate Source n+ FIGURE 11.CS, CS, EN, ST Control Logic Break-before-make switching prevents momentary shorting when changing from one input to another. The devices feature a two-level switch arrangement whereby two banks of eight switches (first level) are connected via two series switches (second level) to a common DRAIN output. In order to improve crosstalk all sixteen first level switches are configured as “T” switches (see Figure 12). With this method SW2 operates out of phase with SW1 and SW3. In the on condition SW1 and SW3 are closed with SW2 open whereas in the off condition SW1 and SW3 are open and SW2 closed. In the off condition the input to SW3 is effectively the isolation leakage of SW1 working into the on-resistance of SW2 (typically 200 ). www.vishay.com 5-10 Drain n+ p p– Substrate GND FIGURE 13. Cross-Section of a Single DMOS Switch It can clearly be seen from Figure 13 that there exists a PN junction between the substrate and the drain/source terminals. Should a signal which is negative with respect to the substrate (GND pin) be connected to a source or drain terminal, then the PN junction will become forward biased and current will flow between the signal source and GND. This effective shorting of the signal source to GND will not necessarily cause any damage to the device, provided that the total current flowing is less than the maximum rating, (i.e., 20 mA). Document Number: 70070 S-02315—Rev. D, 05-Oct-00 DG535/536 Vishay Siliconix DETAILED DESCRIPTION Since no PN junctions exist between the signal path and V+, positive overvoltages are not a problem, unless the breakdown voltage of the DMOS drain terminal (see Figure 13) (+18 V) is exceeded. Positive overvoltage conditions must not exceed +18 V with respect to the GND pin. If this condition is possible (e.g. transients in the signal), then a diode or Zener clamp may be used to prevent breakdown. The overvoltage conditions described may exist if the supplies are collapsed while a signal is present on the inputs. If this condition is unavoidable, then the necessary steps outlined above should be taken to protect the device being coupled back to the analog signal source and C2 blocks the dc bias from the output signal. Both C1 and C2 should be tantalum or ceramic disc type capacitors in order to operate efficiently at high frequencies. Active bias circuits are recommended if rapid switching time between channels is required. An alternative method is to offset the supply voltages (see Figure 15). Decoupling would have to be applied to the negative supply to ensure that the substrate is well referenced to signal ground. Again the capacitors should be of a type offering good high frequency characteristics. DC Biasing To avoid negative overvoltage conditions and subsequent distortion of ac analog signals, dc biasing may be necessary. Biasing is not required, however, in applications where signals are always positive with respect to the GND or substrate connection, or in applications involving multiplexing of low level (up to "200 mV) signals, where forward biasing of the PN substrate-source/drain terminals would not occur. Level shifting of the logic signals may be necessary using this offset supply arrangement. +12 V Analog Signal IN S V+ DG536 Biasing can be accomplished in a number of ways, the simplest of which is a resistive potential divider and a few dc blocking capacitors as shown in Figure 14. D Analog Signal OUT GND Decoupling Capacitors + –3 V +15 V Analog Signal IN C1 FIGURE 15. DG536 with Offset Supply R1 + S 100 F/16 V Tantalum R2 V+ C2 + DG536 GND D Analog Signal OUT 100 F/16 V Tantalum TTL to CMOS level shifting is easily obtained by using a MC14504B. Circuit Layout FIGURE 14. Simp le Bias Circuit R1 and R2 are chosen to suit the appropriate biasing requirements. For video applications, approximately 3 V of bias is required for optimal differential gain and phase performance. Capacitor C1 blocks the dc bias voltage from Document Number: 70070 S-02315—Rev. D, 05-Oct-00 Good circuit board layout and extensive shielding is essential for optimizing the high frequency performance of the DG536. Stray capacitances on the PC board and/or connecting leads will considerably degrade the ac performance. Hence, signal paths must be kept as short as practically possible, with extensive ground planes separating signal tracks. www.vishay.com 5-11