TC59LM818DMG-33,-40
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
Lead-Free
288Mbits Network FCRAM2
− 4,194,304-WORDS × 4 BANKS × 18-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMG is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM818DMG is organized as 4,194,304-words × 4 banks × 18
bits. TC59LM818DMG feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM818DMG can operate fast core cycle compared with regular DDR SDRAM.
TC59LM818DMG is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
TC59LM818DMG
PARAMETER
CL = 4
tCK
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock Cycle Time (min)
-33
-40
4.5 ns
5.0 ns
CL = 5
3.75 ns
4.5 ns
CL = 6
3.33 ns
4.0 ns
tRC
Random Read/Write Cycle Time (min)
22.5 ns
25 ns
tRAC
Random Access Time (max)
22.5 ns
25 ns
IDD1S Operating Current (single bank) (max)
235 mA
210 mA
lDD2P Power Down Current (max)
65 mA
60 mA
lDD6
15 mA
15 mA
Self-Refresh Current (max)
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
Fast clock cycle time of 3.33 ns minimum
Clock: 300 MHz maximum
Data: 600 Mbps/pin maximum
Quad Independent Banks operation
Fast cycle and Short Latency
Selectable Data Strobe
Distributed Auto-Refresh cycle in 3.9 µs
Self-Refresh
Power Down Mode
Variable Write Length Control
Write Latency = CAS Latency-1
Programable CAS Latency and Burst Length
CAS Latency = 4, 5, 6
Burst Length = 2, 4
Organization: 4,194,304 words × 4 banks × 18 bits
Power Supply Voltage VDD:
2.5 V ± 0.125V
VDDQ: 1.4 V ~ 1.9 V
Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL
Package:
60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ)
Lead-Free
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Rev 1.4
2005-10-19
1/57
TC59LM818DMG-33,-40
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
ball pitch=1.0 x 1.0mm
PIN
NAME
x18
A0~A14
Address Input
BA0, BA1
Bank Address
DQ0~DQ17
Data Input/Output
CS
Chip Select
FN
Function Control
PD
Power Down Control
CLK, CLK
Clock Input
DS / QS
Write/Read Data Strobe
VDD
Power (+2.5 V)
VSS
Ground
VDDQ
Power (+1.5 V, +1.8 V)
(for DQ buffer)
VSSQ
Ground
(for DQ buffer)
VREF
Reference Voltage
NC
Not Connected
1
2
VSS
DQ17
DQ0
VDD
B
DQ16
VSSQ
VDDQ
DQ1
C
DQ15
VDDQ
VSSQ
DQ2
D
DQ14
DQ13
DQ4
DQ3
E
DQ12
VSSQ
VDDQ
DQ5
F
DQ11
VDDQ
VSSQ
DQ6
G
DQ10
VSSQ
VDDQ
DQ7
H
DQ9
DS
QS
DQ8
J
VREF
VSS
VDD
A14
K
CLK
CLK
FN
A13
L
A12
PD
CS
NC
M
A11
A9
BA1
BA0
N
A8
A7
A0
A10
P
A5
A6
A2
A1
R
VSS
A4
A3
VDD
A
Index
3
4
5
6
: Depopulated Ball
Rev 1.4
2005-10-19
2/57
TC59LM818DMG-33,-40
BLOCK DIAGRAM
CLK
CLK
PD
CS
FN
DLL
CLOCK
BUFFER
COMMAND
DECODER
To each block
CONTROL
SIGNAL
GENERATOR
BANK #3
BANK #2
BANK #1
BA0, BA1
ADDRESS
BUFFER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
REFRESH
COUNTER
BURST
COUNTER
ROW DECODER
A0~A14
DATA
CONTROL and LATCH
CIRCUIT
BANK #0
MODE
REGISTER
MEMORY
CELL ARRAY
COLUMN DECODER
READ
DATA
BUFFER
WRITE ADDRESS
LATCH/
ADDRESS
COMPARATOR
DS
QS
WRITE
DATA
BUFFER
DQ BUFFER
DQ0~DQ17
Note: The TC59LM818DMG configuration is 4 Bank of 32768 × 128 × 18 of cell array with the DQ pins numbered DQ0~DQ17.
Rev 1.4
2005-10-19
3/57
TC59LM818DMG-33,-40
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
−0.3~ 3.3
V
VDD
Power Supply Voltage
VDDQ
Power Supply Voltage (for DQ buffer)
−0.3~VDD+ 0.3
V
VIN
Input Voltage
−0.3~VDD+ 0.3
V
VOUT
Output and DQ pin Voltage
−0.3~VDDQ + 0.3
V
VREF
Input Reference Voltage
−0.3~VDD+ 0.3
V
Topr
Operating Temperature (case)
0~85
°C
Tstg
Storage Temperature
−55~150
°C
Tsolder
Soldering Temperature (10 s)
260
°C
PD
Power Dissipation
2
W
IOUT
Short Circuit Output Current
±50
mA
NOTES
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1) (TCASE = 0°C ~ 85°C)
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
2.375
2.5
2.625
V
1.4
1.9
V
NOTES
VDD
Power Supply Voltage
VDDQ
Power Supply Voltage (for DQ buffer)
VREF
Reference Voltage
VDDQ/2 × 95%
VDDQ/2
VDDQ/2 × 105%
V
2
VIH (DC)
Input DC High Voltage
VREF + 0.125
VDDQ + 0.2
V
5
VIL (DC)
Input DC Low Voltage
−0.1
VREF − 0.125
V
5
VICK (DC)
Differential Clock DC Input Voltage
−0.1
VDDQ + 0.1
V
10
VID (DC)
Differential Input Voltage.
CLK and CLK inputs (DC)
0.4
VDDQ + 0.2
V
7, 10
VIH (AC)
Input AC High Voltage
VREF + 0.2
VDDQ + 0.2
V
3, 6
VIL (AC)
Input AC Low Voltage
−0.1
VREF − 0.2
V
4, 6
VID (AC)
Differential InputVoltage.
CLK and CLK inputs (AC)
0.55
VDDQ + 0.2
V
7, 10
VX (AC)
Differential AC Input Cross Point Voltage
VDDQ/2 − 0.125
VDDQ/2 + 0.125
V
8, 10
VISO (AC)
Differential Clock AC Middle Level
VDDQ/2 − 0.125
VDDQ/2 + 0.125
V
9, 10
Rev 1.4
2005-10-19
4/57
TC59LM818DMG-33,-40
NOTES:
(1)
All voltages referenced to VSS, VSSQ.
(2)
VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3)
Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns.
(4)
Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns.
(5)
VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6)
VIH (AC) and VIL (AC) are levels to change to the new logic state.
(7)
VID is differential voltage of CLK input level and CLK input level.
(8)
The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9)
VISO means {VICK (CLK) + VICK ( CLK )} /2
(10)
Refer to the figure below.
CLK
Vx
Vx
Vx
Vx
Vx
VID (AC)
CLK
VICK
VICK
VICK
VISO (min)
VISO (max)
VICK
VSS
|VID (AC)|
0 V Differential
VISO
VSS
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC)
± 0.04 V.
CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C)
SYMBOL
PARAMETER
MIN
MAX
Delta
UNIT
CIN
Input pin Capacitance
1.5
3.0
0.25
pF
CINC
Clock pin (CLK, CLK ) Capacitance
1.5
3.0
0.25
pF
CI/O
DQ, DS, QS Capacitance
2.5
3.5
0.5
pF
CNC
NC pin Capacitance
1.5
pF
Note: These parameters are periodically sampled and not 100% tested.
Rev 1.4
2005-10-19
5/57
TC59LM818DMG-33,-40
RECOMMENDED DC OPERATING CONDITIONS
(VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C)
SYMBOL
PARAMETER
MAX
UNIT
NOTES
-33
-40
IDD1S
Operating Current
One bank read or write operation ;
tCK = min; IRC = min, IOUT = 0mA ;
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
Address inputs change up to 2 times during minimum IRC,
Read data change twice per clock cycle
235
210
1, 2
IDD2N
Standby Current
All banks: inactive state ;
tCK = min, CS = VIH, PD = VIH ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Other input signals change one time during 4 × tCK,
DQ and DS inputs change twice per clock cycle
95
90
1, 2
IDD2P
Standby (power down) Current
All banks: inactive state ;
tCK = min, PD = VIL (power down) ;
CAS Latency = 6, Free running QS mode ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Other input signals change one time during 4 × tCK,
DQ and DS inputs are floating (VDDQ/2)
65
60
1, 2
IDD4W
Write Operating Current (4Banks)
4 Bank interleaved continuous burst write operation ;
tCK = min, IRC = min ;
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change once per clock cycle,
DQ and DS inputs change twice per clock cycle
450
400
1, 2
IDD4R
Read Operating Current (4Banks)
4 Bank interleaved continuous burst read operation ;
tCK = min, IRC = min, IOUT = 0mA ;
Burst Length = 4, CAS Latency = 6, Free running QS mode ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;
Address inputs change once per clock cycle,
Read data change twice per clock cycle
450
400
1, 2
IDD5B
Burst Auto Refresh Current
Refresh command at every IREFC interval ;
tCK = min; IREFC = min ;
CAS Latency = 6, Free running QS mode ;
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
Address inputs change up to 2 times during minimum IREFC,
DQ and DS inputs change twice per clock cycle
235
210
1, 2, 3
IDD6
Self-Refresh Current
PD = 0.2 V ;
Other input signals are floating (VDDQ/2),
DQ and DS inputs are floating (VDDQ/2)
15
15
2
mA
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC.
2. These parameters define the current between VDD and VSS.
3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI
specification.
Rev 1.4
2005-10-19
6/57
TC59LM818DMG-33,-40
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
ILI
Input Leakage Current
( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V)
−5
5
µA
ILO
Output Leakage Current
(Output disabled, 0 V ≤ VOUT ≤ VDDQ)
−5
5
µA
IREF
VREF Current
−5
5
µA
VOH = 1.420 V
−5.6
VOL = 0.280 V
5.6
VOH = 1.420 V
−9.8
(VDDQ = 1.7V~1.9V) V = 0.280 V
OL
9.8
VOH = 1.420 V
−2.8
VOL = 0.280 V
2.8
VOH = VDDQ – 0.4V
−4
VOL = 0.4V
4
VOH = VDDQ – 0.4V
−8
8
Not defined
Not defined
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
IOH (DC)
IOL (DC)
Normal Output
Driver
Strong Output
Driver
Output DC Current
Weak
Output Driver
Normal
Output Driver
Strong
Output Driver
Weak
Output Driver
Output DC Current
(VDDQ = 1.4V~1.6V) V = 0.4V
OL
NOTES
mA
1
mA
1
Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
Rev 1.4
2005-10-19
7/57
TC59LM818DMG-33,-40
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(VDD = 2.5 V ± 0.125V, VDDQ = 1.4V ~ 1.9V, TCASE = 0 ~ 85°C)
-33
SYMBOL
tRC
tCK
-40
PARAMETER
UNIT
MAX
MIN
MAX
22.5
25
3
CL = 4
4.5
7.5
5.0
7.5
3
CL = 5
3.75
7.5
4.5
7.5
3
CL = 6
3.33
7.5
4.0
7.5
3
22.5
25
3
Random Cycle Time
Clock Cycle Time
NOTES
MIN
tRAC
Random Access Time
tCH
Clock High Time
0.45 × tCK
0.45 × tCK
3
tCL
Clock Low Time
0.45 × tCK
0.45 × tCK
3
tCKQS
QS Access Time from CLK
−0.45
0.45
−0.6
0.6
3, 8, 10
tQSQ
Data Output Skew from QS
0.25
0.3
tAC
Data Access Time from CLK
−0.5
0. 5
−0.65
0.65
3, 8, 10
tOH
Data Output Hold Time from CLK
−0.5
0.5
−0.65
0.65
3, 8
tHP
CLK half period
(minimum of Actual tCH, tCL)
min
(tCH, tCL)
min
(tCH, tCL)
3
tQSP
QS (read) Pulse Width
tHP−tQHS
tHP−tQHS
4, 8
tQSQV
Data Output Valid Time from QS
tHP− tQHS
tHP− tQHS
4, 8
tQHS
DQ, QS Hold Skew factor
0.055×tCK +
0.17
0.055×tCK +
0.17
tDQSS
DS (write) Low to High Setup Time
0.8 × tCK
1.2 × tCK
0.8 × tCK
1.2 × tCK
tDSPRE
DS (write) Preamble Pulse Width
0.4 × tCK
0.4 × tCK
3
4
ns
0
0
DS First Low Input Hold Time
0.3 × tCK
0.3 × tCK
3
tDSP
DS High or Low Input Pulse Width
0.45 × tCK
0.55 × tCK
0.45 × tCK
0.55 × tCK
4
CL = 4
0.8
1.0
3, 4
tDSS
DS Input Falling Edge
to Clock Setup Time
CL = 5
0.8
1.0
3, 4
CL = 6
0.8
1.0
3, 4
0.45 × tCK
0.45 × tCK
4
CL = 4
0.8
1.0
3, 4
CL = 5
0.8
1.0
3, 4
CL = 6
0.8
1.0
3, 4
tDSPRES
DS First Input Setup Time
tDSPREH
tDSPST
DS (write) Postamble Pulse Width
tDSPSTH
DS (write) Postamble
Hold Time
3
tDS
Data Input Setup Time from DS
0.35
0.4
4
tDH
Data Input Hold Time from DS
0.35
0.4
4
tIS
Command/Address Input Setup
Time
0.6
0.7
3
tIH
Command/Address Input Hold
Time
0.6
0.7
3
tLZ
Data-out Low Impedance Time
from CLK
−0.5
−0.65
3,6,8
tHZ
Data-out High Impedance Time
from CLK
0.5
0.65
3,7,8
Rev 1.4
2005-10-19
8/57
TC59LM818DMG-33,-40
AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-33
SYMBOL
-40
PARAMETER
UNIT
MIN
MAX
MIN
MAX
0
0
tQPDH
Last output to PD High Hold
Time
tPDEX
Power Down Exit Time
0.6
0.7
tT
Input Transition Time
0.1
1
0.1
1
tFPDL
PD Low Input Window for
Self-Refresh Entry
−0.5 × tCK
5
−0.5 × tCK
5
tREFI
Auto-Refresh Average Interval
0.4
3.9
0.4
3.9
tPAUSE
Pause Time after Power-up
200
200
CL = 4
5
5
IRC
Random Read/Write
Cycle Time
(applicable to same
bank)
CL = 5
6
6
CL = 6
7
7
1
1
1
1
CL = 4
4
4
CL = 5
5
5
CL = 6
6
6
2
2
2
2
3
3
1
1
CL = 4
7
7
CL = 5
7
7
CL = 6
7
7
IRCD
RDA/WRA to LAL Command Input
Delay
(applicable to same bank)
IRAS
LAL to RDA/WRA
Command Input Delay
(applicable to same
bank)
IRBD
IRWD
IWRD
IRSC
Random Bank Access Delay
(applicable to other bank)
LAL following RDA to
BL = 2
WRA Delay
(applicable to other
BL = 4
bank)
LAL following WRA to RDA Delay
(applicable to other bank)
Mode Register Set
Cycle Time
IPD
PD Low to Inactive State of Input
Buffer
2
2
IPDA
PD High to Active State of Input
Buffer
1
1
19
19
IPDV
CL = 4
Power down mode valid
CL = 5
from REF command
CL = 6
23
23
25
25
CL = 4
19
19
CL = 5
23
23
CL = 6
25
25
IREFC
IREFC
200
200
IREFC
Auto-Refresh Cycle
Time
ICKD
REF Command to Clock Input
Disable at Self-Refresh Entry
ILOCK
DLL Lock-on Time (applicable to
RDA command)
NOTES
3
ns
3
5
µs
cycle
Rev 1.4
2005-10-19
9/57
TC59LM818DMG-33,-40
AC TEST CONDITIONS
SYMBOL
PARAMETER
VALUE
UNIT
VIH (min)
Input High Voltage (minimum)
VREF + 0.2
V
VIL (max)
Input Low Voltage (maximum)
VREF − 0.2
V
VREF
Input Reference Voltage
VDDQ/2
V
VTT
Termination Voltage
VREF
V
VSWING
Input Signal Peak to Peak Swing
0.8
V
Vr
Differential Clock Input Reference Level
VX (AC)
V
VID (AC)
Input Differential Voltage
1.0
V
SLEW
Input Signal Minimum Slew Rate
2.5
V/ns
VOTR
Output Timing Measurement Reference Voltage
VDDQ/2
V
NOTES
9
VDDQ
VIH min (AC)
VTT
25 Ω
VREF
VSWING
Output
VIL max (AC)
VSS
Measurement point
∆T
∆T
SLEW = (VIH min (AC) − VIL max (AC))/∆T
AC Test Load
NOTES:
(1)
Transition times are measured between VIH min (DC) and VIL max (DC).
Transition (rise and fall) of input signals have a fixed slope.
(2)
If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is
rounded up to the nearest decimal place.
(i.e., tDQSS = 0.8 × tCK, tCK = 3.3 ns, 0.8 × 3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
(3)
These parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4)
These parameters are measured from signal transition point of DS crossing VREF level.
(5)
The tREFI (max) applies to equally distributed refresh method.
The tREFI (min) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximum.
(6)
Low Impedance State is specified at VDDQ/2 ± 0.1 V from steady state.
(7)
High Impedance State is specified where output buffer is no longer driven.
(8)
These parameters depend on the clock jitter. These parameters are measured at stable clock.
(9)
Output timing is measured by using Normal driver strength at VDDQ = 1.7 V ∼ 1.9 V.
Output timing is measured by using Strong driver strength at VDDQ = 1.4 V ∼ 1.6 V.
(10)
These parameters are measured at tCK = minimum ∼6.0ns. When tCK is longer than 6.0ns, these parameters
are specified as below for all speed version.
tCKQS (MIN/MAX) = −0.6ns / 0.6ns, tAC (MIN/MAX) = −0.65ns / 0.65ns
Rev 1.4
2005-10-19
10/57
TC59LM818DMG-33,-40
POWER UP SEQUENCE
(1)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2)
Apply VDD before or at the same time as VDDQ.
(3)
Apply VDDQ before or at the same time as VREF.
(4)
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5)
After stable power and clock, apply DESL and take PD =H.
(6)
Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1)
(7)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8)
Issue two or more Auto-Refresh commands (Note: 1).
(9)
Ready for normal operation after 200 clocks from Extended Mode Register programming.
NOTES:
(1)
Sequence 6, 7 and 8 can be issued in random order.
(2)
L = Logic Low, H = Logic High
(3)
DQ output is Hi-Z state during power upsequence.
2.5V(TYP)
VDD
1.5V or 1.8V(TYP)
VDDQ
1/2 VDDQ (TYP)
VREF
CLK
CLK
tPDEX
lRSC
200us(min)
lRSC
PD
lREFC
lREFC
lLOCK = 200clock cycle(min)
lPDA
Command
DESL RDA MRS DESL
op-code
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
Address
EMRS
MRS
DQ
(Input)
DS
QS
Low
(Uni-QS mode)
QS
(Free Running mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
Rev 1.4
2005-10-19
11/57
TC59LM818DMG-33,-40
TIMING DIAGRAMS
Input Timing
Command and Address
tCK
tCK
tCH
tCL
CLK
CLK
tIS
tIH
tIS
1st
CS
tIS
2nd
tIH
tIS
1st
FN
tIS
A0~A14
BA0, BA1
tIH
tIH
2nd
tIH
tIS
UA, BA
tIH
LA
Data
DS
tDS
tDH
tDS
tDH
DQn (input)
tDS
tDH
tDS
tDH
DQm (input)
Refer to the Command Truth Table.
Timing of the CLK, CLK
tCH
tCL
VIH
VIH (AC)
VIL (AC)
VIL
CLK
CLK
tT
tCK
tT
CLK
VIH
CLK
VIL
VID (AC)
VX
VX
VX
Rev 1.4
2005-10-19
12/57
TC59LM818DMG-33,-40
Read Timing (Burst Length = 4)
Unidirectional DS/QS mode
tCH
tCL
tCK
CLK
CLK
tIS tIH
LAL (after RDA)
Input
(control &
addresses)
DESL
DS
(Input)
tCKQS
CAS latency = 4
QS
(output)
tCKQS
tCKQS tQSP tQSP
Low
Low
tQSQV
tLZ
tQSQ
tQSQ tQSQ tQSQV
DQ
(output)
Hi-Z
Q0
tAC
Q1
Q2
tAC
tHZ
Q3
tAC
tOH
tCKQS
CAS latency = 5
QS
(output)
tCKQS
tCKQS
tQSP
tQSP
Low
Low
tLZ
tQSQV
tQSQ
tQSQ tQSQ tQSQV
DQ
(output)
Hi-Z
Q0
tAC
Q1
tAC
Q2
tHZ
Q3
tAC
tOH
tCKQS
CAS latency = 6
QS
(output)
Low
Low
tLZ
DQ
(output)
tCKQS
tCKQS tQSP tQSP
Hi-Z
tAC
tQSQV
tQSQ
tQSQ tQS
tQSQV
Q0
Q2
Q1
tAC
tHZ
Q3
tAC
tOH
Note: DQ0 to DQ17 are aligned with QS.
Rev 1.4
2005-10-19
13/57
TC59LM818DMG-33,-40
Read Timing (Burst Length = 4)
Unidirectional DS/Free Running QS mode
tCH
tCL
tCK
CLK
CLK
tIS tIH
LAL (after RDA)
Input
(control &
addresses)
DESL
DS
(Input)
tCKQS
CAS latency = 4
tCKQS
tCKQS
tQSP tQSP
QS
(output)
tLZ
tQSQV
tQSQ
tQSQ tQSQ tQSQV
DQ
(output)
Hi-Z
Q0
tAC
Q1
tAC
Q2
tHZ
Q3
tAC
tOH
tCKQS
CAS latency = 5
tCKQS
tCKQS
tQSP tQSP
QS
(output)
tLZ
tQSQV
tQSQ
tQSQ tQSQ tQSQV
DQ
(output)
Hi-Z
Q0
tAC
Q1
tAC
Q2
tHZ
Q3
tAC
tOH
tCKQS
CAS latency = 6
tCKQS
tCKQS
tQSP tQSP
QS
(output)
tLZ
tQSQV
tQSQ
tQSQ tQSQ tQSQV
DQ
(output)
Hi-Z
Q0
tAC
Q1
tAC
Q2
tHZ
Q3
tAC
tOH
Note: DQ0 to DQ17 are aligned with QS.
QS is always asserted in Free Running QS mode.
Rev 1.4
2005-10-19
14/57
TC59LM818DMG-33,-40
Write Timing (Burst Length = 4)
Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode
tCH
tCL
tCK
CLK
CLK
tIS tIH LAL (after WRA)
Input
(control &
addresses)
DESL
tDSPSTH
tDQSS
tDSS
tDSPRES
CAS latency = 4
tDSPREH
tDSP tDSP tDSP
tDSPST
DS
(input)
tDSS
Preamble
tDSPRE
tDS
tDS
tDS
tDH
tDH
DQ
(input)
Postamble
D0
D1
D2
tDH
D3
tDQSS
CAS latency = 5
tDSPRES
t
tDSPREH DSP
tDSS
tDSPSTH
tDSS
tDSP tDSP tDSPST
DS
(input)
Preamble
tDSPRE
Postamble
tDS
tDH
DQ
(input)
D0
D1
tDS
tDH
tDH
D3
D2
tDQSS
tDQSS
CAS latency = 6
tDS
tDSS
tDSPSTH
tDSS
tDSPRES
tDSP tDSP tDSP
tDSPREH
tDSPST
DS
(input)
Preamble
tDSPRE
Postamble
tDS
tDS
tDH
DQ
(input)
D0
tDQSS
QS
(Uni-QS)
tDS
tDH
D1
D2
tDH
D3
tDQSS
Low
QS
(Free Runninig)
Note: DQ0 to DQ17 are sampled at both edges of DS.
Rev 1.4
2005-10-19
15/57
TC59LM818DMG-33,-40
tREFI, tPAUSE, IXXXX Timing
CLK
CLK
tREFI, tPAUSE, IXXXX
tIS tIH
tIS tIH
Input
(control &
addresses)
Command
Command
Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc.
Rev 1.4
2005-10-19
16/57
TC59LM818DMG-33,-40
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL
FUNCTION
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
DESL
Device Deselect
H
×
×
×
×
×
×
RDA
Read with Auto-close
L
H
BA
UA
UA
UA
UA
WRA
Write with Auto-close
L
L
BA
UA
UA
UA
UA
• The Second Command (The next clock of RDA or WRA command)
SYMBOL
FUNCTION
CS
FN
BA1~
BA0
A14~
A13
A12~
A11
A10~A9
A8
A7
A6~A0
LAL
Lower Address Latch
H
×
×
V
×
×
×
×
LA
REF
Auto-Refresh
L
×
×
×
×
×
×
×
×
MRS
Mode Register Set
L
×
V
L
L
L
L
V
V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
RDA (1st)
L
H
BA
UA
UA
UA
UA
LAL (2nd)
H
×
×
×
×
×
LA
NOTES
Write Command Table
COMMAND(SYMBOL)
CS
FN
BA1~
BA0
A14
A13
A12
A11
A10~
A9
A8
A7
A6~A0
WRA (1st)
L
L
BA
UA
UA
UA
UA
UA
UA
UA
UA
LAL (2nd)
H
×
×
VW0
VW1
×
×
×
×
×
LA
Notes: 5. A14~ A13 are used for Variable Write Length (VW) control at Write Operation.
VW Truth Table
Burst Length
Function
VW0
VW1
Write All Words
L
×
Write First One Word
H
×
Reserved
L
L
Write All Words
H
L
Write First Two Words
L
H
Write First One Word
H
H
BL=2
BL=4
Rev 1.4
2005-10-19
17/57
TC59LM818DMG-33,-40
FUNCTION TRUTH TABLE (continued)
Mode Register Set Command Table
COMMAND (SYMBOL)
CS
FN
BA1~BA0
A14~A9
A8
A7
A6~A0
RDA (1st)
L
H
×
×
×
×
×
MRS (2nd)
L
×
V
L
L
V
V
CS
FN
BA1~BA0
A14~A9
A8
A7
NOTES
6
Notes: 6. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Auto-Refresh
REF (2nd)
FUNCTION
PD
A6~A0 NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
Active
H
H
L
×
×
×
×
×
×
CS
FN
BA1~BA0
A14~A9
A8
A7
Self-Refresh Command Table
COMMAND
(SYMBOL)
CURRENT
STATE
Active
WRA (1st)
Self-Refresh Entry
FUNCTION
PD
A6~A0 NOTES
n−1
n
Standby
H
H
L
L
×
×
×
×
×
REF (2nd)
Active
H
L
L
×
×
×
×
×
×
Self Refresh
L
L
×
×
×
×
×
×
×
SELFX
Self Refresh
L
H
H
×
×
×
×
×
×
COMMAND
(SYMBOL)
CURRENT
STATE
CS
FN
BA1~BA0
A14~A9
A8
A7
PDEN
Self-Refresh
Continue
Self-Refresh Exit
7, 8
9
Power Down Table
FUNCTION
Power Down Entry
Power Down Continue
Power Down Exit
Notes: 7.
8.
PD
A6~A0 NOTES
n−1
n
Standby
H
L
H
×
×
×
×
×
×
Power
Down
L
L
×
×
×
×
×
×
×
PDEX
Power
Down
L
H
H
×
×
×
×
×
×
8
9
PD has to be brought to Low within tFPDL from REF command.
PD should be brought to Low after DQ’s state turned high impedance.
9. When PD is brought to High from Low, this function is executed asynchronously.
Rev 1.4
2005-10-19
18/57
TC59LM818DMG-33,-40
FUNCTION TRUTH TABLE (continued)
CURRENT STATE
PD
CS
FN
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
Row Active for Read
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
Op-code
×
×
×
LAL
MRS/EMRS
PDEN
MRS/EMRS
Row Active for Write
H
H
H
H
L
H
H
L
L
×
H
L
H
L
×
×
×
×
×
×
LA
×
×
×
×
LAL
REF
PDEN
REF (self)
Read
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
Continue Burst Read to End
Illegal
Illegal
Illegal
Illegal
Invalid
Write
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
Data Write&Continue Burst Write to End
Illegal
Illegal
Illegal
Illegal
Invalid
Auto-Refreshing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
NOP → Idle after IREFC
Illegal
Illegal
Self-Refresh Entry
Illegal
Refer to Self-Refreshing State
Mode Register
Accessing
H
H
H
H
H
L
H
H
H
L
L
×
H
L
L
H
L
×
×
H
L
×
×
×
×
BA, UA
BA, UA
×
×
×
DESL
RDA
WRA
PDEN
NOP → Idle after IRSC
Illegal
Illegal
Illegal
Illegal
Invalid
H
L
×
L
×
×
×
×
×
×
L
H
H
×
×
PDEX
L
H
L
×
×
Invalid
Maintain Power Down Mode
Exit Power Down Mode → Idle after
tPDEX
Illegal
H
L
L
L
×
L
H
H
×
×
H
L
×
×
×
×
×
×
×
×
SELFX
Invalid
Maintain Self-Refresh
Exit Self-Refresh → Idle after IREFC
Illegal
n−1
n
Idle
H
H
H
H
H
L
Power Down
Self-Refreshing
ADDRESS COMMAND
ACTION
NOTES
NOP
Row activate for Read
Row activate for Write
Power Down Entry
Illegal
Refer to Power Down State
10
Begin Read
Access to Mode Register
Illegal
Illegal
Invalid
Begin Write
Auto-Refresh
Illegal
Self-Refresh Entry
Invalid
11
11
11
11
12
Notes: 10. Illegal if any bank is not idle.
11. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
12. Illegal if tFPDL is not satisfied.
Rev 1.4
2005-10-19
19/57
TC59LM818DMG-33,-40
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
*1
ADDRESS
*1
BA1
BA0
0
0
Register
A14~A8
A7
0
*3
A6~A4
A3
A2~A0
CL
BT
BL
TE
A7
TEST MODE (TE)
A3
BURST TYPE (BT)
0
Regular (default)
0
Sequential
1
Test Mode Entry
1
Interleave
A6
A5
A4
CAS LATENCY (CL)
0
0
×
Reserved
0
1
0
Reserved
Reserved
*2
*2
*2
A2
A1
A0
0
0
0
0
0
1
2
0
1
0
4
0
1
1
1
0
0
4
0
1
1
1
0
1
5
1
×
×
1
1
0
6
1
1
1
Reserved
BURST LENGTH (BL)
Reserved
Reserved
*2
*2
*2
Extended Mode Register (Notes: 4)
ADDRESS
*4
*4
BA1
BA0
0
1
Register
A14~A7
A6~A5
A4~A3
A2~A1
0
SS
DIC (QS)
DIC (DQ)
QS
A6
0
A5
0
DQ
Reserved
Reserved
*2
*5
DS
A4
A3
A2
A1
OUTPUT DRIVE IMPEDANCE CONTROL
(DIC)
0
0
0
0
Normal Output Driver
0
1
0
1
Strong Output Driver
STROBE SELECT
*2
A0
0
1
1
0
Unidirectional DS/QS
1
0
1
0
Weak Output Driver
1
1
Unidirectional DS/Free Running QS
1
1
1
1
Reserved
A0
DLL SWITCH (DS)
0
DLL Enable
1
DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
Rev 1.4
2005-10-19
20/57
TC59LM818DMG-33,-40
STATE DIAGRAM
SELFREFRESH
POWER
DOWN
SELFX
( PD = H)
PDEX
( PD = H)
PD = L
PDEN
( PD = L)
STANDBY
(IDLE)
PD = H
AUTOREFRESH
MODE
REGISTER
WRA
RDA
REF
MRS
ACTIVE
(RESTORE)
ACTIVE
LAL
LAL
WRITE
(BUFFER)
READ
Command input
Automatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
Rev 1.4
2005-10-19
21/57
TC59LM818DMG-33,-40
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 4 cycles
LA
RDA
LAL
IRCD=1 cycle
UA
DESL
IRAS = 4 cycles
LA
IRC = 5 cycles
RDA
IRCD=1 cycle
UA
#0
LAL
DESL
RDA
IRAS = 4 cycles
LA
UA
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1
CL = 4
Q0 Q1
Q0
BL = 4
DS
(input)
QS
(output)
Low
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1 Q2 Q3
CL = 4
Q0 Q1 Q2 Q3
Q0
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1
CL = 4
Q0 Q1
Q0
BL = 4
DS
(input)
QS
(output)
CL = 4
DQ
(output)
Hi-Z
CL = 4
Q0 Q1 Q2 Q3
CL = 4
Q0 Q1 Q2 Q3
Q0
Rev 1.4
2005-10-19
22/57
TC59LM818DMG-33,-40
SINGLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RDA
LAL
14
15
CLK
CLK
IRC = 6 cycles
IRC = 6 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 5 cycles
LA
RDA
LAL
IRCD=1 cycle
UA
DESL
IRAS = 5 cycles
LA
IRCD=1 cycle
UA
#0
DESL
LA
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
DQ
(output)
Hi-Z
CL = 5
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
Low
CL = 5
DQ
(output)
Hi-Z
CL = 5
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
DQ
(output)
Hi-Z
CL = 5
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
CL = 5
DQ
(output)
Hi-Z
CL = 5
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
Rev 1.4
2005-10-19
23/57
TC59LM818DMG-33,-40
SINGLE BANK READ TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
LAL
CLK
CLK
IRC = 7 cycles
IRC = 7 cycles
Command
RDA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
IRAS = 6 cycles
LA
RDA
LAL
IRCD=1 cycle
UA
DESL
IRAS = 6 cycles
LA
IRCD=1 cycle
UA
#0
LA
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
DQ
(output)
Hi-Z
CL = 6
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
Low
CL = 6
DQ
(output)
Hi-Z
CL = 6
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
DQ
(output)
Hi-Z
CL = 6
Q0 Q1
Q0 Q1
BL = 4
DS
(input)
QS
(output)
CL = 6
DQ
(output)
Hi-Z
CL = 6
Q0 Q1 Q2 Q3
Q0 Q1 Q2
Rev 1.4
2005-10-19
24/57
TC59LM818DMG-33,-40
SINGLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
Command
WRA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
WRA
IRAS = 4 cycles
LA
LAL
IRCD=1 cycle
UA
IRC = 5 cycles
DESL
WRA
IRAS = 4 cycles
LA
IRCD=1 cycle
UA
#0
LAL
DESL
WRA
IRAS = 4 cycles
LA
UA
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 3
DQ
(input)
WL = 3
D0 D1
WL = 3
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
Low
WL = 3
DQ
(input)
WL = 3
D0 D1 D2 D3
WL = 3
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 3
DQ
(input)
WL = 3
D0 D1
WL = 3
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 3
DQ
(input)
WL = 3
D0 D1 D2 D3
WL = 3
D0 D1 D2 D3
D0 D1 D2 D3
Rev 1.4
2005-10-19
25/57
TC59LM818DMG-33,-40
SINGLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
WRA
LAL
14
15
CLK
CLK
IRC = 6 cycles
IRC = 6 cycles
Command
WRA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
WRA
IRAS = 5 cycles
LAL
IRCD=1 cycle
LA
UA
DESL
IRAS = 5 cycles
DESL
IRCD=1 cycle
LA
UA
#0
LA
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 4
DQ
(input)
WL = 4
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
Low
WL = 4
DQ
(input)
WL = 4
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
DQ
(input)
WL = 4
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 4
DQ
(input)
WL = 4
D0 D1 D2 D3
D0 D1 D2 D3
Rev 1.4
2005-10-19
26/57
TC59LM818DMG-33,-40
SINGLE BANK WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
WRA
LAL
CLK
CLK
IRC = 7 cycles
IRC = 7 cycles
Command
WRA
LAL
IRCD=1 cycle
Address
UA
Bank Add.
#0
DESL
WRA
IRAS = 6 cycles
LAL
IRCD=1 cycle
LA
UA
DESL
IRAS = 6 cycles
IRCD=1 cycle
LA
UA
#0
LA
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 5
DQ
(input)
WL = 5
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
Low
WL = 5
DQ
(input)
WL = 5
D0 D1 D2 D3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 5
DQ
(input)
WL = 5
D0 D1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 5
DQ
(input)
WL = 5
D0 D1 D2 D3
D0 D1 D2 D3
Rev 1.4
2005-10-19
27/57
TC59LM818DMG-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
IRC = 5 cycles
IRC = 5 cycles
RDA
LAL
Address
UA
LA
Bank Add.
#0
Command
DESL
WRA
LAL
UA
LA
DESL
IRC = 5 cycles
RDA
LAL
UA
LA
#0
DESL
WRA
UA
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1
CL = 4
D0 D1
Q0
BL = 4
DS
(input)
QS
(output)
Low
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1 Q2 Q3
CL = 4
D0 D1 D2 D3
Q0
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
DQ
Hi-Z
WL = 3
Q0 Q1
CL = 4
D0 D1
Q0
BL = 4
DS
(input)
QS
(output)
CL = 4
DQ
Hi-Z
WL = 3
CL = 4
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Read data
Write data
Q0
Rev 1.4
2005-10-19
28/57
TC59LM818DMG-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
RDA
LAL
UA
LA
14
15
CLK
CLK
IRC = 6 cycles
IRC = 6 cycles
RDA
LAL
Address
UA
LA
Bank Add.
#0
Command
DESL
WRA
LAL
UA
LA
DESL
#0
DESL
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
DQ
Hi-Z
WL = 4
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
Low
WL = 4
CL = 5
DQ
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
DQ
Hi-Z
WL = 4
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 4
CL = 5
DQ
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Read data
Write data
Rev 1.4
2005-10-19
29/57
TC59LM818DMG-33,-40
SINGLE BANK READ-WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
LAL
UA
LA
CLK
CLK
IRC = 7 cycles
IRC = 7 cycles
RDA
LAL
Address
UA
LA
Bank Add.
#0
Command
DESL
WRA
LAL
UA
LA
DESL
#0
#0
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
DQ
Hi-Z
WL = 5
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
Low
WL = 5
CL = 6
DQ
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
DQ
Hi-Z
WL = 5
Q0 Q1
D0 D1
BL = 4
DS
(input)
QS
(output)
WL = 5
CL = 6
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Read data
Write data
Rev 1.4
2005-10-19
30/57
TC59LM818DMG-33,-40
MULTIPLE BANK READ TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cyclesIRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL RDA
Bank
"b"
UA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"b"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DS
(input)
QS
(output)
Low
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
Qc0Qc1
BL = 4
DS
(input)
QS
(output)
CL = 4
CL = 4
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2
Note: lRC to the same bank must be satisfied.
Rev 1.4
2005-10-19
31/57
TC59LM818DMG-33,-40
MULTIPLE BANK READ TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL
Bank
"b"
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 6 cycles
IRC (Bank"b") = 6 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
Qb0Qb1
BL = 4
DS
(input)
QS
(output)
Low
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
Qa0Qa1
Qa0Qa1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qb0Qb1
Qb0Qb1
BL = 4
DS
(input)
QS
(output)
CL = 5
CL = 5
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2Qa3Qb0Qb1Qb2
Note: lRC to the same bank must be satisfied.
Rev 1.4
2005-10-19
32/57
TC59LM818DMG-33,-40
MULTIPLE BANK READ TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
RDA
LAL
RDA
LAL
UA
LA
UA
LA
Bank
"a"
DESL
Bank
"b"
RDA
LAL
RDA
LAL
RDA
LAL
RDA
LAL
RDA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 7 cycles
IRC (Bank"b") = 7 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
CL = 6
CL = 6
DQ
(output)
Hi-Z
Qa0Qa1
Qb0Qb1
Qa0Qa1
BL = 4
DS
(input)
QS
(output)
Low
CL = 6
CL = 6
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2
Qa0Qa1
Qa0Qa1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Qb0Qb1
BL = 4
DS
(input)
QS
(output)
CL = 6
CL = 6
DQ
(output)
Hi-Z
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3
Qa0Qa1Qa2
Rev 1.4
2005-10-19
33/57
TC59LM818DMG-33,-40
MULTIPLE BANK WRITE TIMING (CL = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
LA
Bank
"a"
DESL WRA
UA
Bank
"b"
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 3
WL = 3
DQ
(input)
Da0 Da1
Db0Db1
Da0Da1
Db0Db1
Dc0 Dc1
Dd0Dd1
BL = 4
DS
(input)
QS
(output)
Low
WL = 3
WL = 3
DQ
(input)
Da0 Da1 Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0Dd1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 3
WL = 3
DQ
(input)
Da0 Da1
Db0Db1
Da0Da1
Db0Db1
Dc0 Dc1
Dd0Dd1
BL = 4
DS
(input)
QS
(output)
WL = 3
WL = 3
DQ
(input)
Da0 Da1 Da2Da3Db0Db1Db2Db3
Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2 Dc3 Dd0Dd1
Note: lRC to the same bank must be satisfied.
Rev 1.4
2005-10-19
34/57
TC59LM818DMG-33,-40
MULTIPLE BANK WRITE TIMING (CL = 5)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
LA
Bank
"a"
DESL
Bank
"b"
IRC (Bank"a") = 6 cycles
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
UA
LA
UA
LA
UA
LA
UA
LA
UA
LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"b") = 6 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 4
WL = 4
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0 Db1
Dc0Dc1
BL = 4
DS
(input)
QS
(output)
Low
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0 Dc1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1
Db0Db1
Da0Da1
Db0 Db1
Dc0Dc1
BL = 4
DS
(input)
QS
(output)
WL = 4
WL = 4
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0 Dc1
Note: lRC to the same bank must be satisfied.
Rev 1.4
2005-10-19
35/57
TC59LM818DMG-33,-40
MULTIPLE BANK WRITE TIMING (CL = 6)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
CLK
Command
Address
Bank Add.
IRBD = 2 cycles
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
WRA
LAL
WRA
LAL
UA
LA
UA
Bank
"a"
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LAL
WRA
LA
UA
LA
UA
LA
UA
LA
UA
LA
UA
Bank
"b"
IRC (Bank"a") = 7 cycles
Bank
"a"
DESL
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"b") = 7 cycles
Unidirectional DS/QS mode
BL = 2
DS
(input)
QS
(output)
Low
WL = 5
WL = 5
DQ
(input)
Da0Da1
Db0Db1
Da0 Da1
Db0Db1
BL = 4
DS
(input)
QS
(output)
Low
WL = 5
WL = 5
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0 Da1 Da2Da3Db0Db1
Da0Da1
Da0 Da1
Unidirectional DS/Free Running QS mode
BL = 2
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
(input)
Db0Db1
Db0Db1
BL = 4
DS
(input)
QS
(output)
WL = 5
WL = 5
DQ
(input)
Da0Da1Da2Da3Db0Db1Db2Db3
Da0 Da1 Da2Da3Db0Db1
Note: lRC to the same bank must be satisfied.
Rev 1.4
2005-10-19
36/57
TC59LM818DMG-33,-40
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0
1
2
3
4
5
6
7
8
LAL
RDA
LAL
9
10
11
12
13
LAL
RDA
LAL
LA
UA
LA
14
15
CLK
CLK
Command
IRBD = 2 cycles
WRA
LAL
RDA
IWRD = 1 cycle
Address
Bank Add.
UA
LA
UA
Bank
"a"
LAL
DESL WRA
IRWD = 2 cycles IWRD = 1 cycle
LA
UA
Bank
"b"
LA
Bank
"c"
UA
DESL WRA
DESL WRA
IRWD = 2 cycles
LA
UA
Bank
"d"
Bank
"a"
UA
Bank
"b"
Bank
"c"
IRC (Bank"a")
IRC (Bank"b")
Unidirectional DS/QS mode
CL = 4
DS
(input)
QS
(output)
Low
CL = 4
WL = 3
DQ
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 5
DS
(input)
QS
(output)
Low
CL = 5
WL = 4
DQ
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 6
DS
(input)
QS
(output)
Low
CL = 6
WL = 5
DQ
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Unidirectional DS/Free Running QS mode
CL = 4
DS
(input)
QS
(output)
WL = 3
DQ
Hi-Z
CL = 4
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 5
DS
(input)
QS
(output)
WL = 4
DQ
Hi-Z
CL = 5
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Da0 Da1
CL = 6
DS
(input)
QS
(output)
WL = 5
DQ
CL = 6
Hi-Z
Da0 Da1
Qb0 Qb1
Dc0 Dc1
Qd0 Qd1
Note: lRC to the same bank must be satisfied.
Rev 1.4
2005-10-19
37/57
TC59LM818DMG-33,-40
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0
1
2
3
4
5
6
7
8
9
WRA
LAL
RDA
LAL
10
11
12
13
14
15
WRA
LAL
RDA
LAL
CLK
CLK
Command
IRBD = 2 cycles
WRA
LAL
RDA
IWRD = 1 cycle
Address
Bank Add.
UA
LA
UA
Bank
"a"
DESL
LAL
IRWD = 3 cycles
LA
Bank
"b"
IWRD = 1 cycle
UA
LA
Bank
"c"
IRC (Bank"a")
UA
DESL
IRWD = 3 cycles
IWRD = 1 cycle
LA
UA
Bank
"d"
Bank
"a"
LA
UA
LA
Bank
"b"
IRC (Bank"b")
Unidirectional DS/QS mode
CL = 4
DS
(input)
QS
(output)
Low
WL = 3
DQ
Hi-Z
CL = 4
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 5
DS
(input)
QS
(output)
Low
CL = 5
WL = 4
DQ
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 6
DS
(input)
QS
(output)
Low
CL = 6
WL = 5
DQ
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1
Unidirectional DS/Free Running QS mode
CL = 4
DS
(input)
QS
(output)
WL = 3
DQ
Hi-Z
CL = 4
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 5
DS
(input)
QS
(output)
WL = 4
DQ
Hi-Z
CL = 5
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1 Qd2 Qd3
CL = 6
DS
(input)
QS
(output)
WL = 5
DQ
Hi-Z
Note: lRC to the same bank must be satisfied.
CL = 6
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2 Dc3
Qd0 Qd1
Rev 1.4
2005-10-19
38/57
TC59LM818DMG-33,-40
WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 4)
0
1
2
3
4
5
6
WRA
LAL
UA
LA=#1
VW=1
7
8
9
10
11
12
13
14
15
CLK
CLK
BL = 2, SEQUENTIAL MODE
Command
Address
WRA
LAL
UA
LA=#3
VW=All
DESL
VW0 = Low
VW1 = don't care
Bank Add.
Bank
"a"
DESL
VW0 = High
VW1 = don't care
Bank
"a"
DS
(input)
DQ
(input)
Lower Address
D0 D1
D0
#3 #2
#1 (#0)
Last one data is masked.
BL = 4, SEQUENTIAL MODE
Command
Address
WRA
LAL
UA
LA=#3
VW=All
DESL
WRA
LAL
UA
LA=#1
VW=1
VW0 = High
VW1 = Low
Bank Add.
Bank
"a"
DESL
WRA
LAL
UA
LA=#2
VW=2
VW0 = High
VW1 = High
DESL
VW0 = Low
VW1 = High
Bank
"a"
Bank
"a"
DS
(input)
DQ
(input)
Lower Address
D0 D1 D2 D3
D0
D0 D1
#3 #0 #1 #2
#1(#2)(#3)(#0)
#2 #3 (#0)(#1)
Last three data are masked.
Last two data are masked.
Note: DS input must be continued till end of burst count even if some of laster data is masked.
Rev 1.4
2005-10-19
39/57
TC59LM818DMG-33,-40
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
IPDA
Command
Address
RDA
LAL
UA
LA
DESL
DESL
RDA
or
WRA
UA
tIS
IPD = 2 cycle
tIH
PD
tQPDH
tPDEX
lRC(min) , tREFI(max)
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
CL = 4
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Hi-Z
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
CL = 4
DQ
(output)
Hi-Z
Q0 Q1 Q2 Q3
Power Down Entry
Hi-Z
Power Down Exit
Note: PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
Rev 1.4
2005-10-19
40/57
TC59LM818DMG-33,-40
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
n-2
n-1
n
n+1
n+2
CLK
CLK
IPDA
Command
Address
RDA
LAL
UA
LA
DESL
DESL
RDA
or
WRA
UA
tIS
IPD = 2 cycle
tIH
PD
tQPDH
Unidirectional DS/QS mode
tPDEX
lRC(min) , tREFI(max)
DS
(input)
QS
(output)
Low
WL = 3
DQ
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
WL = 3
DQ
(input)
D0 D1 D2 D3
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" and a stable clock signal must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
Rev 1.4
2005-10-19
41/57
TC59LM818DMG-33,-40
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="0"
BA1="0"
BA
CLK
CLK
IRSC = 7 cycles
RDA
LAL
A14~A0
UA
LA
BA0, BA1
BA
Command
DESL
RDA
MRS
DESL
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
DQ
(output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
(output)
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
Rev 1.4
2005-10-19
42/57
TC59LM818DMG-33,-40
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
0
1
2
3
4
5
6
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="0"
BA1="0"
BA
7
8
9
10
11
12
13
CLK
CLK
IRSC = 7 cycles
Command
WRA
LAL
A14~A0
UA
LA
BA0, BA1
BA
DESL
RDA
MRS
DESL
WL+BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
DQ
(input)
Low
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
(input)
D0 D1 D2 D3
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
Rev 1.4
2005-10-19
43/57
TC59LM818DMG-33,-40
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="1"
BA1="0"
BA
CLK
CLK
IRSC = 7 cycles
RDA
LAL
A14~A0
UA
LA
BA0, BA1
BA
Command
DESL
RDA
MRS
DESL
CL + BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
DQ
(output)
Q0 Q1
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
(output)
Q0 Q1
Note:
Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
When DQ strobe mode is changed by EMRS, QS output is invalid for lRSC period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Rev 1.4
2005-10-19
44/57
TC59LM818DMG-33,-40
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
0
1
2
3
4
5
6
14
15
RDA
or
WRA
LAL
Valid
(opcode)
UA
LA
BA0="1"
BA1="0"
BA
7
8
9
10
11
12
13
CLK
CLK
IRSC = 7 cycles
WRA
LAL
A14~A0
UA
LA
BA0, BA1
BA
Command
DESL
RDA
MRS
DESL
WL+BL/2
Unidirectional DS/QS mode
DS
(input)
QS
(output)
Low
DQ
(input)
D0 D1 D2 D3
Unidirectional DS/Free Running QS mode
DS
(input)
QS
(output)
DQ
(input)
D0 D1 D2 D3
Note:
When DQ strobe mode is changed by EMRS, QS output is invalid for lRSC period.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
Rev 1.4
2005-10-19
45/57
TC59LM818DMG-33,-40
AUTO-REFRESH TIMING (CL = 4, BL = 4)
Unidirectional DS/QS mode
0
1
2
3
4
5
6
7
n−1
n
n+1
n+2
RDA
or
WRA
LAL or
MRS or
REF
RDA
or
WRA
LAL or
MRS or
REF
CLK
CLK
IRC = 5 cycles
Command
RDA
LAL
Bank, Address
Bank,
UA
LA
IRCD = 1 cycle
QS
(output)
IREFC = 19 cycles
DESL
WRA
IRAS = 4 cycles
REF
DESL
IRCD = 1 cycle
Low
Low
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Unidirectional DS/Free Running QS mode
CLK
CLK
IRC = 5 cycles
Command
RDA
LAL
Bank, Address
Bank,
UA
LA
IREFC = 19 cycles
DESL
IRCD = 1 cycle
WRA
IRAS = 4 cycles
REF
DESL
IRCD = 1 cycle
QS
(output)
CL = 4
DQ
(output)
Hi-Z
Hi-Z
Q0 Q1 Q2 Q3
Note: In case of CL = 4, IREFC must be meet 19 clock cycles.
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh
command specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
t1
t2
t3
t7
t8
CLK
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
tREFI =
Total time of 8 Refresh cycle
8
=
t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8
8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area
than Read / Write operation.
Rev 1.4
2005-10-19
46/57
TC59LM818DMG-33,-40
SELF-REFRESH ENTRY TIMING
Unidirectional DS/QS mode
0
1
2
3
4
m−1
5
m+1
m
CLK
CLK
Command
IRCD = 1 cycle
WRA
IREFC
REF
DESL
tFPDL (min) tFPDL (max)
PD
Auto Refresh
Self Refresh Entry
IPDV *2
tQPDH
ICKD
QS
(output)
DQ
(output)
Hi-Z
Low
Hi-Z
Qx
Notes: 1.
is don’t care.
2.
PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self
Refresh mode.When PD is brought to "Low" after lPDV, TC59LM818DMG perform Auto Refresh
and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM818DMG
will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be
specified which mode TC59LM818DMG operates.
3. It is desirable that clock input is continued at least lCKD from REF command even though PD is
brought to “Low” for Self-Refresh Entry.
4. In case of Self-Refresh entry after Write Operation, from the LAL command following WRA to the
REF command delay time is Write latency(WL)+2 clock cycles minimum.
SELF-REFRESH EXIT TIMING
Unidirectional DS/QS mode
0
1
2
m−1
m+1
m
m+2
n−1
n
n+1
p−1
p
CLK
CLK
*2
IREFC
*3
DESL
Command
IREFC
WRA
*4
REF
*4
Command (1st)*5
Command (2nd)*5
DESL
IRCD = 1 cycle
RDA
*6
LAL
*6
IRCD = 1 cycle
PD
tPDEX
ILOCK
QS
(output)
Hi-Z
DQ
(output)
Hi-Z
Low
Self-Refresh Exit
Notes: 1.
is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during IREFC after PD is brought to “High”.
4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
5. Any command (except Read command) can be issued after IREFC.
6. Read command (RDA + LAL) can be issued after ILOCK.
Rev 1.4
2005-10-19
47/57
TC59LM818DMG-33,-40
SELF-REFRESH ENTRY TIMING
Unidirectional DS/Free Running QS mode
0
1
2
3
4
m−1
5
m+1
m
CLK
CLK
Command
IRCD = 1 cycle
WRA
IREFC
REF
DESL
tFPDL (min) tFPDL (max)
PD
Auto Refresh
Self Refresh Entry
IPDV *2
ICKD
tQPDH
QS
(output)
DQ
(output)
Hi-Z
Hi-Z
Qx
Notes: 1.
is don’t care.
2.
PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self
Refresh mode. When PD is brought to "Low" after lPDV, TC59LM818DMG perform Auto Refresh
and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM818DMG
will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be
specified which mode TC59LM818DMG operates.
3. It is desirable that clock input is continued at least lCKD from REF command even though PD is
brought to “Low” for Self-Refresh Entry.
4. In case of Self-Refresh entry after Write Operation, from the LAL command following WRA to the
REF command delay time is Write latency(WL)+2 clock cycles minimum.
SELF-REFRESH EXIT TIMING
Unidirectional DS/Free Running QS mode
0
1
2
m−1
m+1
m
m+2
n−1
n
n+1
p−1
p
CLK
CLK
*2
IREFC
*3
DESL
Command
IREFC
WRA
*4
REF
*4
Command (1st)*5
Command (2nd)*5
DESL
IRCD = 1 cycle
RDA
*6
LAL
*6
IRCD = 1 cycle
PD
tPDEX
QS
(output)
DQ
(output)
ILOCK
Hi-Z
Self-Refresh Exit
Notes: 1.
is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during IREFC after PD is brought to “High”.
4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
5. Any command (except Read command) can be issued after IREFC.
6. Read command (RDA + LAL) can be issued after ILOCK.
7. QS output is invalid until DLL lock from Self-Refresh exit.
Rev 1.4
2005-10-19
48/57
TC59LM818DMG-33,-40
FUNCTIONAL DESCRIPTION
TM
Network FCRAM
The FCRAMTM is an acronym of Fast Cycle Random Access Memory.
The Network FCRAMTM is competent to perform fast random core access, low latency and high-speed data
transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and CLK . The
timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: CS & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected
the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
BA0
BA1
Bank #0
0
0
Bank #1
1
0
Bank #2
0
1
Bank #3
1
1
ADDRESS INPUTS: A0~A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
I/O Organization
UPPER ADDRESS
LOWER ADDRESS
18 bits
A0~A14
A0~A6
Rev 1.4
2005-10-19
49/57
TC59LM818DMG-33,-40
DATA INPUT/OUTPUT: DQ0~DQ17
The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal. The output
data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal.
DATA STROBE: DS, QS
Method of data strobe is chosen by Extended mode register.
(1) Unidirectional DS / QS mode
DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation.
Both edges of QS are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and
NOP cycle, QS assert always “Low” level. QS is Hi-Z in Self-Refresh mode.
(2) Unidirectional DS / Free running QS mode
DS is input signal and QS is output signal. Both edge of DS are used to sample all DQs at Write operation.
Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal
except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits.
VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
Rev 1.4
2005-10-19
50/57
TC59LM818DMG-33,-40
COMMAND FUNCTIONS and OPERATIONS
TC59LM818DMG are introduced the two consecutive command input method. Therefore, except for Power Down
mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the
next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing
of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after lRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS
input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input
after CAS latency-1 from the issuing of the LAL command. The DS has to be provided for a burst length. The
CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes
back automatically to the idle state after lRC. Write Burst Length is controlled by VW0 and VW1 inputs with
LAL command. See VW truth table.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM818DMG are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF
command having gone into the next clock of the WRA command instead of the LAL command. The minimum
period between the Auto-Refresh command and the next command is specified by lREFC. However, about a
synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh,
Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh
or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands has to be more
than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within 3.2 µs (8 ×
400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD = “L”)
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM818DMG become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL from the
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition,
it is desirable that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held
“Low”. During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks
specified by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one
Auto-Refresh command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh
exit.
Power Down Mode ( PD = “L”)
When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM818DMG become Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation
lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be
issued for lPDA cycle after PD goes high. The Power Down exit function is asynchronous operation.
Rev 1.4
2005-10-19
51/57
TC59LM818DMG-33,-40
Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM818DMG have
two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is
chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has three function fields.
The three fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Data Strobe Select
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode
Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or
Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued
before proper operation.
•
Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1
BA0
Mode Register Set
0
0
Regular MRS
0
1
Extended MRS
1
×
Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst
Length to be 2 or 4 words.
A2
A1
A0
BURST LENGTH
0
0
0
Reserved
0
0
1
2 words
0
1
0
4 words
0
1
1
Reserved
1
×
×
Reserved
(R-2) Burst Type field (A3)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”,
Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types
support burst length of 2 and 4 words.
A3
BURST TYPE
0
Sequential
1
Interleave
Rev 1.4
2005-10-19
52/57
TC59LM818DMG-33,-40
•
Addressing sequence of Sequential mode (A3)
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
CAS Latency = 4 (Free Running QS mode)
CLK
CLK
Command
RDA
LAL
QS
Data Data Data Data
0
1
2
3
DQ
Addressing sequence for Sequential mode
•
DATA
ACCESS ADDRESS
Data 0
n
Data 1
n+1
Data 2
n+2
Data 3
n+3
BURST LENGTH
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address
bits in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA
ACCESS ADDRESS
BURST LENGTH
Data 0
ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1
ּּּA8 A7 A6 A5 A4 A3 A2 A1
A0
Data 2
ּּּA8 A7 A6 A5 A4 A3 A2
A1
A0
Data 3
ּּּA8 A7 A6 A5 A4 A3 A2
A1
A0
2 words
4 words
(R-3) CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum value of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6
A5
A4
CAS LATENCY
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
Reserved
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
(R-4) Test Mode field (A7)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14)
These bits are reserved for future operations. They must be set to “0” for normal operation.
Rev 1.4
2005-10-19
53/57
TC59LM818DMG-33,-40
Extended Mode Register fields
(E-1) DLL Switch field (A0)
This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must be set to “0”
for normal operation.
(E-2) Output Driver Impedance Control field (A1 to A4)
This field is used to choose Output Driver Strength. Three types of Driver Strength are supported.
QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3
specified the QS Driver Strength.
QS
DQ
OUTPUT DRIVER IMPEDANCE CONTROL
A4
A3
A2
A1
0
0
0
0
Normal Output Driver
0
1
0
1
Strong Output Driver
1
0
1
0
Weak Output Driver
1
1
1
1
Reserved
(E-3) Strobe Select (A6 / A5)
Two types of data strobe are supported. This field is used to choose the type of data strobe.
(1) Unidirectional DS/QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data at Read
operation.
(2) Unidirectional DS/Free running QS mode
Data strobe is separated DS for write strobe and QS for read strobe.
DS is used to sample write data at write operation. QS is aligned with read data and always
clocking.
A6
A5
STROBE SELECT
0
0
Reserved
0
1
Reserved
1
0
Unidirectional DS/QS mode
1
1
Unidirectional DS/Free running QS mode
(E-4) Reserved field (A7 to A14)
These bits are reserved for future operations and must be set to “0” for normal operation.
Rev 1.4
2005-10-19
54/57
TC59LM818DMG-33,-40
PACKAGE DIMENSIONS
P-BGA60-0917-1.00AZ
0.2 S A
16.5
0.2 S B
0
12.518 -0.15
1
9.0
0
6.218 -0.15
4
0.15
1.2MAX
0.2 S
S
0.4 0.05
0.15MIN
0.1 S
0.5 0.05
S AB
0.08
1.25
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
INDEX
A
1
2.0
1
2
B
1.0
3
1.5
4
1.5
5
6
1
2.0
1.0
Weight: 0.15 g (typ.)
Rev 1.4
2005-10-19
55/57
TC59LM818DMG-33,-40
REVISION HISTORY
− Rev.1.1 (Jan. 17 ’2005)
Difference between lead product( P/N: TC59LM818DMB ) and this lead-free product in this datasheet is only
part number and notes for lead-free product on page 1.
− Rev.1.2 (Mar. 7 ’2005)
Corrected figure of lPDA based AC timing spec table ( page 11, 40, 41, 47, 48 ).
− Rev.1.3 (Sep. 26 ’2005)
IDD6( Self-Refresh current ) spec changed from 10mA to 15mA ( page 1 and 6 ).
− Rev.1.4 (Oct.19 ’2005)
“-30”( 333MHz clock/666Mbps ) version dropped.
Rev 1.4
2005-10-19
56/57
TC59LM818DMG-33,-40
RESTRICTIONS ON PRODUCT USE
030619EBA
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor
devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced
and sold, under any law and regulations.
Rev 1.4
2005-10-19
57/57