HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -6 -7 -7.5 -8 Units • Data Mask for Read / Write control (x4, x8) • Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh fCK 166 143 133 125 MHz • Power Down and Clock Suspend Mode tCK3 6 7 7.5 8 ns • 8192 refresh cycles / 64 ms (7,8 µs) tAC3 5 5.4 5.4 6 ns • tCK2 7.5 7.5 10 10 ns Random Column Address every CLK ( 1-N Rule) • Single 3.3V +/- 0.3V Power Supply tAC2 5.4 5.4 6 6 ns • LVTTL Interface versions • Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) • Chipsize Packages: 54 ball TFBGA (12 mm x 8 mm) • -6 parts for PC166 3-3-3 operation -7 parts for PC133 2-2-2 operation -7.5 parts for PC133 3-3-3 operation -8 parts for PC100 2-2-2 operation • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature • Four Banks controlled by BA0 & BA1 • Programmable CAS Latency: 2 & 3 • Programmable Wrap Sequence: Sequential or Interleave • Programmable Burst Length: 1, 2, 4, 8 and full page • Multiple Burst Read with Single Write Operation • Automatic Command and Controlled Precharge The HYB39S256400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4 banks x 16MBit x4, 4 banks x 8MBit x8 and 4 banks x 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm 256MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3V +/- 0.3V power supply. All 256Mbit components are available in TSOPII-54 and TFBGA-54 packages. INFINEON Technologies 1 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Ordering Information Type Speed Grade Package Description HYB 39S256400DT-6 PC166-333-520 P-TSOP-54-2 (400mil) 166MHz 4B x 16M x 4 SDRAM HYB 39S256400DT-7 PC133-222-520 P-TSOP-54-2 (400mil) 143MHz 4B x 16M x 4 SDRAM HYB 39S256400DT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 16M x 4 SDRAM HYB 39S256400DT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 16M x 4 SDRAM HYB 39S256800DT-6 PC166-333-520 P-TSOP-54-2 (400mil) 166MHz 4B x 8M x 8 SDRAM HYB 39S256800DT-7 PC133-222-520 P-TSOP-54-2 (400mil) 143MHz 4B x 8M x 8 SDRAM HYB 39S256800DT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 8M x 8 SDRAM HYB 39S256800DT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 8M x 8 SDRAM HYB 39S256160DT-6 PC166-333-520 P-TSOP-54-2 (400mil) 166MHz 4B x 4M x 16 SDRAM HYB 39S256160DT-7 PC133-222-520 P-TSOP-54-2 (400mil) 143MHz 4B x 4M x 16 SDRAM HYB 39S256160DT-7.5 PC133-333-520 P-TSOP-54-2 (400mil) 133MHz 4B x 4M x 16 SDRAM HYB 39S256160DT-8 PC100-222-620 P-TSOP-54-2 (400mil) 125MHz 4B x 4M x 16 SDRAM HYB39S256800DTL-x P-TSOP-54-2 (400mil) 4B x 8M x 8 SDRAM Low Power Versions (on request) HYB39S256160DTL-x P-TSOP-54-2 (400mil) 4B x 4M x 16 SDRAM Low Power Versions (on request) HYB39S256xx0DC(L)-x P-TFBGA-54 (on request) Pin Description: CLK Clock Input DQx Data Input /Output CKE Clock Enable DQM, LDQM, UDQM Data Mask Power (+3.3V) CS Chip Select VDD RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQ’s (+ 3.3V) WE Write Enable VSSQ Ground for DQ’s A0-A12 Address Inputs NC not connected BA0, BA1 Bank Select INFINEON Technologies 2 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Pinouts (TSOP-54) 16 M x 16 32 M x 8 64 M x 4 VDD VDD VDD DQ0 DQ0 N.C. VDDQ VDDQ VDDQ DQ1 DQ2 N.C. DQ1 N.C. DQ0 VSSQ VSSQ VSSQ DQ3 DQ4 N.C. DQ2 N.C. N.C. VDDQ VDDQ VDDQ DQ5 DQ6 N.C. DQ3 N.C. DQ1 VSSQ VSSQ VSSQ DQ7 N.C. N.C. VDD VDD VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 N.C. WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 N.C. WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS VSS VSS N.C. DQ7 DQ15 VSSQ VSSQ VSSQ N.C. DQ3 N.C. DQ6 DQ14 DQ13 VDDQ VDDQ VDDQ N.C. N.C. N.C. DQ5 DQ12 DQ11 VSSQ VSSQ VSSQ N.C. DQ2 N.C. DQ4 DQ10 DQ9 VDDQ VDDQ VDDQ N.C. N.C. DQ8 VSS VSS VSS N.C. DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 N.C. DQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 N.C. UDQM CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS VSS VSS TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch) SPP04126 INFINEON Technologies 3 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Pinouts (TFBGA-54) Pin Configuration for x16 devices: 1 2 3 VSS DQ15 VSSQ A 7 8 9 VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 NC VSS E VDD LDQM DQ7 UDQM CLK CKE F CAS RAS WE A12 A11 A9 G BA0 BA1 CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD 7 8 9 A VDDQ DQ0 VDD Pin Configuration for x8 devices: 1 2 3 VSS DQ7 VSSQ NC DQ6 VDDQ B VSSQ DQ1 NC NC DQ5 VSSQ C VDDQ DQ2 NC NC DQ4 VDDQ D VSSQ DQ3 NC NC NC VSS E VDD NC NC DQM CLK CKE F CAS RAS WE A12 A11 A9 G BA0 BA1 CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD 7 8 9 A VDDQ NC VDD Pin Configuration for x4 devices: 1 2 3 VSS NC VSSQ NC DQ3 VDDQ B VSSQ DQ0 NC NC NC VSSQ C VDDQ NC NC NC DQ2 VDDQ D VSSQ DQ1 NC NC NC VSS E VDD NC NC DQM CLK CKE F CAS RAS WE A12 A11 A9 G BA0 BA1 CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD INFINEON Technologies 4 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Pinout for x4, x8 & x16 organised 256M-DRAMs C o lu m n A d d re s s C o u n te r C o lu m n A d d re s s B u ffe r R o w A d d re s s B u ffe r Row D e co de r R ow Decoder Row D e co de r R ow D eco d e r M em ory A rray M em ory A rra y M em ory A rra y M em ory A rra y 8 1 96 x 20 4 8 x 4 B it In p u t B u ffe r B a nk 1 81 9 2 x 2 0 48 x 4 B it Bank 2 8192 x 20 4 8 x 4 B it O u tp u t B u ffe r R e fre s h C o u n te r Column Decoder Sense amplifier & I(O) Bus Bank 0 Column Decoder Sense amplifier & I(O) Bus A0 - A12, BA0, B A1 Column Decoder Sense amplifier & I(O) Bus R o w A d d re s s e s A 0 - A 9 , A 1 1 , A P, B A0, BA 1 Column Decoder Sense amplifier & I(O) Bus C o lu m n A d d re s s e s B a nk 3 8 19 2 x 2048 x 4 B it C o n tro l L o g ic & T im in g G e n e ra to r CLK CKE CS RAS CAS WE DQM DQ0 - DQ3 S P B 0 4 1 2 7 _2 Block Diagram for 64M x 4 SDRAM ( 13 / 11 / 2 addressing) INFINEON Technologies 5 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Column Address Counter Column Address Buffer Row Address Buffer Row Decoder Row Decoder Row Decoder Row Decoder Memory Array Memory Array Memory Array Memory Array 8192 x 1024 x 8 Bit Input Buffer Bank 1 8192 x 1024 x 8 Bit Bank 2 8192 x 1024 x 8 Bit Output Buffer Refresh Counter Column Decoder Sense amplifier & I(O) Bus Bank 0 Column Decoder Sense amplifier & I(O) Bus A0 - A12, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Row Addresses A0 - A9, AP, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Column Addresses Bank 3 8192 x 1024 x 8 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQM DQ0 - DQ7 SPB04128 Block Diagram for 32M x 8 SDRAM ( 13 / 10 / 2 addressing) INFINEON Technologies 6 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM A0 - A12, BA0, BA1 Column Address Counter Column Address Buffer Row Address Buffer Row Decoder Row Decoder Bank 0 8192 x 512 x 16 Bit Input Buffer Memory Array Bank 1 8192 x 512 x 16 Bit Memory Array Bank 2 8192 x 512 x 16 Bit Output Buffer Row Decoder Column Decoder Sense amplifier & I(O) Bus Memory Array Refresh Counter Row Decoder Column Decoder Sense amplifier & I(O) Bus Column Decoder Sense amplifier & I(O) Bus Row Addresses A0 - A8, AP, BA0, BA1 Column Decoder Sense amplifier & I(O) Bus Column Addresses Memory Array Bank 3 8192 x 512 x 16 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQMU DQML DQ0 - DQ15 SPB04129 Block Diagram for 16M x16 SDRAM ( 13 / 9 / 2 addressing) INFINEON Technologies 7 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiating either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A12 Input Level – During a Bank Activate command cycle, A0-A12 define the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An define the column address (CA0-CAn) when sampled at the rising clock edge.CAn depends upon the SDRAM organization: 64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits) 32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits) 16M x16 SDRAM CAn = CA8 (Page Length = 512 bits) In addition to the column address, A10(= AP) is used to invoke the autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input DQx Level – Bank Select Inputs. Bank address inputs selects which of the four banks a command applies to. Input Level Output – Data Input/Output pins operate in the same manner as on conventional DRAMs. INFINEON Technologies 8 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Pin Type Signal Polarity Function DQM LDQM UDQM Input Pulse VDD VSS VDDQ VSSQ Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input is present in x4 and x8 SDRAMs, LDQM and UDQM controls the lower and upper bytes in x16 SDRAMs. Supply – – Power and ground for the input buffers and the core logic. Supply – – Isolated power supply and ground for the output buffers to provide improved noise immunity. INFINEON Technologies 9 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device State CKE n-1 CKE n DQM BA0 BA1 AP= A10 Addr . CS RAS CAS WE Bank Active Idle3 H X X V V V L L H H Bank Precharge Any H X X V L X L L H L Precharge All Any H X X X H X L L H L Write Active3 H X X V L V L H L L Write with Autoprecharge Active3 H X X V H V L H L L Read Active3 H X X V L V L H L H Read with Autoprecharge Active3 H X X V H V L H L H Mode Register Set Idle H X X V V V L L L L No Operation Any H X X X X X L H H H Burst Stop Active H X X X X X L H H L Device Deselect Any H X X X X X H X X X Auto Refresh Idle H H X X X X L L L H Self Refresh Entry Idle H L X X X X Self Refresh Exit Idle (Self Refr.) L H X X X X Clock Suspend Entry Active H L X X X X Power Down Entry (Precharge or active standby) Idle H L X X X X Active4 Clock Suspend Exit Active L H X X X X Power Down Exit Any (Power Down) L H X X X X Data Write/Output Enable L L L H H X X X L H H X X X X X H X X X L H H H X X X X H X X X L H H L Active H X L X X X X X X X Data Write/Output Disable Active H X H X X X X X X X Notes 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in clock suspend mode. INFINEON Technologies 10 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Mode Register Set Table BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Operation Mode CAS Latency BT Burst Length Mode Register (Mx) Operation Mode Burst Type M9 0 Mode burst read / burst write M3 Type 0 Sequential 1 burst read / single write 1 Interleave Burst Length CAS Latency M6 M5 M4 Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 1 0 1 1 1 0 1 1 1 INFINEON Technologies Reserved 11 M2 M1 M0 0 0 0 Length Sequential Interleave 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 1 0 1 1 1 0 1 1 1 Reserved Reserved Full Page 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into four fields. First, a Burst Length Field which sets the length of the burst, Second, an Addressing Selection bit which programs the column access sequence in a burst cycle (interleaved or sequential). Third, a CAS Latency Field to set the access time at clock cycle. Fourth, an Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. After the initial power up, the mode set operation must be done before any activate command. Any content of the mode register can be altered by reexecuting the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 166 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4 and 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organization and column addressing. Full page burst operation does not self INFINEON Technologies 12 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM terminate once the burst length has been reached. In other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAMs, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be performed between different pages. Burst Length and Sequence: Burst Starting Address Length (A2 A1 A0) 2 xx0 xx1 4 x00 x01 x10 x11 8 000 001 010 011 100 101 110 111 Full Page nnn Sequential Burst Addressing (decimal) Interleave Burst Addressing (decimal) 0, 1 1, 0 0, 1, 1, 2, 2, 3, 3, 0, 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 0, 1 1, 0 0, 1, 2, 1, 0, 3, 2, 3, 0, 3, 2, 1, 2, 3 3, 0 0, 1 1, 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 Cn, Cn+1, Cn+2 .... 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 3 2 1 0 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 not supported Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. INFINEON Technologies 13 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to “high“ at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking CKE “high“. One clock delay is required for Power Down mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with AutoPrecharge function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR (“write recovery time”) after the last data in. A burst operation with Auto-Precharge may only be interrupted by a burst start to another bank. It must not be interrupted by a precharge or a burst stop command. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay twr (“write recovery time”) of 2 clocks minimum from the last data out to apply the precharge command. INFINEON Technologies 14 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Bank Selection by Address Bits A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 x x all Banks Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Capacitance TA = 0 to 70 °C; VDD,VDDQ = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Values min. max. Unit Input capacitance (CLK) CI1 2.5 3.5 pF Input capacitance CI2 2.5 3.8 pF CIO 4.0 6.0 pF (A0-A12, BA0,BA1,RAS, CAS, WE, CS, CKE, DQM) Input / Output capacitance (DQ) Note: Capacitance values are shown for TSOP-54 packages. Capacitance values for TFBGA packages are lower by 0.5 pF. INFINEON Technologies 15 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Absolute Maximum Ratings Parameter Symbol Limit Values min. Unit max. Input / Output voltage relative to VSS VIN, VOUT – 1.0 4.6 V Power supply voltage VDD,VDDQ – 1.0 4.6 V Operating Temperature TA 0 +70 oC Storage temperature range TSTG -55 +150 oC Power dissipation per SDRAM component PD – 1 W Data out current (short circuit) IOS – 50 mA Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability Recommended Operation Conditions and DC Eletrical Characteristics TA = 0 to 70 oC; Parameter Symbol Supply Voltage VDD,VDDQ Input high voltage Input low voltage Limit Values Unit Notes min. typ. max. 3.0 3.3 3.6 VIH 2.0 3.0 V DDQ+0.3 V 1, 2 VIL – 0.3 0 0.8 V 1, 2 2.4 – – V 1 1 Output high voltage (IOUT = – 4.0 mA) VOH V 1 Output low voltage (IOUT = 4.0 mA) VOL – – 0.4 V Input leakage current, any input IIL –5 – 5 mA IOL –5 – 5 mA (0 V < VIN < VDD, all other inputs = 0 V) Output leakage current (DQs are disabled, 0 V < VOUT < VDDQ) Notes: 1. All voltages are referenced to VSS. 2. Vih may overshoot to VDDQ + 2.0 V for pulse width of < 4ns with 3.3V. Vil may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. INFINEON Technologies 16 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Operating Currents TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V Parameter & Test Condition Symb. -6 -7 -7.5 -8 tRC = t RC(min), Io = 0 mA IDD1 100 80 80 80 mA 3, 4 Precharge Standby Current in Power Down Mode CS =VIH (min.), CKE<=Vil(max) IDD2P 2 2 2 2 mA 3 Precharge Standby Current in Non-Power Down Mode CS = VIH (min.), CKE>=Vih(min) IDD2N 35 30 30 25 mA 3 No Operating Current CS = VIH(min), CKE>=VIH(min.) IDD3N 40 35 35 30 mA 3 active state ( max. 4 banks) CS = VIH(min), CKE<=VIL(max.) IDD3P 5 5 5 5 mA 3 IDD4 110 90 90 70 mA 3, 4 220 190 190 160 mA 3 3 3 3 mA Note max. Operating Current One bank active, Burst length = 1 Burst Operating Current Read command cycling Auto Refresh Current Auto Refresh command cycling Self Refresh Current (standard components) Self Refresh Mode, CKE=0.2V, tck=infinity Self Refresh Current (low power components) Self Refresh Mode, CKE=0.2V, tck=infinity tRFC= tRFC(min) IDD5 t RFC= 7.8 µs x4, x8 x16 IDD6 3 1.5 3 1.5 3 1.5 3 1.5 mA mA x8, x16 IDD6 0.85 0.85 0.85 0.85 mA 5 Notes: 3. These parameters depend on the cycle rate. All values are measured at 166 MHz for “-6”, at 133 MHz for “-7” and “-7.5” and at 100 MHz for “-8” components with the outputs open. Input signals are changed once during tck. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. 5. tRFC= tRFC(min) “burst refresh”, tRFC= 7.8 µs “distributed refresh”. INFINEON Technologies 17 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM AC Characteristics 1)2) TA = 0 to 70 oC; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Unit Limit Values -6 PC166333 min. -7 PC133222 max. min. -7.5 PC133333 max. min. -8 PC100222 max. min. max. Clock and Clock Enable Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK 6 7.5 – – 7 7.5 – – 7.5 10 – – 8 10 Clock Frequency CAS Latency = 3 CAS Latency = 2 tCK – – 166 133 – – 143 133 – – 133 100 – – Access Time from Clock CAS Latency = 3 CAS Latency = 2 tAC – – 5 5.4 – – 5.4 5.4 – – 5.4 6 – – 6 6 ns ns Clock High Pulse Width tCH 2 – 2.5 – 2.5 – 3 – ns Clock Low Pulse Width tCL 2 – 2.5 – 2.5 – 3 – ns Transition time tT 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns tIS 1.5 – 1.5 – 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 0.8 – 0.8 – 1 – ns 4 CKE Setup Time tCKS 1.5 – 1.5 – 1.5 – 2 – ns 4 CKE Hold Time tCKH 0.8 – 0.8 – 0.8 – 1 – ns 4 Mode Register Set-up to Active delay tRSC 2 – 2 – 2 – 2 – CLK Power Down Mode Entry Time tSB 0 6 0 7 0 7.5 0 8 ns Row to Column Delay Time tRCD 15 – 15 – 20 – 20 – ns 5 Row Precharge Time tRP 15 – 15 – 20 – 20 – ns 5 Row Active Time tRAS 36 100k 37 100k 45 100k 48 100k ns 5 Row Cycle Time tRC 60 – 60 – 67 – 70 – ns 5 – – ns ns 125 MHz 100 MHz 2, 3, 6 Setup and Hold Times Input Setup Time Common Parameters INFINEON Technologies 18 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Parameter Limit Values Symbol -6 PC166333 -7 PC133222 Unit -7.5 PC133333 -8 PC100222 min. max. min. max. min. max. min. Row Cycle Time during Auto Refresh tRFC 60 63 67 70 max. Activate(a) to Activate(b) Command period tRRD 12 – 14 – 15 – 16 – ns CAS(a) to CAS(b) Command period tCCD 1 – 1 – 1 – 1 – CLK Refresh Period (8192 cycles) tREF – 64 – 64 – 64 – 64 Self Refresh Exit Time tSREX 1 – 1 – 1 – 1 Data Out Hold Time tOH 2.5 – 3 – 3 – 3 – ns Data Out to Low Impedance Time ns 5 Refresh Cycle ms CLK Read Cycle tLZ 0 – 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 6 3 7 3 7 3 8 ns DQM Data Out Disable Latency tDQZ – 2 – 2 – 2 – 2 CLK tWR 12 – 14 – 15 – 15 – ns 2, 6 Write Cycle Last Data Input to Precharge 7 (Write without AutoPrecharge) Last Data Input to Activate CLK 8 (twr/tck) + (trp/tck) tDAL,min (Write with AutoPrecharge) DQM Write Mask Latency INFINEON Technologies tDQW 0 – 19 0 – 0 – 0 – CLK 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Notes 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests for LV-TTL versions have V IL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V. t CH 2.4 V 0.4 V 1 .4 V CLOCK tCL t IS tT t IH 1 .4 V IN P U T t AC tLZ tA C t OH O UTPUT 1.4 V I/O 50 pF tHZ IO.vsd Measurement conditions for tAC and tOH 3. If clock rising time is longer than 1 ns, a time ( tT /2 − 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing period (counted in fractions as a whole number) 6. Access time from clock tAC is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time tOH is 1.8 ns for PC133 components with no termination and 0 pF load. 7. It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write command without Auto-Precharge. One clock cycle between the last data-in and the precharge command is also supported, but restricted to cycle times tck greater or equal the specified twr value, where tck is equal to the actual system clock time 8. When a Write command with AutoPrecharge has been issued, a time of tdal(min) has be fullfilled before the next Activate Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tck is equal to the actual system clock time. INFINEON Technologies 20 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Package Outlines - TSOP 0.8 15˚±5˚ 26x 0.8 = 20.8 3) 0.35 +0.1 -0.05 0.1 54x 0.5 ±0.1 11.76 ±0.2 0.2 M 54x 28 6 max 54 10.16 ±0.13 2) 0.15 +0.06 -0.03 1±0.05 15˚±5˚ 0.1±0.05 Plastic Package P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 1 27 2.5 max 22.22 ±0.13 1) GPX09039 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side 2) INFINEON Technologies 21 2002-04-23 HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM Package Outlines- TFBGA TFBGA-54 package (12 mm x 8 mm, 54 balls) INFINEON Technologies 22 2002-04-23