FUJITSU MB81P643287

FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11402-2E
MEMORY
CMOS
8 x 256K x 32 BIT, FCRAMTM CORE
BASED DOUBLE DATA RATE SDRAM
MB81P643287-50/-60
CMOS 8-BANK x 262,144-WORD x 32 BIT, FCRAM Core Based
Synchronous Dynamic Random Access Memory
with Double Data Rate
■ DESCRIPTION
The Fujitsu MB81P643287 is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) with Fujitsu
advanced FCRAM (Fast Cycle Random Access Memory) Core Technology, containing 67,108,864 memory cells
accessible in an 32-bit format. The MB81P643287 features a fully synchronous operation referenced to clock
edge whereby all operations are synchronized at a clock input which enables high performance and simple user
interface coexistence. The MB81P643287 is designed to reduce the complexity of using a standard dynamic RAM
(DRAM) which requires many control signal timin.g constraints. The MB81P643287 uses Double Data Rate (DDR)
where data bandwidth is twice of fast speed compared with regular SDRAMs.
The MB81P643287 is ideally suited for Digital Visual Systems, High Performance Graphic Adapters, Hardware
Accelerators, Buffers, and other applications where large memory density and high effective bandwidth are
required and where a simple interface is needed.
The MB81P643287 adopts new I/O interface circuitry, SSTL_2 interface, which is capable of extremely fast data
transfer of quality under either terminated or point to point bus environment.
■ PRODUCT LINE
MB81P643287
Parameter
-50
-60
CL = 3
200 MHz Max.
167 MHz Max.
CL = 2
133 MHz Max.
111 MHz Max.
CL = 3
2.5 ns Min.
3.0 ns Min.
CL = 2
3.75 ns Min.
4.5 ns Min.
Random Address Cycle Time
30 ns Min.
36 ns Min.
DQS Access Time From Clock
0.1 × tCK + 0.2 ns Max.
0.1 × tCK + 0.2 ns Max.
460 mA Max.
405 mA Max.
Clock Frequency
Burst Mode Cycle Time
Operating Current
Power Down Current
Note: FCRAM is a trademark of Fujitsu Limited, Japan.
35 mA Max.
MB81P643287-50/-60
■ FEATURES
•
•
•
•
•
•
•
Double Data Rate
Bi-directional Data Strobe Signal
Eight bank operation
Burst read/write operation
Programmable burst length and CAS latency
Byte write control by DM0 to DM3
Standby Power Down Mode
•
•
•
•
4096 Auto-refresh cycles in 32 ms
SSTL_2 (class 2) for all signals
+2.5V Supply ± 0.2V tolerance
VDD:
VDDQ:
+2.5V Supply ± 0.2V tolerance
■ PACKAGE
86-pin plastic TSOP(II)
(FPT-86P-M01)
(Normal Bend)
2
MB81P643287-50/-60
■ PIN ASSIGNMENTS
86-pin TSOP (II)
(TOP VIEW)
(Normal Bend)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
DQS0
VDD
DM0
WE
CAS
RAS
CS
BA2
BA0
BA1
A10/AP
A0
A1
A2
DM2
VDD
DQS2
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
DQS1
VSS
DM1
VREF
CLK
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DM3
VSS
DQS3
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
(FPT-86P-M01)
3
MB81P643287-50/-60
■ DESCRIPTIONS
Pin Number
Symbol
1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81
VDD, VDDQ
Supply Voltage
6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86
VSS, VSSQ
Ground
2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39,
40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76,
77, 79, 80, 82, 83, 85
4
DQ0 to DQ31
Function
Data I/O
•
•
•
•
Byte 0: DQ0 to DQ7
Byte 1: DQ8 to DQ15
Byte 2: DQ16 to DQ23
Byte 3: DQ24 to DQ31
•
•
•
•
DQS0: for DQ0 to DQ7
DQS1: for DQ8 to DQ15
DQS2: for DQ16 to DQ23
DQS3: for DQ24 to DQ31
14, 30, 57, 73
DQS0 to DQS3
Data Strobe
16, 28, 59, 71
DM0 to DM3
Input Mask
17
WE
Write Enable
18
CAS
Column Address Strobe
19
RAS
Row Address Strobe
20
CS
21, 22, 23
BA2, BA1, BA0
24
AP
24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66
A0 to A10
Address Input
67
CKE
Power Down
68
CLK
Clock Input
69
CLK
Clock Input
70
VREF
Input Reference Voltage
Chip Select
Bank Select (Bank Address)
Auto Precharge Enable
• Row:
A0 to A10
• Column: A0 to A6
MB81P643287-50/-60
■ BLOCK DIAGRAM
Fig. 1 - MB81P643287 BLOCK DIAGRAM
CLK
CLK
CLOCK
BUFFER
To each block
CKE
Bank-7
Enable
Bank-1
Bank-0
RAS
CS
CONTROL
SIGNAL
LATCH
RAS
CAS
CAS
COMMAND
DECODER
WE
WE
DRAM
CORE
(2048 × 128 × 32)
AP
MODE
REGISTER
ROW
ADDRESS
11
A0 to A10
BA0, BA1,
BA2
ADDRESS
BUFFER/
REGISTER
COLUMN
ADDRESS
COUNTER
DM0 to
DM3
DQ0 to
DQ31
DQS0 to
DQS3
7
COLUMN
ADDRESS
I/O
I/O DATA
BUFFER/
REGISTER
&
DQS
GENERATOR
32
VDD
DLL
Clock Buffer
VREF
VSS/VSSQ
VDDQ, VSSQ
5
MB81P643287-50/-60
■ FUNCTION TRUTH TABLE (Note*1)
COMMAND TRUTH TABLE (Note *2, and *3)
Function
Notes Symbol CKE
CS
RAS
CAS
WE
BA2-0
A10/AP
A9-7
A6-0
Device Deselect
*4
DESL
H
H
X
X
X
X
X
X
X
No Operation
*4
NOP
H
L
H
H
H
X
X
X
X
Burst Stop
*5
BST
H
L
H
H
L
X
X
X
X
Read
*6
READ
H
L
H
L
H
V
L
X
V
Read with Auto-precharge
*6 READA
H
L
H
L
H
V
H
X
V
Write
*6
H
L
H
L
L
V
L
X
V
Write with Auto-precharge
*6 WRITA
H
L
H
L
L
V
H
X
V
Bank Active (RAS)
*7
ACTV
H
L
L
H
H
V
V
V
V
Precharge Single Bank
*8
PRE
H
L
L
H
L
V
L
X
X
Precharge All Banks
*8
PALL
H
L
L
H
L
V
H
X
X
Mode Register Set/
*8,9,10
Extended Mode Register Set
MRS/
EMRS
H
L
L
L
L
V
L
V
V
WRIT
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance.
*2. All commands are assumed to be valid state transitions.
*3. All inputs for command are latched on the rising edge of clock(CLK).
*4. NOP and DESL commands have the same effect on the part.
Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions.
*5. BST is effective after READ command is issued.
*6. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to “■ STATE DIAGRAM”.
*7. ACTV command should only be issued after corresponding bank has been page closed by PRE or
PALL command.
*8. Either PRE or PALL command and MRS or EMRS command are required after power up.
*9. MRS or EMRS command should only be issued after all banks have been page closed (PRE or PALL
command), and DQs are in Hi-Z. Refer to “■ STATE DIAGRAM”.
*10. Refer to“■ MODE REGISTER TABLE”.
6
MB81P643287-50/-60
DM TRUTH TABLE (Effective during Write mode)
Function
CKE
Command
(n - 1)
(n)
DM0
DM1
DM2
DM3
Data Mask for DQ0 to DQ7
MASK0
H
X
H
X
X
X
Data Mask for DQ8 to DQ15
MASK1
H
X
X
H
X
X
Data Mask for DQ16 to DQ23
MASK2
H
X
X
X
H
X
Data Mask for DQ24 to DQ31
MASK3
H
X
X
X
X
H
CKE TRUTH TABLE
Current
State
CKE
Function
Notes
Command
(n-1) (n)
CS RAS CAS WE
AP
A0
BA0
to
BA2
A10
DQ0
to
DQ31
to
Idle
Auto-refresh
*11
REF
H
H
L
L
L
H
X
X
X
—
Idle
Self-refresh Entry
*11
*12
SELF
H
L
L
L
L
H
X
X
X
Hi-Z
Selfrefresh
Self-refresh Continue
—
L
L
X
X
X
X
X
X
X
Hi-Z
Selfrefresh
Self-refresh Exit
L
H
L
H
H
H
X
X
X
Hi-Z
L
H
H
X
X
X
X
X
X
Hi-Z
Idle
Power Down Entry
H
L
L
H
H
H
X
X
X
Hi-Z
H
L
H
X
X
X
X
X
X
Hi-Z
Power
Down
Power Down Continue
L
L
X
X
X
X
X
X
X
Hi-Z
Power
Down
Power Down Exit
L
H
L
H
H
H
X
X
X
Hi-Z
L
H
H
X
X
X
X
X
X
Hi-Z
SELFX
*13
PDEN
—
PDEX
*11: The REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL
command). In case of SELF command, it should also be issued after the last read data have been appeared
on DQ. Refer to “■ STATE DIAGRAM”.
*12: CKE must bring to Low level together with REF command.
*13: The PDEN command should only be issued after the last read data have been appeared on DQ and after the
lDPL is satisfied from last write data input.
7
MB81P643287-50/-60
OPERATION COMMAND TABLE (Applicable to single bank)(Note*13)
Current
Address
Command
CS RAS CAS WE
State
Idle
Bank Active
8
Function
Notes
H
X
X
X
X
DESL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
NOP
*15
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*16
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*16
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
NOP
L
L
H
L
BA, AP
PALL
NOP
*15
L
L
L
H
X
REF/SELF
Auto-refresh or Self-refresh
*17
L
L
L
L
MODE
MRS
Mode Register Set
(Idle after lMRD)
*17
H
X
X
X
X
DESL
NOP
L
H
H
H
X
NOP
NOP
L
H
H
L
X
BST
NOP
L
H
L
H
BA, CA, AP
READ/READA
Begin Read; Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Begin Write; Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
PRE
Precharge
L
L
H
L
BA, AP
PALL
Precharge
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
Bank Active after lRCD
Illegal
*15
*16
*15
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
CS
RAS CAS
WE
Address
Command
Notes
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Bank Active)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Bank Active)
L
H
H
L
X
BST
Terminate Burst → Bank Active
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, New Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
L
L
H
H
BA, RA
ACTV
Illegal
L
L
H
L
BA, AP
PRE
Terminate Burst, Precharge
L
L
H
L
BA, AP
PALL
Terminate Burst, Precharge
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Write Recovering)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Write Recovering)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
Terminate Burst, Start Read;
Determine AP
L
H
L
L
BA, CA, AP
WRIT/WRITA
Terminate Burst, New Write;
Determine AP
L
L
H
H
BA, RA
ACTV
L
L
H
L
BA, AP
L
L
H
L
L
L
L
L
L
L
Read
Write
Function
*16
*15
*20
Illegal
*16
PRE
Terminate Burst, Precharge
*18
BA, AP
PALL
Terminate Burst, Precharge
*15,
*18
H
X
REF/SELF
Illegal
L
MODE
MRS
Illegal
9
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
Read With
AutoPrecharge
Write with
Auto
Precharge
10
CS
RAS CAS
WE
Address
Command
Function
Notes
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Precharge)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Precharge)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
Illegal
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
L
L
H
H
BA, RA
ACTV
Illegal
*16
L
L
H
L
BA, AP
PRE
Illegal
*16
L
L
H
L
BA, AP
PALL
Illegal
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Continue Burst to End →
Write Recovering with Precharge)
L
H
H
H
X
NOP
NOP (Continue Burst to End →
Write Recovering with Precharge)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
Illegal
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*16
L
L
H
H
BA, RA
ACTV
Illegal
*16
L
L
H
L
BA, AP
PRE
Illegal
*16
L
L
H
L
BA, AP
PALL
Illegal
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
*16
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
Precharging
Bank
Activating
CS
RAS CAS
WE
Address
Command
Function
Notes
H
X
X
X
X
DESL
NOP (Idle after lRP)
L
H
H
H
X
NOP
NOP (Idle after lRP)
L
H
H
L
X
BST
NOP (Idle after lRP)
*15
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*16
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*16
L
L
H
H
BA, RA
ACTV
Illegal
*16
L
L
H
L
BA, AP
PRE
NOP
*16
L
L
H
L
BA, AP
PALL
NOP
*15
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Bank Active after lRCD)
L
H
H
H
X
NOP
NOP (Bank Active after lRCD)
L
H
H
L
X
BST
NOP (Bank Active after lRCD)
*15
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*16
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*16
L
L
H
H
BA, RA
ACTV
Illegal
*19
L
L
H
L
BA, AP
PRE
Illegal
*16
L
L
H
L
BA, AP
PALL
Illegal
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
11
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
Write
Recovering
Write
Recovering
with Autoprecharge
CS
RAS CAS
WE
Address
Command
Function
H
X
X
X
X
DESL
NOP (Bank Active after lWRD)
L
H
H
H
X
NOP
NOP (Bank Active after lWRD)
L
H
H
L
X
BST
NOP (Bank Active after lWRD)
*15
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*16
L
H
L
L
BA, CA, AP
WRIT/WRITA
New Write; Determine AP
L
L
H
H
BA, RA
ACTV
Illegal
*16
L
L
H
L
BA, AP
PRE
Illegal
*16
L
L
H
L
BA, AP
PALL
Illegal
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Idle after lWAL)
L
H
H
H
X
NOP
NOP (Idle after lWAL)
L
H
H
L
X
BST
Illegal
L
H
L
H
BA, CA, AP
READ/READA
Illegal
*16
L
H
L
L
BA, CA, AP
WRIT/WRITA
Illegal
*16
L
L
H
H
BA, RA
ACTV
Illegal
*16
L
L
H
L
BA, AP
PRE
Illegal
*16
L
L
H
L
BA, AP
PALL
Illegal
L
L
L
H
X
REF/SELF
Illegal
L
L
L
L
MODE
MRS
Illegal
H
X
X
X
X
DESL
NOP (Idle after lRFC)
L
H
H
X
X
NOP/BST
NOP (Idle after lRFC)
L
H
L
X
X
L
L
H
X
X
ACTV/
PRE/PALL
Illegal
L
L
L
X
X
REF/SELF/
MRS
Illegal
Refreshing
12
Notes
READ/READA/
Illegal
WRIT/WRITA
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
Mode
Register
Setting
CS
RAS CAS
WE
Address
Command
Function
H
X
X
X
X
DESL
NOP (Idle after lMRD)
L
H
H
H
X
NOP
NOP (Idle after lMRD)
L
H
H
L
X
BST
Illegal
L
H
L
X
X
READ/READA/
Illegal
WRIT/WRITA
ACTV/PRE/
PALL/REF/
SELF/MRS
Abbreviations: RA = Row Address
BA = Bank Address
CA = Column Address AP = Auto Precharge
L
L
X
X
X
Notes
Illegal
Notes: *14. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
*15. Entry may affect other banks.
*16. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
of that bank.
*17. Illegal if any bank is not idle.
*18. Must mask preceding data that don‘t satisfy lDPL.
*19. Legal if other bank specified in BA is idle state and lRRD is satisfied for that bank.
*20. Must mask preceding data that don‘t satisfy lWRD.
13
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE
Current
State
Selfrefresh
Selfrefresh
Recovery
Power
Down
14
CKE
(n-1)
CKE
(n)
CS
RAS
CAS
WE
Address
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
Exit Self-refresh
(Self-refresh Recovery →
Idle after tPDEX + lSCD or lXSNR)
L
H
L
H
H
H
X
Exit Self-refresh
(Self-refresh Recovery →
Idle after tPDEX + lSCD or lXSNR)
L
H
L
H
H
L
X
Illegal
L
H
L
H
L
X
X
Illegal
L
H
L
L
X
X
X
Illegal
L
L
X
X
X
X
X
NOP (Maintain Self-refresh)
L
X
X
X
X
X
X
Invalid
H
H
H
X
X
X
X
Idle after lSCD or lXSNR
H
H
L
H
H
H
X
Idle after lSCD or lXSNR
H
H
L
H
H
L
X
Illegal
H
H
L
H
L
X
X
Illegal
H
H
L
L
X
X
X
Illegal
H
L
X
X
X
X
X
Illegal
H
X
X
X
X
X
X
Invalid
L
H
H
X
X
X
X
Power Down Exit → Return to original
state after tPDEX
L
H
L
H
H
H
X
Power Down Exit → Return to original
state after tPDEX
L
H
L
H
H
L
X
Illegal
L
H
L
H
L
X
X
Illegal
L
H
L
L
X
X
X
Illegal
L
L
X
X
X
X
X
NOP (Maintain Power Down Mode)
Function
Notes
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE (continued)
Current
State
All
Banks
Idle
Bank Active
CKE
(n-1)
CKE
(n)
CS
RAS
CAS
WE
Address
H
H
H
X
X
X
X
NOP
H
H
L
H
X
X
V
Refer to the Command Truth Table.
H
H
L
L
H
X
V
Refer to the Command Truth Table.
H
H
L
L
L
H
X
Auto-refresh
H
H
L
L
L
L
V
Mode Register Set
*21
H
L
H
X
X
X
X
Power Down Entry
*22
H
L
L
H
H
H
X
Power Down Entry
*22
H
L
L
H
H
L
X
Illegal
H
L
L
H
L
X
X
Illegal
H
L
L
L
H
X
X
Illegal
H
L
L
L
L
H
X
Self-refresh Entry
H
L
L
L
L
L
X
Illegal
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to the Command Truth Table.
H
L
X
X
X
X
X
Illegal
L
H
X
X
X
X
X
Invalid
L
L
X
X
X
X
X
Invalid
Function
Notes
*22
15
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE (continued)
Current
State
CKE
(n-1)
CKE
(n)
CS
RAS
CAS
WE
Address
Bank
Activating,
Read, Write,
Write
Recovering,
Precharging
H
H
X
X
X
X
X
Refer to the Command Truth Table.
H
L
X
X
X
X
X
Illegal
L
H
X
X
X
X
X
Invalid
L
L
X
X
X
X
X
Invalid
Any State
Other Than
Listed Above
L
X
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to the Command Truth Table.
H
L
X
X
X
X
X
Illegal
H
L
H
L
L
L
X
Illegal
H
L
L
H
H
H
X
Illegal
H
L
L
H
H
L
X
Illegal
H
L
L
H
L
X
X
Illegal
H
L
L
L
X
X
X
Illegal
L
L
X
X
X
X
X
Invalid
L
H
X
X
X
X
X
Invalid
H
H
X
X
X
X
X
Refer to the Command Truth Table.
Refresh
Function
Notes
*23
*23
Notes: *21. Refer to “■ MODE REGISTER TABLE”.
*22. PDEN and SELF command should only be issued after the last read data have been appeared on DQ.
*23. The Clock Suspend mode is not supported on this device and it is illegal if CKE is brought to Low during
the Burst Read or Write mode.
16
MB81P643287-50/-60
■ STATE DIAGRAM
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second command
(same bank)
First
command
MRS
*1
MRS
lMRD
ACTV READ
READA
WRIT
WRITA
lMRD
*4
ACTV
lRCD
lRCD
READ
1
1
BST
PRE
PALL
REF
SELF
lMRD
lMRD
lMRD
lMRD
lMRD
1
lRAS
lRAS
1
1
*4
lRCD
*4
lRCD
*3
lRWD
*3, 4
lRWD
*4
*5, 6
READA
BL/2
+ lRP
*4
BL/2
+ lRP
BL/2
+ lRP
*7
lWRD
WRIT
*4, 7
lWRD
*4
1
lWAL
*4
BL/2
+ lRP
*4,7
1
lDPL
*6
WRITA
*4
1
lWAL
*3
1
*4,7
lBSNC
*3
lBSNC
*4
lWAL
*4
*6
lWAL
*6
lWAL
*4
1
1
1
lRP
1
1
1
lRP
lRP
BST
1
*5, 6
BL/2
+ lRP
lDPL
*4
lWAL
*6
BL/2
+ lRP
*5, 6
*4
*6
*5, 6
PRE
lRP
PALL
lRPA
lRPA
1
1
1
lRPA
lRPA
REF
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
SELFX
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
*5
*5
Notes: *1. BL/2 = tCK × BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)
*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. lRAS must be satisfied.
*5. Assume all outputs are in High-Z state.
*6. Assume all other banks are in idle state.
*7. lDPL and lWRD are specified from last data input and assumed preceding pair of write data are masked
by DM0 to DM3 input.
Illegal Command
17
MB81P643287-50/-60
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION
Second command
(other bank)
*10
*8
*8
MRS
ACTV READ
READA
*8
*8
*9
WRIT
WRITA
BST
PRE
PALL
REF
SELF
lMRD
lMRD
lMRD
lMRD
lMRD
1
1
lRAS
1
1
1
*2, 9
First
command
MRS
lMRD
lMRD
*6
ACTV
lRRD
READ
1
*11
*11
*11
1
1
1
1
1
lRWD
*6
*5, 6
READA
BL/2 +
lRP
*3
*6
1
*4
1
*6
WRITA
lWAL
*7
lWRD
*6
1
*4
*6
*5, 6
*6
1
*11
1
*11
1
*4
* 3, 4
*6
lRWD
1
1
1
1
lDPL
BL/2 + BL/2 + BL/2 +
lRP
lRP
lRP
1
lWAL
1
1
1
1
1
lRP
lRP
*4,7
*4
1
*3, 11
lBSNC
*11
1
*5, 6
lRWD
*4
*11
1
*3
lRWD
* 3, 4
*11
*7
lWRD
BL/2 BL/2
+ lWRD + lWRD
1
BST
*4
1
*6
1
WRIT
*11
1
*4
*6
1
*3, 11
lBSNC
*3, 11
*3, 11
1
1
lWAL
*6
lWAL
*4
1
*11
*4
*6
*5, 6
PRE
lRP
PALL
lRPA
lRPA
1
1
1
lRPA
lRPA
REF
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
lRFC
SELFX
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
lXSNR
*5
18
*5
MB81P643287-50/-60
Notes: *1. BL/2 = tCK × BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)
*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. lRAS must be satisfied.
*5. Assume all outputs are in High-Z state.
*6. Assume the other bank(s) is in idle state.
*7. lDPL and lWRD are specified from last data input and assumed preceding pair of write data are masked
by DM0 to DM3 input.
*8. Assume the other bank(s) is in active state and lRCD is satisfied.
*9. Assume the other bank(s) is in active state and lRAS is satisfied.
*10. Second command have to follow the minimum clock latency or delay time of single bank operation in
other bank (second command is asserted.)
*11. Assume other banks are not in READA/WRITA state.
Illegal Command.
19
MB81P643287-50/-60
Fig. 2 - STATE DIAGRAM (Simplified for Single Bank Operation)
SELF
MRS
MODE
REGISTER
SET
SELFREFRESH
SELFX
IDLE
PDEX
REF
PDEN
AUTO
REFRESH
ACTV
POWER
DOWN
BANK
ACTIVE
BST
WRIT
READ
WRIT
READ
READA
WRITA
READ
WRITE
READ
WRIT
WRITE
WITH AUTO
PRECHARGE
POWER
ON
20
PRE or
PALL
PDEX and 8 PRE (or 1 PALL)
POWER
APPLIED
with PDEN
WRITA
READA
PRE or
PALL
WRITA
PRE or
PALL
READA
READ WITH
AUTO
PRECHARGE
PRECHARGE
DEFINITION OF ALLOWS
Manual
Input
Automatic
Sequence
MB81P643287-50/-60
■ FUNCTIONAL DESCRIPTION
DDR, Double Data Rate Function
The regular SDRAM read and write cycle have only used the rising edge of external clock input. When clock
signal goes to High from Low at the read mode, the read out data will be available at every rising clock edge
after the specified latency up to burst length. The MB81P643287 DDR FCRAM features a twice of data transfer
rate within a same clock period by transferring data at every rising and falling clock edge. Refer to Figure 3.
FCRAMTM
The MB81P643287 utilizes FCRAM core technology. The FCRAM is an acronym of Fast Cycle Random Access
Memory and provides very fast random cycle time, low latency and low power consumption than regular DRAMs.
CLOCK INPUT (CLK, CLK)
The MB81P643287 adopts differential clock scheme. CLK is a master clock and its rising edge is used to latch
all command and address inputs. CLK is a complementary clock input.
The MB81P643287 implements Delay Locked Loop (DLL) circuit. This internal DLL tracks the signal cross point
between CLK and CLK and generate some clock cycle delay for the output buffer control at Read mode.
The internal DLL circuit requires some Lock-on time for the stable delay time generation. In order to stabilize
the delay, a constant stable clock input for lPCD period is required during the Power-up initialization and a constant
stable clock input for lSCD period is also required after Self-refresh exit as specified lSCD prior to the any command.
POWER DOWN (CKE)
CKE is a synchronous input signal and enables power down mode.
When all banks are in idle state, CKE controls Power Down (PD) and Self-refresh mode. The PD and Self-refresh
is entered when CKE is brought to Low and exited when it returns to High.
During the Power Down and Self-refresh mode, both CLK and CLK are disabled after specified time.
CKE does not have a Clock Suspend function unlike CKE pin of regular SDRAMs, and it is illegal to bring CKE
into Low if any read or write operation is being performed. For the detail, refer to Timing Diagrams.
It is recommended to maintain CKE to be Low until VDD gets in the specified operating range in order to assure
the power-up initialization.
CHIP SELECT (CS)
CS enables all commands inputs, RAS, CAS, and WE, and address input. When CS is High, all command signals
are negated but internal operation such as burst cycle will not be suspended.
COMMAND INPUTS (RAS, CAS and WE)
As well as regular SDRAMs, each combination of RAS, CAS and WE input in conjunction with CS input at a
rising edge of the CLK determines SDRAM operation. Refer to “■FUNCTION TRUTH TABLE”.
21
MB81P643287-50/-60
BANK ADDRESS (BA0 to BA2)
The MB81P643287 has eight internal banks and each bank is organized as 256K words by 32-bit.
Bank selection by BA occurs at Bank Active command (ACTV) followed by read (READ or READA), write (WRIT
or WRITA), and Precharge(PRE) command.
ADDRESS INPUTS (A0 to A10)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each
bank. A total of twenty address input signals are required to decode such a matrix. DDR SDRAM adopts an
address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV),
eleven Row addresses are initially latched as well as three Bank addresses and the remainder of seven Column
addresses are then latched by a Column address strobe command of either a read command (READ or READA)
or write command (WRIT or WRITA).
DATA STROBE (DQS0 to DQS3)
DQS0 to DQS3 are bi-directional signal and represent byte 0 to byte 3, respectively. During Read operation, DQS0
to DQS3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver
circuit of the controller(s). It turns Low before first data is coming out and toggle High to Low or Low to High till
end of burst read. Refer to Figure 3 for the timing example.
The CAS Latency is specified to the first Low to High transition of these DQS0 to DQS3 output.
During the write operation, DQS0 to DQS3 are used to latch write data and Data Mask signals. As well as the
behavior of read data strobe, the first rising edge of DQS0 to DQS3 input latches first input data and following
falling edge of DQS0 to DQS3 signal latches second input data. This sequence shall be continued till end of burst
count. Therefore, DQS0 to DQS3 must be provided from controller that drives write data.
Note that DQS0 to DQS3 input signal should not be tristated from High at the end of write mode.
DATA INPUTS AND OUTPUTS (DQ0 to DQ31)
Input data is latched by DQS0 to DQS3 input signal and written into memory at the clock following the write
command input. Output data is obtained together with DQS0 to DQS3 output signals at programmed read CAS
latency.
The polarity of the output data is identical to that of the input. Data is valid after DQS0 to DQS3 output signal
transitions (tQSQ) as specified in Data Valid Time (tDV).
WRITE DATA MASK (DM0 to DM3)
DM0 to DM3 are active High enable inputs and represent byte 0 to byte 3 respectively. DM0 to DM3 have a data
input mask function, and are also sampled by DQS0 to DQS3 input signal together with input data.
During write cycle, DM0 to DM3 provide byte mask function. When DMx = High is latched by a DQS0 to DQS3
signal edge, data input at the same edge of DQS0 to DQS3 is masked.
During read cycle, all DM0 to DM3 are inactive and do not have any effect on read operation.
Refer to DM0 to DM3 TRUTH TABLE.
22
MB81P643287-50/-60
BURST MODE OPERATION AND BURST TYPE
The burst mode provides faster memory access and MB81P643287 read and write operations are burst oriented.
The burst mode is implemented by keeping the same Row address and by automatic strobing Column address
in every single clock edge till programmed burst length(BL). Access time of burst mode is specified as tACC. The
internal column address counter operation is determined by a mode register which defines burst type(BT) and
burst count length(BL) of 2, 4 or 8 bits of boundary. In order to terminate or to move from the current burst mode
to the next stage while the remaining burst count is more than 2, the following combinations will be required.
Current Stage
Next Stage
Method (Assert the following command)
Burst Read
Burst Read
Burst Read
Burst Write
Burst Write
Burst Write
Burst Write
Burst Read
Burst Read
Precharge
Burst Write
Precharge
Read Command
1st Step
Burst Stop Command (BST)
2nd Step
Write Command after lBSNC
Write Command
1st Step
Data Mask Input
2nd Step
Read Command after lWRD from last data input
Precharge Command
1st Step
Data Mask Input
2nd Step
Precharge Command after lDPL from last data input
The burst type is sequential only. The sequential mode is an incremental decoding scheme within a boundary
address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end
of boundary address and then wraps round to the least significant address(= 0). If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
Starting Column Address
Sequential Mode
Burst Length
A2 A1 A0
2
4
8
X X 0
0–1
X X 1
1–0
X 0 0
0–1–2–3
X 0 1
1–2–3–0
X 1 0
2–3–0–1
X 1 1
3–0–1–2
0 0 0
0–1–2–3–4–5–6–7
0 0 1
1–2–3–4–5–6–7–0
0 1 0
2–3–4–5–6–7–0–1
0 1 1
3–4–5–6–7–0–1–2
1 0 0
4–5–6–7–0–1–2–3
1 0 1
5–6–7–0–1–2–3–4
1 1 0
6–7–0–1–2–3–4–5
1 1 1
7–0–1–2–3–4–5–6
23
MB81P643287-50/-60
BURST STOP COMMAND (BST)
The Burst Stop command (BST) terminates the burst read operation except for a case that Auto-precharge option
is asserted. When the BST command is issued during the burst read operation, the all output buffers, DQs and
DQS0 to DQS3, will turn to High-Z state after some latencies that to be matched with programmed CAS latency
and internal bank state remains active state.
In a case of terminating the burst write operation, the BST command should not be issued at any time during
burst write operation. Refer to previous page for the write interrupt and termination rule.
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
The DDR SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is executed by the precharge
operation (PRE or PALL). With the precharge operation, DDR SDRAM will automatically be in standby state
after specified precharge time (lRP, lRPA).
The precharged bank is selected by combination of AP and bank address (BA) when precharge command is
issued. If AP = High, all banks are precharged regardless of BA (PALL command). If AP = Low, a bank to be
selected by BA is precharged (PRE command).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
issue. This auto-precharge is entered by AP = High when a Read (READ) or Write (WRIT) command is issued.
Applying BST is illegal if the Auto-precharge option is used.
Refer to “■FUNCTION TRUTH TABLE”.
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The MB81P643287 Auto-refresh command (REF) automatically generates Bank Active and Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be issued within every 8
µs period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh operation until cancelled by SELFX.
The Self-refresh mode is entered by applying an Auto-refresh command in conjunction with CKE = Low (SELF).
Once MB81P643287 enters the self-refresh mode, all inputs except for CKE can be either logic high or low level
state and outputs will be in a High-Z state. During Self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted
prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit Self-refresh mode, CKE must bring to High for at least 2 clock cycles together with NOP condition.
Refer to Timing Diagram for the detail procedure. It is recommended to issue at least one Auto-refresh command
just after the lRFC period to avoid the violation of refresh period.
WARNING: A stable clock for lSCD period with a constant duty cycle must be supplied prior to applying any read
command to insure the DLL is locked against the latest device conditions.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted
both before the self-refresh entry and after the self-refresh exit.
24
MB81P643287-50/-60
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS Latency, and Test Mode Entry (This Test Mode Entry must not be used).
Refer to MODE REGISTER TABLE.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power). MRS command should only be issued on condition that all
banks are in idle state and all DQS are in High-Z. The condition of the mode register is undefined after the powerup stage. It is required to set each field at power-up initialization.
Refer to POWER-UP INITIALIZATION below.
Note: The Extended Mode Register Set command (EMRS) and its DLL Enable function of EMRS field is only used
at power-on sequence.
POWER-UP INITIALIZATION
The MB81P643287 internal condition at and after power-up will be undefined. It is required to follow the following
Power On Sequence to execute read or write operation.
1. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input
signals to be Low state (or at least CKE to be Low state).
2. Apply VDD voltage to all VDDQ pins before or at the same time as VREF and VTT.
3. Apply VREF and VTT. (VTT is applied to the system).
4. Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200 µs.
5. After the minimum of 200 µs stable power and clock, apply NOP condition and take CKE to be High
state.
6. Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every
banks.
7. Issue EMRS to enable DLL, DE = Low.
8. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lPCD*1
period is required to lock the DLL.
9. Apply minimum of two Auto-refresh command (REF).*2
10. Program the mode register by Mode Register Set command (MRS) with DR = Low.*2
*1: The lPCD depends on operating clock period. The lPCD is counted from “DLL Reset” at step-8 to any command
input at step-10.
*2: The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
POWER-DOWN
The MB81P643287 uses multiple power supply voltage. It is required to follow the reversed sequence of above
Power On Sequence.
1. Take all input signals to be VSS or High-Z.
2. Deapply VDDQ.
3. Deapply VDD at the same time as VDDQ.
25
MB81P643287-50/-60
Fig. 3 - SDRAM READ TIMING EXAMPLE (@ CL=2 & BL=2)
<SDRAM>
t0
t1
t2
t3
t4
CLK
(external)
Command
READ
Stored by CLK input
DATA
Hi-Z
Q1
Q2
Output in every rising CLK edge
< DDR SDRAM >
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
CLK
CLK
Command
READ
DQS signal transition
occurs at the same
time as data bus.
Stored by CLK input
DQS
DATA
Hi-Z
Low
Hi-Z
High
Q1
Q2
Output in every
cross point of clock input
26
MB81P643287-50/-60
■ MODE REGISTER TABLE
MODE REGISTER SET
ADDRESS BA2 BA1 BA0
0*1
REGISTER
0*1
0*1
A10
A9
A8
A7
A6 to A4
A3
A2 to A0
0
0
DR
TE
CL
BT
BL
A6
A5
A4
CAS Latency
(CL)
A2
A1
A0
Burst Length
(BL)
0
0
X
Reserved
0
0
0
Reserved
0
1
0
2
0
0
1
2
0
1
1
3
0
1
0
4
1
0
0
Reserved
0
1
1
8
1
0
1
Reserved
1
X
X
Reserved
1
1
0
Reserved
1
1
1
Reserved
A7
Test Mode Entry (TE)
0
Normal Operation
1
Test Mode (Used for Supplier Test
Mode)
A8
A3
Burst Type (BT)
0
Sequential (Wrap round, Binary up)
1
Reserved
DLL RESET (DR)
0
Normal Operation
1
RESET DLL
EXTENDED MODE REGISTER SET (Note *4)
ADDRESS
BA2 BA1 BA0 A10 A9
EXTENDED MODE
REGISTER
0*2
0*2
A8
1*2
A7
A6
A5
A4
A3
A2
A1
RESERVED *3
A0
DE
DLL Enable (DE)
A0
0
DLL Enable
1
DLL Disable
*1: A combination of BA2 = BA1 = BA0 = 0 (Low) selects standard Mode Register.
*2: A combination of BA1 = BA2 = 0 and BA0 = 1 (High) selects Extended Mode Register.
*3: These RESERVED field in EMRS must be set as 0.
27
MB81P643287-50/-60
■ ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter
Symbol
Value
Unit
Voltage of VDD Supply Relative to VSS
VDD, VDDQ
–0.5 to +3.6
V
Voltage at Any Pin Relative to VSS
VIN, VOUT
–0.5 to +3.6
V
Short Circuit Output Current
IOUT
±50
mA
Power Dissipation
PD
2.0
W
TSTG
–55 to +125
°C
Storage Temperature
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter
Notes
Supply Voltage
Min.
Typ.
Max.
Unit
VDD
2.3
2.5
2.7
V
VDDQ
VDD
VDD
VDD
V
VSS, VSSQ
0
0
0
V
VDDQ × 0.49 VDDQ × 0.5 VDDQ × 0.51
V
Input Reference Voltage
*1
VREF
Termination Voltage
*2
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Single Ended SSTL DC Level Input High Voltage
*3
VIH (DC)
VREF + 0.25
—
VDDQ + 0.1
V
Single Ended SSTL DC Level Input Low Voltage
*3
VIL (DC)
- 0.1
—
VREF - 0.25
V
Single Ended SSTL AC Level Input High Voltage *3, *5
VIH (AC)
VREF + 0.35
—
—
V
Single Ended SSTL AC Level Input Low Voltage *3, *5
VIL (AC)
—
—
VREF - 0.35
V
Differential DC Level Input Voltage Range
*3
VIN (DC)
- 0.1
—
VDDQ + 0.1
V
Differential DC Level Differential Input Voltage
*3 VSWING (DC)
0.5
—
VDDQ + 0.2
V
Differential AC Level Differential Input Voltage
*3 VSWING (AC)
0.7
—
—
V
Differential AC Level Input Crosspoint Voltage
*3
VX (AC)
VDDQ/2 - 0.2
VDDQ/2
VDDQ/2 + 0.2
V
Differential Input Signal Offset Voltage
*4
VISO (AC)
VDDQ/2 - 0.2
VDDQ/2
VDDQ/2 + 0.2
V
Termination Resistor (SSTL I/Os)
*2
RT
—
50
—
Ω
TA
0
—
70
o
Ambient Temperature
Note 5.
Note 6.
VDD + 1.0 V
VIH
50% of pulse amplitude
VIH
VIHmin
VIL
28
Symbol
Pulse width < 4 ns
VILmax
VIL
50% of pulse amplitude
Pulse width < 4 ns
−1.0 V
C
MB81P643287-50/-60
Notes: *1. VREF is expected to track variations in the DC level of VDDQ of the transmitting device. Peak-to-Peak
noise level on VREF may not exceed ± 2% of the supplied DC value.
*2. VTT is used for SSTL_2 bus and is not applied to the device. VTT is expected to be set equal to VREF
and must be track variations in the DC level of VREF.
*3. Applicable when signal(s) is terminated to the VTT of SSTL_2 bus.
*4. VISO means {VIN(CLK) + VIN(CLK)} / 2. Refer to Differential Input Signal Definition.
*5. Overshoot limit: VIH (Max.) = VDD + 1.0V for pulse width ≤ 4 ns acceptable, pulse width measured at
50% of pulse amplitude.
*6. Undershoot limit: VIL (Min.) = VSS -1.0V for pulse width ≤ 4 ns acceptable, pulse width measured at
50%of pulse amplitude.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Differential Input Signal Definition
Fig. 4 - Differential Input Signal Offset Voltage (For Clock Input)
CLK
VX
CLK
VSWING (AC)
VSS
IVSWINGI
0 V Differential
VISO
VISO (Max.)
VISO (Min.)
VSS
■ CAPACITANCE
(TA = 25°C, f = 1 MHz)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input Capacitance, Address & Control
CIN1
2.5
—
3.5
pF
Input Capacitance, CLK & CLK
CIN2
2.5
—
3.5
pF
Input Capacitance, DM0 to DM3
CIN3
4.0
—
5.5
pF
I/O Capacitance
CI/O
4.0
—
5.5
pF
29
MB81P643287-50/-60
■ DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Note *1,*2,*3
Parameter
Symbol
Condition
Value
Min.
Max.
Unit
Output Minimum Source DC Current
IOH(DC)
VDDQ = 2.3V,
VOH = VDDQ-0.43V
-15.2
—
mA
Output Minimum Sink DC Current
IOL(DC)
VDDQ = 2.3V,
VOL = +0.35V
15.2
—
mA
Input Leakage Current (any input)
ILI
0 V ≤ VIN ≤ VDD;
All other pins not under test = 0 V
-10
10
µA
Output Leakage Current
ILO
0 V ≤ VIN ≤ VDD;
Data out disabled
-10
10
µA
VREF Current
IREF
-10
10
µA
MB81P643287-50
Operating Current
(Average Power
Supply Current)
IDD1S
MB81P643287-60
CKE = VIL, tCK = Min.
All banks idle,
0 V ≤ VIN ≤ VDD
—
IDD3N
CKE = VIH, tCK = Min.
All banks Active,
NOP commands only,
Input signals (except to CMD) are
changed one time during 20 ns
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
MB81P643287-50
MB81P643287-60
mA
405
IDD2P
MB81P643287-60
Active Standby Current
(Power Supply Current)
—
—
IDD2N
Power Down Current
460
CKE = VIH, tCK = Min.
All banks idle,
NOP commands only,
Input signals (except to CMD) are
changed one time during 20 ns
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
MB81P643287-50
Standby Current
Burst Length = 2
tCK = Min.,
One bank active,
Address change up to 3 times during lRC (Min.)
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
85
mA
75
35
mA
260
—
mA
225
(Continued)
30
MB81P643287-50/-60
(Continued)
Parameter
Symbol
MB81P643287-50
Burst Read Current
(Average Power
Supply Current)
IDD4R
MB81P643287-60
MB81P643287-50
Burst Write Current
(Average Power
Supply Current)
IDD4W
MB81P643287-60
Auto-refresh Current MB81P643287-50
(Average Power
Supply Current)
MB81P643287-60
IDD5
Self-refresh Current
(Average Power Supply Current)
IDD6
Condition
Burst Length = 4,
CAS Latency = 3,
All bank active,
Gapless data,
tCK = Min.,
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
Burst Length = 4,
CAS Latency = 3,
All bank active,
Gapless data,
tCK = Min.,
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
Value
Min.
Max.
Unit
535
—
mA
460
595
—
mA
505
Auto-refresh;
tCK = Min.,
0 V ≤ VIN ≤ VIL (Max.),
VIH (Min.) ≤ VIN ≤ VDD
—
Self-refresh;
CKE = VIL,
0 V ≤ VIN ≤ VDD
—
320
mA
270
5
mA
Notes: *1. All voltages referenced to VSS.
*2. DC characteristics are measured after following the POWER-UP INITIALIZATION procedure.
*3. IDD depends on the output termination or load conditions, clock cycle rate, and number of address and
command change within certain period. The specified values are obtained with the output open.
31
MB81P643287-50/-60
■ AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.) Note *1,*2,*3
AC PARAMETERS (CAS LATENCY DEPENDENT)
Parameter
Clock Period
Symbol
tCK
Parameter
Notes
Min.
Max.
Min.
Max.
CL = 3
5.0
9.0
6.0
10.5
CL = 2
7.5
10.5
9.0
10.5
Symbol
MB81P643287-50 MB81P643287-60
Min.
Max.
Min.
Max.
Unit
ns
Unit
Input Setup Time
(Except for DQS, DM and DQs)
*4
tIS
1.0
—
1.2
—
ns
Input Hold Time
(Except for DQS, DM and DQs)
*4
tIH
1.0
—
1.2
—
ns
DM and Data Input Setup Time
*5
tDS
0.6
—
0.7
—
ns
DM and Data Input Hold Time
*5
tDH
0.6
—
0.7
—
ns
DQS First Input Setup Time
(Input Preamble Setup Time)
*6
tDSPRES
0
—
0
—
ns
tQCKEH
0
—
0
—
ns
Last Data Output to CKE High Level
Hold Time
Input Transition Time
*7
tT
0.1
0.8
0.1
0.9
ns
Precharge Power Down Exit
and Self-refresh Exit Time
*4
tPDEX
3.0
—
3.6
—
ns
Time between Refresh
*8
tREF
—
32
—
32
ms
Time between Auto-refresh Command
*8
tAREF
—
8.0
—
8.0
µs
tPAUSE
200
—
200
—
µs
Pause Time after Power-on
32
MB81P643287-50 MB81P643287-60
MB81P643287-50/-60
AC PARAMETERS (FREQUENCY DEPENDANT) Note *9
Parameter
Notes Symbol
Min.
Max.
Unit
Clock High Time
*4
tCH
0.45 × tCK
—
ns
Clock Low Time
*4
tCL
0.45 × tCK
—
ns
tDQSS
0.75 × tCK
1.25 × tCK
ns
DQS Low Input Pulse Width
tDSL
0.4 × tCK
—
ns
DQS High Input Pulse Width
tDSH
0.4 × tCK
—
ns
tDSPREH
0.25 × tCK
—
ns
DQS First Low Input Pulse Width
(Input Preamble Pulse Width)
tDSPRE
0.4 × tCK
—
ns
DQS Last Low Input Hold Time
(Input Postamble Hold Time)
tDSPST
0.4 × tCK
—
ns
tQSCK
- 0.1 × tCK - 0.2
0.1 × tCK + 0.2
ns
tQSV
0.3 × tCK
—
ns
*4, *11
tQSLZ
- 0.1 × tCK - 0.2
—
ns
DQS First Low Output Hold Time
(Output Preamble Hold Time)
*4
tQSPRE
0.9 × tCK - 0.2
1.1 × tCK + 0.2
ns
DQS Last Low Output Hold Time
(Output Postamble Hold Time)
*4, *12
tQSPST
0.4 × tCK - 0.2
0.6 × tCK + 0.2
ns
*12
tQSHZ
—
0.1 × tCK + 0.2
ns
DQ Access Time from CLK & CLK
*4
tACC
- 0.1 × tCK - 0.2
0.1 × tCK + 0.2
ns
DQ Access Time from DQS
*5
tQSQ
- 0.1 × tCK
0.1 × tCK
ns
tDV
0.3 × tCK
—
ns
DQS Low to High Input Transition
Setup Time from CLK
DQS First Low Input Hold Time
(Input Preamble Hold Time)
DQS Access Time from Clock
*4, *10
*4
*4
DQS Output Valid Time
DQS Output in Low-Z
(Output Preamble Setup Time)
DQS Last Low Output in High-Z
from CLK or CLK
DQ Output Data Valid Time from DQS
DQ Output in Low-Z
*4, *11
tLZ
- 0.1 × tCK - 0.2
—
ns
DQ Output in High-Z
*4, *12
tHZ
- 0.1 × tCK - 0.2
0.1 × tCK + 0.2
ns
DQ & DM Input Pulse Width
tDIPW
0.4 × tCK
—
ns
DQS Falling Edge to Clock Hold Time
tDSCH
0.2 × tCK
(1.5 ns Min.)
—
ns
DQS Falling Edge to Clock Setup Time
tDSCS
0.2 × tCK
(1.5 ns Min.)
—
ns
33
MB81P643287-50/-60
EXAMPLE OF FREQUENCY DEPENDANT AC PARAMETERS (@ Minimum tCK)
tCK = 6ns tCK = 7.5ns tCK = 9ns
tCK = 5ns
Parameter
Symbol
34
tCK = 10.5ns
Min. Max. Min. Max. Min. Max. Min. Max.
Min.
Max.
Unit
Clock High Time
tCH
2.3
—
2.7
—
3.4
—
4.1
—
4.8
—
ns
Clock Low Time
tCL
2.3
—
2.7
—
3.4
—
4.1
—
4.8
—
ns
DQS Low to High Input
Transition Setup Time from CLK
tDQSS
3.8
6.3
4.5
7.5
5.7
9.4
6.8
11.3
7.9
13.2
ns
DQS Low Input Pulse Width
tDSL
2.0
—
2.4
—
3.0
—
3.6
—
4.2
—
ns
DQS High Input Pulse Width
tDSH
2.0
—
2.4
—
3.0
—
3.6
—
4.2
—
ns
DQS First Low Input Hold Time
(Input Preamble Hold Time)
tDSPREH
1.3
—
1.5
—
1.9
—
2.3
—
2.7
—
ns
DQS First Low Input Pulse Width
(Input Preamble Pulse Width)
tDSPRE
2.0
—
2.4
—
3.0
—
3.6
—
4.2
—
ns
DQS Last Low Input Hold Time
(Postamble Hold Time)
tDSPST
2.0
—
2.4
—
3.0
—
3.6
—
4.2
—
ns
DQS Access Time from Clock
tQSCK
-0.7
0.7
-0.8
0.8
-1.0
1.0
-1.1
1.1
-1.3
1.3
ns
DQS Output Valid Time
tQSV
1.5
—
1.8
—
2.3
—
2.7
—
3.2
—
ns
DQS Output in Low-Z
(Output Preamble)
tQSLZ
-0.7
—
-0.8
—
-1.0
—
-1.1
—
-1.3
—
ns
DQS First Low Output Hold Time
(Output Preamble)
tQSPRE
4.3
5.7
5.2
6.8
6.6
8.5
7.9
10.1
9.3
11.8
ns
DQS Last Low Output Hold Time
(Output Postamble)
tQSPST
1.8
3.2
2.2
3.8
2.8
4.7
3.4
5.6
4.0
6.5
ns
DQS Last Low Output in High-Z
from CLK or CLK
tQSHZ
—
0.7
—
0.8
—
1.0
—
1.1
—
1.3
ns
DQ Output Access Time
from CLK & CLK
tACC
-0.7
0.7
-0.8
0.8
-1.0
1.0
-1.1
1.1
-1.3
1.3
ns
DQ Output Access Time
from DQS
tQSQ
-0.5
0.5
-0.6
0.6
-0.8
0.8
-0.9
0.9
-1.1
1.1
ns
DQ Output Data Valid Time
from DQS
tDV
1.5
—
1.8
—
2.3
—
2.7
—
3.2
—
ns
DQ Output in Low-Z
tLZ
-0.7
—
-0.8
—
-1.0
—
-1.1
—
-1.3
—
ns
DQ Output in High-Z
tHZ
-0.7
0.7
-0.8
0.8
-1.0
1.0
-1.1
1.1
-1.3
1.3
ns
DQ & DM Input Pulse Width
tDIPW
2.0
—
2.4
—
3.0
—
3.6
—
4.2
—
ns
DQS Falling Edge to Clock Hold
Time
tDSCH
1.5
—
1.5
—
1.5
—
1.8
—
2.1
—
ns
DQS Falling Edge to Clock
Setup Time
tDSCS
1.5
—
1.5
—
1.5
—
1.8
—
2.1
—
ns
MB81P643287-50/-60
LATENCY
(The latency values on these parameters are fixed regardless of clock period.)
MB81P643287-50
MB81P643287-60
Symbol
Parameter
Notes
Min.
Max.
Min.
Max.
Unit
6
—
6
—
tCK
5
—
5
—
tCK
4
11000
4
11000
tCK
3
7333
3
7333
tCK
2
—
2
—
tCK
3
—
3
—
tCK
2
—
2
—
tCK
1
—
1
—
tCK
4
—
4
—
tCK
3
—
3
—
tCK
BL/2+3
—
BL/2+3
—
tCK
BL/2+2
—
BL/2+2
—
tCK
lWRD
2.5
—
2.5
—
tCK
Last Input Data to Precharge Command
Lead Time
*14
lDPL
2.5
—
2.5
—
tCK
Write with Auto Precharge Command to
Active command Delay
*14
lWAL
BL/2+3+lRP
—
BL/2+3+lRP
—
tCK
Mode Register Access to Next Command
Input Delay
lMRD
2
—
2
—
tCK
CAS to CAS Delay
lCCD
1
—
1
—
tCK
CAS Bank Delay
lCBD
1
—
1
—
tCK
lPDEXP
2
—
2
—
tCK
Minimum Stable Clock Input After Self- *15
refresh Exit Before READ Command Input
lSCD
400
—
400
—
tCK
Minimum Stable Clock Input After Selfrefresh Exit Before non-READ Command
Input
lXSNR
12
—
12
—
tCK
Minimum Stable Clock Input for tCK ≤ 7.5ns
DLL Lock-on in Power-up
Initialization sequence.
*16 tCK ≤ 10.5ns
400
—
400
—
tCK
lPCD
630
—
630
—
tCK
Auto-refresh Cycle Time
lRFC
12
—
12
—
tCK
RAS Cycle Time
*13
RAS Active Time
CL = 3
CL = 2
CL = 3
CL = 2
RAS Precharge Time
RAS to CAS Delay Time
Read Command to Write
Command Delay
lRAS
lRP
CL = 3
CL = 2
RAS to RAS Bank Active Delay Time
Precharge All Bank to Active
lRC
lRRD
CL = 3
CL = 2
CL = 3
CL = 2
Last Input Data to Read Command
Delay
lRCD
*14
Precharge Power Down Exit to Next
Command Input Delay
lRPA
lRWD
35
MB81P643287-50/-60
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
Parameter
BST Command to Output in High-Z
BST Command to New Command Input *17
Notes Symbol MB81P643287-50
CL = 3
CL = 2
CL = 3
CL = 2
DM to Input Data Delay
Precharge to Output in High-Z
lBSNC
lDQD
CL = 3
CL = 2
CKE Low to Command/Address Input Inactive
36
lBSH
lROH
lCKE
MB81P643287-60
Unit
3
3
tCK
2
2
tCK
3
3
tCK
2
2
tCK
0
0
tCK
3
3
tCK
2
2
tCK
1
1
tCK
MB81P643287-50/-60
Notes: *1. AC characteristics are measured after following the POWER-UP INITIALIZATION procedure and stable
clock input with constant clock period and with 50% duty cycle.
*2. Access Times assume input slew rate of 1ns/volt between VREF+0.35V to VREF-0.35V, where VREF is
VDDQ/2, with SSTL_2 output load conditions. Refer to AC TEST LOAD CIRCUIT.
*3. VREF = 1.25V is a typical reference level for measuring timing of input signals.
Transition times are measured between VIH(Min.) and VIL(Max.) unless otherwise noted.
Refer to AC TEST CONDITIONS.
*4. This parameter is measured from the cross point of CLK and CLK input.
*5. This parameter is measured from signal transition point of DQS0 to DQS3 input crossing VREF level.
*6. The specific requirement is that DQS be valid (HIGH or LOW) on or before this CLK edge. The case
shown (DQS going from High-Z to logic LOW) applies when no writes were previously in progress on
the bus. If a previous write was in progress, DQS could be HIGH at this time, depending on tDSS.
*7. tT is defined as the transition time between VIH (AC)(Min.) and VIL (AC)(Max.).
*8. Total of 4096 REF command must be issued within tREF (Max.). tAREF is a reference value for distributed
refresh and specifies the time between one REF command to next REF command except for a condition
where CKE = Low during Self-refresh mode.
*9. This parameter is scalable by actual clock period (tCK) and affected by an abrupt change of duty cycle,
jitters on clock input, TA and level of VDD and VDDQ.The internal DLL circuit can adjust delay time against
the change of following condition :
TA < 0.1 °C / 20 ns,
VDD < 1 mV / 10 ns,
VDDQ < 1 mV / 10 ns,
if change rate is bigger than these values, frequency dependent AC parameters affected by DLL jitters.
*10. More than 2 signal edge of DQS0 to DQS3 should not be input within 1 clock (tCK) cycle.
*11. Low-Z (Low Impedance State) is specified and measured at VTT ± 200mV.
*12. tQSPST, tQSHZ and tHZ are specified where output buffer is no longer driven.
*13. Actual clock count of lRC will be sum of clock count of lRAS and lRP.
*14. Assume tDQSS = 1 × tCK. If actual tDQSS is within specified minimum and maximum range, those parameters
can be assumed tDQSS = 1 × tCK.
*15. Applicable also if device operating conditions such as supply voltages, case temperature, and/or clock
frequency (tCK difference must be 0.2 ns or less) is changed during any operation.
*16. Clock period must satisfy specified tCK and it must be stable.
*17. Assume BST is effective to read operation (issued prior to the end of burst read).
37
MB81P643287-50/-60
Fig. 5 - AC TEST LOAD CIRCUIT (SSTL_2, Class II)
VTT = 0.5 × VDDQ
Output
measurement
point
VTT = 0.5 × VDDQ
RT1 = 50 Ω
RT2 = 50 Ω
RS = 25 Ω
Output
Z0 = 50 Ω
VDDQ
VDDQ
VREF
0.5 × VDDQ
VREF = 0.5 × VDDQ
CL = 20 pF
Device
Under
Test
VSS
Note: AC characteristics are measured in this condition. This load circuit is not applicable for DC Test.
AC TEST CONDITIONS
Parameters
Symbol
Value
Unit
Input High Level
VIH
VREF + 0.35
V
Input Low Level
VIL
VREF − 0.35
V
VREF
VDDQ / 2
V
SLEW
1.0
V/ns
Vr
VX (AC)*
V
Input Level
VSWING
0.7
V
Input Slew Rate
SLEW
1.0
V/ns
Single-end Input
Input Reference Level
Input Slew Rate
Differential Input (CLK and CLK)
Input Reference Level
* : VX means the actual cross point between CLK and CLK input.
38
MB81P643287-50/-60
Fig. 6 - AC TIMING of CLK & CLK
tCK
tCL
tCH
CLK
VX
VSWING (AC)
CLK
Note: Reference level for AC timings of clock are the cross point of CLK and CLK as specified in VX.
Fig. 7 - AC TIMING of Command Input & Address
tCK
CLK
VX
CLK
tIS
Input
(Controls &
Addresses)
tIH
VIH (AC)
Input Valid
VREF
VIL (AC)
Note: The cross point of CLK and CLK (VX) is used for command and address input.
The reference level of single ended input is VREF.
Fig. 8 - AC TIMING of Write Mode (Data Strobe, Write Data and Data Mask Input)
tCK
tCK
CLK
CLK
tIS
Input
(Controls &
Addresses)
tIH
VIH (AC)
Write Command
VREF
tDSCS
VIL (AC)
tDQSS
tDSPRES
DQS Input
(@BL = 4)
VREF
tDQSS
tDSPREH
tDSH
tDSH
tDSPST
tDSPRE
VREF
tDSCH
VIL
tDS
Input
(Data & DM)
tDSL
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Input Valid
Input Valid
Input Valid
Input Valid
tDIPW
tDIPW
tDIPW
tDIPW
39
MB81P643287-50/-60
Fig. 9 - AC TIMING of Read Mode (Clock to DQS Output Delay Time)
tCK
tCK
CLK
VX
CLK
tQSCK(Min.)
tQSLZ
(Min.)
tQSPRE
DQS Output
(@BL = 4)
tQSCK
tQSCK
tQSCK
(Min.)
(Min.)
(Min.)
tQSHZ
tQSCK
tQSCK
tQSCK
tQSCK
(Max.)
(Max.)
(Max.)
(Max.)
tQSV
tQSV
tQSV
VTT
VTT − 0.2 V
tQSPST
Note: DQS Access time (tQSCK) is measured from the cross point of clock (VX) and VREF.
The end of tQSPST and tQSHZ specification is defined at where output buffer is no longer driven.
Fig. 10 - AC TIMING of Read Mode (Clock to Data Output Delay Time)
tCK
tCK
CLK
VX
CLK
tLZ
tACC
(Min.)
tACC
(Min.)
tACC
(Min.)
tACC
(Max.)
tACC
(Max.)
tACC
(Max.)
tHZ
(Min.)
DQS Data
Output
(@BL = 4)
VTT
tACC
(Max.)
VTT + 0.2 V
VTT − 0.2 V
Note: Access time (tACC) is measured from the cross point of clock (VX) and VREF.
The end of tHZ specification is defined at where output buffer is no longer driven.
Fig. 11 - AC TIMING of Read Mode (DQS Output to Data Output Delay Time)
DQS Output
(@BL = 4)
DQ Data
Output
(@BL = 4)
VREF
VTT
tQSQ
tQSQ
tQSQ
tQSQ
(Min.)
(Min.)
(Min.)
(Min.)
tQSQ
(Max.)
tQSQ
(Max.)
tQSQ
(Max.)
tQSQ
(Max.)
tDV
tDV
tDV
tDV
VTT + 0.2 V
VTT − 0.2 V
Note: DQS Output Edge to Data Output Edge Skew Time (tQSQ) is measured from VTT to VTT.
40
MB81P643287-50/-60
Fig. 12 - AC TIMING, PULSE WIDTH
CLK
VX
CLK
VX
IRAS, IRP, IRPA, IRCD, IRRD, tREF, tAREF
Input
(Controls &
Addresses)
Command
Command
Note: All parameters listed above are measured from the cross point at rising edge of the CLK and
falling edge of CLK of one command input to next command input.
Fig. 13 - AC TIMING of Precharge Power Down Mode
IRC (Min.), tREF (Max.)
CKE
VREF
tIS
IPDEXP (Min.) *2
tPDEX
CLK
CLK
ICKE
Command
NOP
NOP
Note*1
NOP
Don't Care
NOP
NOP
ACTV
Notes: *1. Minimum 2 clock cycles is required for complete power down on clock buffer.
*2. If either any supply voltage or clock input condition is changed from the previous operating
condition (other than PDEN and REF), lSCD must be satisfied prior to any command input.
Fig. 14 - AC TIMING of Self-refresh Mode
IRFC (Min.) *2
VREF
CKE
tIS
tPDEX
ISCD *3 or IXSNR
CLK
CLK
Note *1
ICKE
Command
NOP
SELF
NOP
Don't Care
NOP
NOP
ACTV
Notes: *1. Minimum 2 clock cycles is required for complete power down on clock buffer.
*2. CKE must maintain High level and clock must be provided during the lSCD period. lSCD must
be satisfied before read command input.
*3. lSCD must be satisfied before read command input.
41
MB81P643287-50/-60
■ TIMING DIAGRAMS
TIMING DIAGRAM - 1: COLUMN ADDRESS TO COLUMN ADDRESS INPUT DELAY
CLK
CLK
lRCD (Min.)
Address
Row
Address
lCCD (Min.)
Column
Address
lCCD
Column
Address
lCCD
Column
Address
lCCD
Column
Address
Column
Address
RAS
CAS
Note: lCCD, CAS to CAS address delay, is applicable to the same bank access and
it can be one or more clock period.
TIMING DIAGRAM - 2: DIFFERENT BANK ADDRESS INPUT DELAY
CLK
CLK
lRRD (Min.)
Address
Row
Address
lCBD (Min.)
Row
Address
lCBD
Column
Address
lCBD
lCBD
Column
Address
Column
Address
Column
Address
Bank 1
Bank 2
bank 3
lRCD (Min.)
lRCD (Min.)
BA0, BA1
RAS
CAS
42
Bank 0
Bank 1
Bank 0
MB81P643287-50/-60
TIMING DIAGRAM - 3: READ (EXAMPLE @ BL = 4)
CLK
CLK
CKE
High
ICCD (Min.)
Command
READ
READ
NOP
CAS Latency
CAS Latency
DQS
(Output)
@CL = 2
Hi-Z
Preamble
DQ0 to DQ31 Hi-Z
(Output)
@CL = 2
Q1
Q2
Q1
Q2
Q3
Q4
Q1
Q2
Q1
Q2
CAS Latency
CAS Latency
DQS
(Output)
@CL = 3
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
@CL = 3
Preamble
Q3
Q4
Note: CAS Latency is defined from Read command to first rising edge of DQS0 to DQS3 output.
Preamble is 1 × tCK length and starts driving Low level.
43
MB81P643287-50/-60
TIMING DIAGRAM - 4: WRITE (EXAMPLE @ BL = 4)
CLK
CLK
CKE
High
ICCD (Min.)
Command
WRIT
WRIT
tDSPRES
DQS (Input)
tDSPREH
NOP
Don't Care
tDQSS
tDSPRE
Don't Care
Don't Care
tDQSS
DQ0 to DQ31
(Input)
Don't Care
D1
D2
D1
D2
D3
D4
Note: DQS Setup Time, tDQSS, must be within a range of 0.75*tCK to 1.25*tCK from write command Input.
TIMING DIAGRAM - 5: DM, WRITE DATA MASK (EXAMPLE @ BL = 4)
CLK
CLK
Command
WRIT
NOP
WRIT
tDQSS
DQS (Input)
DM
NOP
tDQSS
Don't Care
Don't Care
Don't Care
Don't Care
lDQD = 0
DQ0 to DQ31
(Input)
Don't Care
D1
D2

Masked
D4
lDQD = 0
D1

D3
D4
Masked
Note: DM are latched by DQS Input together with Data Input after write command.
44
Don't Care
MB81P643287-50/-60
TIMING DIAGRAM - 6: READ WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2.0, BL = 4 Applied to same bank)
CLK
CLK
BL × tCK + lRP (See note)
2
IRAS (Min.)
Command
ACTV
READA
IRCD (Min.)
DQS (Output)
IRP (Min.)
ACTV
CAS Latency
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Q1
Q2
Q3
Q4
Note: Internal precharge operation at Read with Auto-precharge command (READA) is started BL/2
clock later from READA command.
If BL=2, the READA command should not be issued no earlier than 1 clock (BL/2 = 1) before
lRAS (Min.).
If BL=4, the READA command should not be issued no earlier than 2 clock (BL/2=2) before lRAS
(Min.).
TIMING DIAGRAM - 7: WRITE WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2.0, BL = 4 Applied to same bank)
CLK
CLK
IWAL (Min.)
IRAS (Min.) (See note)
Command
ACTV
WRITA
IRCD (Min.)
DQS (Input)
ACTV
tDQSS
Hi-Z
DQ0 to DQ31 Hi-Z
(Input)
D1
D2
D3
D4
Note: Write with Auto-precharge command (WRITA) must be issued after lRCD is satisfied and be
considered to meet lRAS requirement applied to end of burst length (BL) regardless of where it is
masked or not.
45
MB81P643287-50/-60
TIMING DIAGRAM - 8: READ INTERRUPTED BY PRECHARGE
(EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
Command
READ
PRE
NOP
IROH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Command
Q1
READ
NOP
Q2
PRE
NOP
IROH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Command
Q1
READ
NOP
Q2
Q3
Q4
PRE
NOP
IROH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Command
Q1
READ
Q2
Q3
NOP
Q4
Q5
Q6
PRE
NOP
No effect (End of Burst)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Note: lROH is the same as CAS Latency (CL). In case of CL =3, the lROH is 3 clock.
46
MB81P643287-50/-60
TIMING DIAGRAM - 9: READ INTERRUPTED BY BURST STOP
(EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
Command
READ
BST
NOP
IBSH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Command
Q1
READ
NOP
Q2
BST
NOP
IBSH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Command
Q1
READ
NOP
Q2
Q3
Q4
BST
NOP
IBSH ( = CAS Latency)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Command
Q1
READ
Q2
Q3
NOP
Q4
Q5
Q6
BST
NOP
No effect (End of Burst)
DQS (Output)
Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Note: lBSH is the same as CAS Latency (CL). In case of CL =3, the lBSH is 3 clock.
47
MB81P643287-50/-60
TIMING DIAGRAM - 10: WRITE INTERRUPTED BY PRECHARGE (EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
IRP (Min.)
Command
WRIT
NOP
tDQSS
DQS (Iutput)
PRE
NOP
ACTV
IDPL(Min.)
Don't Care
Don't Care
See Note 1.
DM
Don't Care
DQ0 to DQ31
(Input)
Don't Care
Don't Care
D1

D2



Don't Care
See Note 2.
Note: 1. DQS Input are not required from when Precharge command is issued.
2. This pair of write data must be masked prior to Precharge command.
TIMING DIAGRAM - 11: READ TO WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
CLK
IRWD (Min.)
Command
READ
NOP
CL
DQS
tDQSS
Hi-Z
DM
DQ0 to DQ31
NOP
WRIT
Don't Care
Hi-Z
Q1
Q2
Q3
Q4
D1
D2
D3
D4
I/O open for bus turn-around
Note: lRWD defines a minimum delay from Read to Write command input applied to the same bank.
48
MB81P643287-50/-60
TIMING DIAGRAM - 12: READ TO WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
CLK
lBSNC
Command
READ
BST
NOP
lBSH
DQS
tDQSS
Hi-Z
DM
DQ0 to DQ31
NOP
WRIT
Don't Care
Hi-Z
Q1
Q2
D1
D2
D3
D4
Terminated
Note: DM are latched by DQS Input after Write command together with data Input.
TIMING DIAGRAM - 13: WRITE TO READ (EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
Command
WRIT
tDQSS
DQS
READ
NOP
NOP
CL
lWRD
Hi-Z
DM
Don't Care
Hi-Z
DQ0 to DQ31
D1
D2
Q1
Masked
Q2
Terminated by Read
Note: Read command must be issued after lWRD is satisfied and proceeding pair of data must be masked.
49
MB81P643287-50/-60
TIMING DIAGRAM - 14: READ WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 4, Multiple Bank Operation)
CLK
CLK
BL × tCK + lRP
2
lRP (Min.)
Command
READA
PRE
lCBD
BA0, BA1
Bank 0
READA
lCBD
lRCD (Min.)
READA
lCBD
Bank 1
Bank 2
ACTV
ACTV
lCBD
Bank 3
lRRD (Min.)
READ
lCBD
Bank 0
Bank 1
Bank 1
CAS Latency
DQS (Output)
DQ0 to DQ31
(Output)
Hi-Z
Hi-Z
Q1
Q2
Q3
Q4
Q1
Q2
Q1
Q2
Q3
Q4
Note: Back to back Read with Auto-precharge (READA) command to the different bank in active state
is possible. However, any new command to the same bank applied READA command can only
be issued after (BL/2) × tCK+lRP.
TIMING DIAGRAM - 15: WRITE WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 4, Multiple Bank Operation)
CLK
CLK
lRP (Min.)
lWAL (Min.)
Command
WRITA
WRITA
lCBD (Min.)
BA0, BA1
Bank 0
PRE
lCBD (Min.)
Bank 1
WRITA
lCBD (Min.)
Bank 2
ACTV
ACTV
lRRD (Min.)
Bank 3
Bank 2
Bank 0
tDQSS
tDQSS
tDQSS
DQS (Input)
DQ0 to DQ31
(Input)
D1
D2
D1
D2
D3
D4
D1
D2
D3
D4
Note: Back to back Write with Auto-precharge (WRITA) command to the different bank in active state
is possible. However, any new command to the same bank applied WRITA command can only
be issued after lWAL.
50
MB81P643287-50/-60
TIMING DIAGRAM - 16: AUTO-REFRESH ENTRY AND EXIT
CLK
CLK
IRFC (Min.)
Command
REF
NOP
Any
TIMING DIAGRAM - 17: SELF-REFRESH ENTRY AND EXIT
IRFC (Min.)
CKE
tQCKEH
tIS
tPDEX
IXSNR or ISCD *
CLK
CLK
Command
NOP
NOP
NOP
ACTV
Hi-Z
DQS (Output)
DQ0 to DQ31
(Output)
Don't Care
SELF
Q
Hi-Z
Last Data Output
Note * :CKE must maintain High level and stable clock must be provided during the lSCD period.
After Self-refresh exit, lXSNR must be satisfied for at least specified period before any command
(except for read) input.
TIMING DIAGRAM - 18: MODE REGISTER SET
CLK
CLK
IMRD
Command
NOP
MRS
NOP
Any
Note: MRS command must be issued after the last data is appeared on each DQ.
51
MB81P643287-50/-60
■ SCITT TEST MODE
ABOUT SCITT
SCITT (Static Component Interconnection Test Technology) is an XNOR circuit based test technology that is
used for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT
provides inexpensive board level test mode in combination with boundary-scan. The basic idea is simple, consider
all output of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of
SDRAM. The ideal schematic block diagram is as shown below.
TEST
Control
Boundary
Scan
ASIC
SDRAM Controller
µC
SDRAM
CORE
xAddress
Bus
XNOR
Data Bus
TEST Control : CAS, CS, CKE
xAddress Bus : A0 to A10, BA0 to BA2, RAS, DM0 to DM3, CLK, CLK, WE
Data Bus
: DQ0 to DQ31, DQS0 to DQS3
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short
faults.
52
MB81P643287-50/-60
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in“■ FUNCTION DESCRIPTION POWER-UP INITIALIZATION”. Once Precharge command is issued
to SDRAM, it never get back to SCITT Test Mode during regular operation unless reset power supply for the
purpose of a fail-safe way in get in and out of test mode.
Maintain all input signals (except CLK,CLK) to be Low state (or at least CKE to be Low) and maintain
CLK and CLK to be complementary state.
2. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins.
3. Apply VDD voltage to all VDDQ pins before or at the same time as VREF and VTT.
4. Apply VREF and VTT (VTT is applied to the system).
5. Maintain stable power for a minimum of 100µs.
6. Enter SCITT test mode.
7. Execute SCITT test.
8. Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
9. Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200µs.
10. After the minimum of 200µs stable power and clock, apply NOP condition and take CKE to be High
state.
11. Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every
banks.
12. Issue EMRS to enable DLL, DE = Low.
13. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lPCD*1
period is required to lock the DLL.
14. Apply minimum of two Auto-refresh command (REF).*2
15. Program the mode register by Mode Register Set command (MRS) with DR = Low.*2
The 6,7,8 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to “■ FUNCTION DESCRIPTION POWER-UP INITIALIZATION”).
1.
Notes: *1. The lPCD depends on operating clock period. The lPCD is counted from “DLL Reset” at step-13 to any
command input at step-15.
*2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
53
MB81P643287-50/-60
COMMAND TRUTH TABLE Note *1
Control
CAS
SCITT mode entry H→L *2
SCITT mode exit
SCITT mode
output enable *4
Output
CS
CKE
WE
RAS
A0 to A10,
BA0 to BA2
DM0
to
DM3
L
L
X
X
X
X
L *5
X
X
X
H
V
V
V
L→H *3 H *5
L
Input
L
DQ0
to
DQ31
DQS0
to
DQS3
X
X
X
X
X
V
V
V
CLK
CLK
H
L
L
H
X
X
V
V
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H
*2. The SCITT mode entry command assumes the first CAS falling edge with CS = CKE = L and CLK,CLK
signals are complementary after power on.
*3. The SCITT mode exit command assumes the first CAS rising edge after the test mode entry.
*4. Refer the test code table.
*5. CS = H or CKE = L is necessary to disable outputs in SCITT mode exit.
54
MB81P643287-50/-60
TEST CODE TABLE
DQ0 to DQ31 and DQS0 to DQS3 output data is static and is determined by following logic during the SCITT mode
operation.
DQ0 = RAS xnor A0
DQ1 = RAS xnor A1
DQ2 = RAS xnor A2
DQ3 = RAS xnor A3
DQ4 = RAS xnor A4
DQ5 = RAS xnor A5
DQ6 = RAS xnor A6
DQ7 = RAS xnor A7
DQ8 = RAS xnor A8
DQ9 = RAS xnor A9
DQ10 = RAS xnor A10
DQ11 = RAS xnor BA1
DQ12 = RAS xnor BA0
DQ13 = RAS xnor BA2
DQ14 = RAS xnor DM0
DQ15 = RAS xnor DM1
DQ16 = RAS xnor DM2
DQ17 = RAS xnor DM3
DQ18 = RAS xnor CLK
DQ19 = RAS xnor CLK
DQ20 = RAS xnor WE
DQ21 = A0 xnor A1
DQ22 = A0 xnor A2
DQ23 = A0 xnor A3
DQ24 = A0 xnor A4
DQ25 = A0 xnor A5
DQ26 = A0 xnor A6
DQ27 = A0 xnor A7
DQ28 = A0 xnor A8
DQ29 = A0 xnor A9
DQ30 = A0 xnor A10
DQ31 = A0 xnor BA0
DQS0 = A0 xnor BA1
DQS1 = A0 xnor BA2
DQS2 = A0 xnor DM0
DQS3 = A0 xnor DM1
• EXAMPLE OF TEST CODE TABLE
Output bus
RAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
BA0
BA1
BA2
DM0
DM1
DM2
DM3
CLK
CLK
WE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS0
DQS1
DQS2
DQS3
Input bus
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
L L L L L L L L L L L L L L L L L L L L L HHHHHHHHHHHHHHH
L HHHHHHHHHHHHHHHHHHHHL L L L L L L L L L L L L L L
HL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHH
HHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHH
HHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHH
HHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHH
HHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHH
HHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHH
HHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHH
HHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHH
HHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHH
HHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHH
HHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHH
HHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHH
HHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HH
HHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL H
HHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL
HHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHH
L L L L L L L L L L L L L L L L L L L L L HHHHHHHHHHHHHHH
L HHHHHHHHHHHHHHHHHHHHL L L L L L L L L L L L L L L
HL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHH
HHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHH
HHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHH
HHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHH
HHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHHH
HHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHHH
HHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHHH
HHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHHH
HHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHHH
HHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHHH
HHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHHH
HHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HHH
HHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL HH
HHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL H
HHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHHL
HHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHL HHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
0 = input Low, 1 = input High, L = output Low, H = output High
55
MB81P643287-50/-60
AC SPECIFICATION
Parameter
56
Description
Min.
Max.
Units
tTS
Test mode entry set up time
10
—
ns
tTH
Test mode entry hold time
10
—
ns
tEPD
Test mode exit to power on sequence delay time
10
—
ns
tTLZ
CS, CKE to output in Low-Z time
0
—
ns
tTHZ
CS, CKE to output in High-Z time
0
20
ns
tTCA
Test mode access time from control signals
(clock enable & chip select)
—
40
ns
tTIA
Test mode Input access time
—
20
ns
tTOH
Test mode Output Hold time
0
—
ns
tETD
Test mode entry to test delay time
10
—
ns
tTIH
Test mode input hold time
30
—
ns
MB81P643287-50/-60
TIMING DIAGRAMS
TIMING DIAGRAM - 1: POWER-UP TIMING DIAGRAM
VDD
100 µs Pause Time
Test Mode Entry Point
CS
CKE
CAS
*3
tETD
*1
CLK
CLK
or
CLK
CLK
*2
Notes: *1. CAS shall be staid either High or Low at power on.
*2 . All output buffers maintains in High-Z state regardless of the state of control signals except
for CAS as long as the above timing is maintained.
*3. CAS must not be brought from High to Low.
57
MB81P643287-50/-60
TIMING DIAGRAM - 2 : SCITT TEST ENTRY AND EXIT *1
Next power on sequence
and normal operation
VCC
Pause 100 µs
tTS
tTH
CAS
H
CS
L
PD
L
Test Mode
tEPD
L
*3
tETD
CLK
CLK
or
CLK
CLK
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS, CS, CKE pins will have some
problems.
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS = H or CKE = L before Exit.
58
MB81P643287-50/-60
TIMING DIAGRAM - 3: OUTPUT CONTROL (1)
VDD
Entry
CAS must not brought from High to Low
CAS
DQ turn to High-Z at CS = H
DQ turn to Low-Z at CS = L and CKE = H
CS
CKE
High-Z
DQ0 to DQ31
DQS0 to DQS3
tTLZ
High-Z
Memory device
output buffer status
Time (a)
Low-Z
tTHZ
Time (b)
High-Z
Time (c)
This is not bus line level
TIMING DIAGRAM - 4: OUTPUT CONTROL (2)
VDD
Entry
CAS must not brought from High to Low
CAS
DQ turn to Low-Z at CS = L and CKE = H
CS
DQ turn to High-Z at CKE = L
CKE
High-Z
DQ0 to DQ31
DQS0 to DQS3
Memory device
output buffer status
High-Z
Time (a)
tTLZ
Low-Z
Time (b)
tTHZ
High-Z
Time (c)
This is not bus line level
59
MB81P643287-50/-60
TIMING DIAGRAM - 5: TEST TIMING (1)
Test mode
Entry Command
Test mode
Entry
Under test
tETD
CAS
CS
DQ becomes Low-Z at CS = L and CKE = H
CKE
A0
tTCA
Under
Check
Pins
A1
tTIA
tTIA
tTIA
A2
tTOH
DQ0 to DQ31
DQS0 to DQS3
Valid
tTLZ
60
tTOH
Valid
Valid
MB81P643287-50/-60
TIMING DIAGRAM - 6: TEST TIMING (2)
Test mode
Entry
CAS
Test mode
Exit
Under test
L
CS-#1
L
Changed under test devices
H
CS-#2
Tested #2 device
Tested #1 device
CKE
tTIH
tTIH
tTIH
tTCA
A0
tTLZ
Under
Check
Pins
tTHZ
A1
tTIA
tTIA
tTIA
tTIA
tTIA
A2
tTOH
DQ0 to DQ31
DQS0 to DQS3
Valid
tTOH
Valid
tTOH
Valid
Valid
Valid
61
MB81P643287-50/-60
TIMING DIAGRAM - 7: TEST TIMING (3)
Test mode
Entry
CAS
Test mode
Exit
Under test
L
CS-#1
L
Changed under test devices
H
CS-#2
Tested #2 device
Tested #1 device
CKE
tTIH
tTIH
tTHZ
tTIH
A0
Under
Check
Pins
tTCA
A1
tTIA
tTIA
tTIA
tTLZ
tTIA
tTIA
A2
tTOH
DQ0 to DQ31
DQS0 to DQS3
62
Valid
tTOH
Valid
tTOH
Valid
Valid
Valid
MB81P643287-50/-60
■ ORDERING INFORMATION
Part number
MB81P643287-50FN
MB81P643287-60FN
Package
Remarks
86-pin plastic TSOP(II)
(FPT-86P-M01)

63
MB81P643287-50/-60
■ PACKAGE DIMENSIONS
86-pin plastic TSOP (II)
(FPT-86P-M01)
*: Resin protrusion.(Each side: 0.15 (.006) Max.)
86
44
Details of "A" part
0.25(.010)
INDEX
0~8°
LEAD No.
0.45/0.75
(.018/.030)
43
1
* 22.22±0.10(.875±.004)
0.22
.009
+0.05
–0.04
+.002
–.002
0.10(.004)
11.76±0.20(.463±.008)
1.20(.047)MAX
(Mounting height)
M
10.16±0.10(.400±.004)
+0.05
0.145 –0.03
+.002
.006 –.001
0.50(.020)TYP
0.10(.004)
21.00(.827)REF
C
0.10±0.05
(.004±.002)
(STAND OFF)
"A"
1996 FUJITSU LIMITED F86001S-1C-1
Dimensions in mm (inches).
MB81P643287-50/-60
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
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Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://www.fujitsu.co.jp/
North and South America
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3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
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1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0010
 FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
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CAUTION:
Customers considering the use of our products in special
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where extremely high levels of reliability are demanded (such as
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are requested to consult with FUJITSU sales representatives before
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Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
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