Preliminary Technical Data True Bipolar Input, Dual 1μs, 14-Bit, 2-Channel SAR ADC AD7367 FEATURES Dual 14-bit, 2-channel ADC True Bipolar Analog Inputs Programmable Input Ranges ±10, ±5, 0 to 10 V Throughput rate: 1 MSPS Simultaneous conversion with read in 1μs Specified for VCC of 5 V±5% Low current consumption: 5.65 mA max Wide input bandwidth 14 bits No Missing Codes On-chip reference: 2.5 V –40°C to +85°C operation High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP compatible iCMOSTM Process Technology 24-lead TSSOP package For 12 bit version see AD7366 FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The AD73671 is a dual, 14-bit, high speed, low power, successive approximation ADC that features throughput rates up to 1 MSPS. The device contains two ADCs, each preceded by a 2channel multiplexer, and a low noise, wide bandwidth trackand-hold amplifier that can handle input frequencies in excess of 10 MHz. The AD7367 is fabricated on Analog Devices’ Industrial CMOS process, iCMOS, a technology platform combining the advantages of low and high voltage CMOS, bipolar and high voltage DMOS processes. The process allows the AD7367 to accept high voltage bipolar signals in addition to reducing power consumption and package size. The AD7367 can accept true bipolar analog input signals in the ±10 V range, ±5 V range and 0 to 10 V range. Figure 1 Table 1.Related Products Device Number Resolution Throughput Rate Number of Channels AD7366 12-Bit 1 MSPS Dual, 2-ch AD7366-5 12-Bit 500 KSPS Dual, 2-ch AD7367-5 14-Bit 500 KSPS Dual, 2-ch The AD7367 has an on-chip 2.5 V reference that can be overdriven if an external reference is preferred. The AD7367 is available in a 24-lead TSSOP package. 1 Protected by U.S. Patent No. 6,681,332. iCMOSTM Process Technology For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30V and operating at +/- 15V supplies while allowing dramatic reductions in power consumption and package size, and increased AC and DC performance. Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD7367 Preliminary Technical Data TABLE OF CONTENTS FEATURES ........................................................................................ 1 Analog Inputs ............................................................................. 11 GENERAL DESCRIPTION ............................................................ 1 VDRIVE ............................................................................................ 12 FUNCTIONAL BLOCK DIAGRAM............................................. 1 Reference ..................................................................................... 12 Revision History ............................................................................... 2 Modes of Operation ....................................................................... 12 Specifications..................................................................................... 3 NORMAL MODE ...................................................................... 12 Timing Specifications .................................................................. 5 Shut-down Mode........................................................................ 12 Absolute Maximum Ratings............................................................ 6 POWER-UP TIMES................................................................... 12 ESD Caution.................................................................................. 6 Serial Interface ................................................................................ 12 Pin Configuration and Function Descriptions............................. 7 Outline Dimensions ....................................................................... 12 Terminology ...................................................................................... 9 Ordering Guide............................................................................... 12 Theory of operation ................................................................... 10 REVISION HISTORY 4/06—PRA: Initial Version 5/06—PRA changes to PRB: Initial Version 10/06—PRB changes to PRC: Modified Supply specifications Rev. PrD | Page 2 of 16 AD7367 Preliminary Technical Data SPECIFICATIONS AVCC = DVCC =4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = −11.5 V to −16.5 V, VDRIVE = 2.7 V to 5.25V, fSAMPLE = 1MSPS, fSCLK = 48MHz, VREF = 2.5 V Internal/External; TA = TMIN to TMAX, unless otherwise noted1. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)2 Signal-to-Noise + Distortion Ratio (SINAD)2 Total Harmonic Distortion (THD) 2 Spurious Free Dynamic Range (SFDR) 2 Intermodulation Distortion (IMD) 2 Second Order Terms Third Order Terms Channel-to-Channel Isolation2 SAMPLE AND HOLD Aperture Delay3 Aperture Jitter3 Aperture Delay Matching3 Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity2 Differential Nonlinearity2 Positive Full Scale Error2 Positive Full Scale Error Match2 Zero Code Error2 Zero Code Error Match2 Negative Full Scale Error2 Negative Full Scale Error Match2 ANALOG INPUT Input Voltage Ranges Min Typ TDB TBD 79 78 -85 -85 Input impedance Unit Test Conditions/ Comments fIN = 50 kHz sine wave; dB dB TBD TBD dB dB fa = 49 kHz, fb = 51 kHz -91 -89 -88 dB dB dB 10 40 100 65 15 14 ±2 ±0.99 ±5 ±0.5 ±1 ±1 ±5 ±0.5 (Programmed via RANGE Pins) DC Leakage Current Input Capacitance Max ns ps ps MHz MHz Bits LSB LSB LSB LSB LSB LSB LSB LSB ±10 V ±5 V 0 to 10V V ±1 µA p pF pF KΩ MΩ KΩ MΩ 12 15 3 260 2.3 125 1.1 Rev. PrD | Page 3 of 16 @ 3 dB, ±10 V range @ 0.1 dB, ±10 V range Guaranteed no missed codes to 14 bits VDD = +11.5V min, VSS = −11.5V min, VCC = 4.75V to 5.25V VDD = +11.5V min, VSS = −11.5V min, VCC = 4.75V to 5.25V VDD = +11.5V min, VSS = -11.5V min, VCC = 4.75V to 5.25V See Table 6. When in track, ±10 V range When in track, ±5 V or 0 to 10 V range When in hold For ±10V @1 Msps For ±10V @100 Ksps For ±5 / 0-10V @1 Msps For ±5 / 0-10V @100Ksps AD7367 Parameter REFERENCE INPUT/OUTPUT Reference Output Voltage4 Reference Input Voltage Range DC Leakage Current Input Capacitance VREFA, VREFB Output Impedance Reference Temperature Coefficient VREF Noise LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating State Leakage Current Floating State Output Capacitance3 CONVERSION RATE Conversion Time Track/Hold Acquisition Time3 Throughput Rate Preliminary Technical Data Min Typ 2.5 +2.5 25 10 10 20 Max Unit Test Conditions/ Comments 2.5 3.0 ±1 V V µA ±0.2% max @ 25°C 20 0.7× VDRIVE V min V max µA max pF typ 0.4 ±1 V V µA pF VDRIVE − 0.2 10 4.75 +11.5 -16.5 2.7 VIN = 0 V or VDRIVE 680 140 1 ns ns MSPS KSPS 5.25 +16.5 -11.5 5.25 V V V V 250 50 1.8 µA µA mA 925 725 4 µA µA mA VDD = +16.5 V VSS = −16.5 V VCC = 5.5 V fs = 1 MSPS VDD = +16.5 V VSS = −16.5 V VCC = 5.25 V, internal reference enabled 1 1 1 µA µA µA VDD = +16.5 V VSS = −16.5 V VCC = 5.25 V 48.23 15 38.25 mW µW µW VDD = +16.5V, VSS = −16.5V, VCC = 5.25V VDD = +5V, VSS = −5V, VCC = 5V VDD = +16.5V, VSS = −16.5V, VCC = 5.25 900 POWER REQUIREMENTS VCC VDD VSS VDRIVE Normal Mode (Static) IDD ISS ICC Normal Mode (Operational) IDD ISS ICC Shut-Down Mode IDD ISS ICC Power Dissipation Normal Mode (Operational) Shut-Down Shut-Down pF Ω ppm/°C µVRMS 0.8 ±1 5 External reference applied to Pin VREFA/Pin VREFB 1 Temperature range is −40°C to +85°C See Terminology section. Sample tested during initial release to ensure compliance. 4 Refers to pins VREFA or VREFB. 2 3 Rev. PrD | Page 4 of 16 Full-scale step input; For 4.75V≤VDRIVE≤5.25V, fSCLK = 48MHz For 2.7V≤VDRIVE<4.75V , fSCLK = 35MHz Digital I/Ps = 0 V or VDRIVE See Table 6 See Table 6 See Table 6 AD7367 Preliminary Technical Data TIMING SPECIFICATIONS AVCC = DVCC =4.75 V to 5.25 V, VDD = 11.5V to 16.5 V, VSS = −11.5V to −16.5 V, VDRIVE = 2.7 V to 5.25V, TA = TMIN to TMAX, unless otherwise noted1. Table 3. Limit at TMIN , TMAX Parameter Unit Test Conditions / Comments ns max Conversion time, Internal clock. CONVST falling edge to BUSY falling edge Frequency of serial read clock. 2.7V≤VDRIVE<4.75V 680 4.75V≤VDRIVE≤5.25V 680 fSCLK 10 35 10 48 tQUIET 30 30 kHz min MHz max ns min t1 t2 t3 10 5 0 10 5 0 ns min ns min ns min t4 10 10 ns max t52 t6 t7 t8 t9 t10 20 5 0.1 tSCLK 0.1 tSCLK 10 5 10 70 14 5 0.1 tSCLK 0.1 tSCLK 10 5 10 70 ns max ns min ns min ns min ns max ns min ns max μs tCONVERT tPOWER-UP Minimum quiet time required between end of serial read and start of next conversion Minimum CONVST Low pulse. CONVST falling edge to BUSY rising edge. BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going Low Delay from CS falling edge until DOUTA and DOUTB are three-state disabled Data access time after SCLK falling edge SCLK to data valid hold time SCLK low pulse width SCLK high pulse width CS rising edge to DOUTA, DOUTB, high impedance SCLK falling edge to DOUTA, DOUTB, high impedance SCLK falling edge to DOUTA, DOUTB, high impedance Power up time from shutdown mode. Time required between CONVST rising edge and CONVST falling edge. 1 Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See Terminology section and Figure 9. 2 The time required for the output to cross 0.4 V or 2.4 V. Rev. PrD | Page 5 of 16 AD7367 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 4 Parameter VDD to AGND, DGND VSS to AGND, DGND VDRIVE to DGND VDD to AVcc AVCC to AGND, DGND DVCC to AVCC DVCC to DGND VDRIVE to AGND AGND to DGND Analog Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to GND VREFA, VREFB input to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package θJA Thermal Impedance θJC Thermal Impedance Pb-free Temperature, Soldering Reflow ESD 1 Rating −0.3 V to +16.5 V −0.3 V to +16.5 V −0.3 V to DVDD Vcc – 0.3V to +16.5V -0.3V to +7V -0.3 V to + 0.3V -0.3 V to + 7V −0.3 V to DVCC −0.3 V to +0.3 V VSS −0.3 V to VDD + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to AVCC + 0.3 V ±10 mA −40°C to +85°C −65°C to +150°C 150°C 128°C/W 42°C/W 260(+0)°C TBD kV Transient currents of up to 100 mA will not cause latch up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrD | Page 6 of 16 Preliminary Technical Data AD7367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DOUTA 24 DGND 1 VDRIVE 2 23 DVCC 3 RANGE1 4 RANGE0 5 ADDR 6 AGND AVCC DOUTB 22 BUSY 21 CNVST AD7367 20 SCLK TOP VIEW 19 CS (Not to Scale) 18 REFSEL 7 8 DCAP A 9 VSS 10 17 AGND 16 DCAP B 15 VDD VA1 11 14 VA2 12 13 VB1 VB2 Figure 2 24-Lead RU-24. Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 23 DOUTA, DOUTB Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 14 SCLK cycles are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of the 14 bits of conversion data and is provided MSB first. If CS is held low for a further 14 SCLK cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or DOUTB using only one serial port. See the Serial Interface section. 2 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface will operate. This pin should be decoupled to DGND. The voltage range on this pin is 2.7V to 5.25V and may be different to that at AVCC and DVCC but should never exceed either by more than 0.3V To achieve a throughput rate of 1Msps VDRIVE must be greater than or equal to 4.75V 3 DVCC Digital Supply Voltage, 4.75V to 5.25V. The DVCC and AVCC voltages should ideally be at the same potential. For best performance it is recommended that DVCC and AVCC pins be shorted together, to ensure the voltage difference between them never exceed 0.3 V even on a transient basis. This supply should be decoupled to DGND. 10 µF and 100 nF decoupling capacitors should be placed on the DVCC pin. 4,5 RANGE0, RANGE1 Analog Input Range Selection. Logic inputs. The polarity on these pins determines the input range of the analog input channels. See Analog Inputs section and Table 7 for details 6 ADDR Multiplexer Select. Logic input. This input is used to select the pair of channels to be simultaneously converted, either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADCB. The logic state on this pin is latched on the rising edge of BUSY to set up the multiplexer for the next conversion. 7,17 AGND Analog Ground. Ground reference point for all analog circuitry on the AD7367. All analog input signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 8 AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages ideally should be at the same potential. For best performance it is recommended that DVCC and AVCC pins be shorted together, to ensure the voltage difference between them never exceed 0.3 V even on a transient basis. This supply should be decoupled to AGND. 10 µF and 100 nF decoupling capacitors should be placed on the AVCC pins. 9,16 DCAPA, DCAPB Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC. For best performance it is recommended to use 680nF decoupling capacitor on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and Rev. PrD | Page 7 of 16 AD7367 Preliminary Technical Data applied externally to the rest of a system. 10 VSS Negative power supply voltage. This is the negative supply voltage for the Analog Input section. The supply must be less than a maximum voltage of -11.5V for all input ranges. See Table 6 for further details. 10 µF and 100 nF decoupling capacitors should be placed on the VSS pin. 11,12 VA1, VA2 Analog Inputs of ADC A. These are both single-ended analog inputs. The Analog input range on these channels is determined by the RANGE0 and RANGE1 pins. 13,14 VB2, VB1 Analog Inputs of ADC B. These are both single-ended analog inputs. The Analog input range on these channels is determined by the RANGE0 and RANGE1 pins. 15 VDD Positive power supply voltage. This is the positive supply voltage for the Analog Input section. The supply must be greater than a minimum voltage of 11.5V for all the analog input ranges. See Table 6 for further details. 10 µF and 100 nF decoupling capacitors should be placed on the VDD pin. 18 REFSEL Internal/External Reference Selection. Logic input. If this pin is tied to a logic high, the on-chip 2.5 V reference is used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to decoupling capacitors. If the REF SELECT pin is tied to GND, an external reference can be supplied to the AD7367 through the DCAPA and/or DCAPB pins. 19 CS Chip Select. Active low logic input. This input frames the serial data transfer. When CS is logic low the output bus is enabled and the conversion result is output on DOUTA, and DOUTB. 20 SCLK Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7367. 21 CONVST Conversion Start. Edge triggered logic input. On the falling edge of this input the track/hold goes into hold mode and conversion is initiated. If CONVST is low at the end of a conversion, the part goes into powerdown mode. In this case, the rising edge of CONVST will instruct the part to power up again. 22 BUSY BUSY Output. Transitions high when a conversion is started and remains high until the conversion is complete. 24 DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7367. The DGND pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Rev. PrD | Page 8 of 16 Preliminary Technical Data AD7367 TERMINOLOGY Differential Nonlinearity Differential nonlinearity is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity Integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a single (1) LSB point below the first code transition and full scale, a point 1 LSB above the last code transition. Zero Code Error It is the deviation of the midscale transition (all 1s to all 0s) from the ideal VIN voltage, i.e., AGND – 1/2 LSB for bipolar ranges and 2×VREF−1LSB for the unipolar range. Positive Full Scale Error It is the deviation of the last code transition (011…110) to (011…111) from the ideal ( +4 × VREF - 1 LSB or + 2 x VREF – 1 LSB) after the Zero Code Error has been adjusted out. Negative Full Scale Error This is the deviation of the first code transition (10…000) to (10…001) from the ideal (i.e., - 4 x VREF + 1 LSB, - 2 x VREF + 1 LSB or AGND + 1LSB) after the Zero Code Error has been adjusted out. Zero Code Error Match This is the difference in zero code error across all 12 channels. Positive Full Scale Error Match This is the difference in positive full scale error across all channels. Negative Full Scale Error Match This is the difference in negative full-scale error across all channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns to track mode at the end of conversion. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion. Signal to (Noise + Distortion) Ratio This ratio is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02N + 1.76) dB Thus for a 12-bit converter, this is 74 dB. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. For the AD7367, it is defined as: THD (dB ) = 20 log V 2 2 + V3 2 + V 4 2 + V5 2 + V6 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic, or spurious noise, is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels when operating in the +/10 V Range. It is measured by applying a full-scale, 150 kHz sine wave signal to all unselected input channels and determining how much that signal is attenuated in the selected channel with a 50 kHz signal. The figure given is the worst-case across all four channels for the AD7367. See also Typical Performance Characteristics. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum, and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa − fb), while the third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and (fa − 2fb). The AD7367 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Rev. PrD | Page 9 of 16 AD7367 Preliminary Technical Data PSRR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the converter’s linearity. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see figure x). up the REFSEL pin must be tied to either a high or low logic state to select either the internal or external reference option. If the internal reference is the preferred option, the user must tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to GND then an external reference can be supplied to both ADC’s through DCAPA & DCAPB pins. THEORY OF OPERATION The analog inputs are configured as two single ended inputs for each ADC. The various different input voltage ranges can be selected by programming the RANGE bits as shown in Table 7. Circuit Information The AD7367 is a fast, dual, 2-Channel, 14-bit, Bipolar Input, Serial A/D converter. The AD7367 can accept bipolar input ranges of ±10V and ±5V. It can also accept a 0 to 10V unipolar input range. The AD7367 requires VDD and VSS dual supplies for the high voltage analog input structure. These supplies must be equal to or greater than 11.5V. See Table 6 for the minimum requirements on these supplies for each Analog Input Range. The AD7367 requires a low voltage 4.75V to 5.25 V VCC supply to power the ADC core. Table 6. Reference and Supply Requirements for each Analog Input Range Selected Analog Input Range (V) ±10 ±5 0 to 10 Reference Voltage (V) AVCC (V) Minimum VDD/VSS (V) 2.5 Full Scale Input Range(V) ±10 5 ±11.5 3.0 ±12 5 ±12 2.5 3.0 2.5 3.0 ±5 ±6 0 to 10 0 to 12 5 5 5 5 ±11.5 ±11.5 ±11.5 ±12 The AD7367 also features power-down option to allow power saving between conversions. The power-down feature is implemented via the CONVST pin as described in the Modes of Operation section. Converter Operation The AD7367 has two successive approximation analog-todigital converters, each based around two capacitive DACs. Figure 3 and Figure 4 show simplified schematics of one of these ADCs in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 3 (the acquisition phase), SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the signal on the input. CAPACITIVE DAC VIN A SW1 CONTROL LOGIC B SW2 COMPARATOR AGND The AD7367 contains two on-chip differential track-and-hold amplifiers, two successive approximation A/D converters, and a serial interface with two separate data output pins. It is housed in a 24-lead TSSOP package, offering the user considerable space-saving advantages over alternative solutions. The AD7367 requires a CONVST signal to start conversion. On the falling edge of CONVST both track-and-holds will be placed into hold mode and the conversions are initiated. The BUSY signal will go high to indicate the conversions are taking place. The clock source for each successive approximation ADC is provided by an internal oscillator. The BUSY signal will go low to indicate the end of conversion. On the falling edge of BUSY the trackand-hold will return to track mode. Once the conversion is finished, the serial clock input accesses data from the part. Figure 3 ADC Acquisition Phase When the ADC starts a conversion (Figure 4), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The AD7367 has an on-chip 2.5 V reference that can be overdriven when an external reference is preferred. If the internal reference is to be used elsewhere in a system, then the output from DCAPA & DCAPB must first be buffered. On Power Rev. PrD | Page 10 of 16 Preliminary Technical Data AD7367 CAPACITIVE DAC A VIN SW1 CONTROL LOGIC B SW2 COMPARATOR The AD7367 requires VDD and VSS dual supplies for the high voltage analog input structures. These supplies must be equal to or greater than ±11.5V. See Table 6 for the requirements on these supplies. The AD7367 requires a low voltage 4.75V to 5.25 V AVCC supply to power the ADC core, a 4.75V to 5.25V DVCC supply for the Digital Power and a 2.7V to 5.25V VDRIVE supply for the interface power. Channel selection is made via the ADDR pin as shown in AGND Figure 4 ADC Conversion Phase Table 8. The logic level on the ADDR pin is latched on the rising edge of BUSY for the next conversion, not the one in progress. When power is first supplied to the AD7367 the default channel selection will be VA1 and VB1. ANALOG INPUTS Each ADC in the AD7367 has two Single Ended Analog Inputs. Figure 5 shows the equivalent circuit of the analog input structure of the AD7367. The two diodes provide ESD protection. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes these diodes to become forward-biased and starts conducting current into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. Capacitor C1 in Figure 5 is typically 5 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the on resistance of the switches. The value of these resistors is typically about TBD Ω. Capacitor C2 is the ADC’s sampling capacitors with a capacitance of approximately TBD pF for the ±10V input range and approximately TBD pF for all other input ranges. ADDR Channels Selected 0 VA1, VB1 1 VA2, VB2 Transfer Function The AD7367 output coding is two’s complement. The designed code transitions occur at successive integer LSB values (i.e. 1 LSB, 2 lSB, and so on). The LSB size is dependant on the analog input range selected. Table 9 LSB sizes for each Analog Input Range. VDD R1 VIN0 04852-023 D C2 VSS Figure 5 Equivalent Analog Input Structure Input Range Full Scale Range/4096 LSB Size ±10 V 20 V/16384 1.22mV ±5 V 10 V/16384 0.61mV 0 to 10 V 10V/16384 0.61mV The ideal transfer characteristic is shown in Figure 6 The AD7367 can handle true bipolar input voltages. The Analog input can be set to one of three ranges; ±10V, ±5V, 0-10V. The logic levels on pins RANGE0 and RANGE1 determine which input range is selected as outlined in Table 7. These range bits should not be changed during the acquisition time prior to a conversion but may change at any other time. Table 7. Analog Input Range Selection RANGE1 RANGE0 Range Selected 0 0 ±10V 0 1 ±5V 011...111 011...110 ADC CODE D C1 Table 8. Channel Selection 000...001 000...000 111...111 100...010 100...001 100...000 -FSR/2 + 1LSB 0V +FSR/2 - 1LSB ANALOG INPUT 1 0 0 to 10V 1 1 Do not program Figure 6.Transfer Characteristic Rev. PrD | Page 11 of 16 AD7367 Preliminary Technical Data VDRIVE The AD7367 also has a VDRIVE feature to control the voltage at which the serial interface operates. VDRIVE allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7367 was operated with a VCC of 5 V, the VDRIVE pin could be powered from a 3 V supply, allowing a large dynamic range with low voltage digital processors. Thus, the AD7367 could be used with the ±10 V input range while still being able to interface to 3 V digital parts. To achieve the maximum throughput rate of 1Msps VDRIVE must be greater than or equal to 4.75V, see table 3. The maximum throughput rate for the AD7367 with the VDRIVE voltage set to less than 4.75 and greater than 2.7 is 900 Ksps. REFERENCE The AD7367 can operate with either the internal 2.5 V on-chip reference or an externally applied reference. The logic state of the REFSEL pin determines whether the internal reference is used. The internal reference is selected for both ADC when the REFSEL pin is tied to logic high. If the REFSEL pin is tied to GND then an external reference can be supplied through the DCAPA and DCAPB pins. On power-up, the REFSEL pin must be tied to either a low or high logic state for the part to operate. Suitable reference sources for the AD7367 include AD780, AD1582, ADR431, REF193, and ADR391. The internal reference circuitry consists of a 2.5 V band gap reference and a reference buffer. When operating the AD7367 in internal reference mode, the 2.5 V internal reference is available at DCAPA and DCAPB pins, which should be decoupled to AGND using a 680nF capacitor. It is recommended that the internal reference be buffered before applying it elsewhere in the system. The internal reference is capable of sourcing up to 150 μA with an analog input range of ±10 and 60 μA for both the ±5V and 0-10V ranges. If the internal reference operation is required for the ADC conversion, the REFSEL pin must be tied to logic high on power-up. The reference buffer requires 500 µs to power up and charge the 680nF decoupling capacitor during the power-up time. The AD7367 is specified for a 2.5 V to 3 V reference range. When a 3V reference is selected, the ranges are ±12 V, ±6 V, and 0 V to +12 V. For these ranges, the VDD and VSS supply must be equal to or greater than the +12V &-12V respectively. Rev. PrD | Page 12 of 16 AD7367 Preliminary Technical Data MODES OF OPERATION The mode of operation of the AD7367 is selected by the (logic) state of the CONVST signal at the end of a conversion. There are two possible modes of operation: normal mode and shut-down mode. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. NORMAL MODE the result from the other on chip ADC is also accessed on the same DOUT line, as shown in Figure 10(see the Serial Interface section) This mode is intended for applications needing fast throughput rates since the user does not have to worry about any power-up times with the AD7367 remaining fully powered at all times. Figure 7 shows the general mode of operation of the AD7367 in this mode. Once 28 SCLK cycles have elapsed, the DOUT line returns to three-state when CS is brought high and not on the 28th SCLK falling edge. If CS is brought high prior to this, the DOUT line returns to three-state at that point. Thus, CS must be brought high once the read is completed, as the bus does not automatically return to three-state upon completion of the dual result read. The conversion is initiated on the falling edge of CONVST as described in the Circuit Information section. To ensure that the part remains fully powered up at all times, CONVST must be at logic state high prior to the BUSY signal going low. If CONVST is at logic state low when the BUSY signal goes low, the analogue circuitry will power down and the part will cease converting. The BUSY signal remain high for the duration of the conversion subsequently fourteen serial clock cycles are required to read the conversion result. The DOUT lines return to three-state when CS is brought high and not after 14 SCLK cycles has elapsed. If CS is left low for a further 14 SCLK cycles, Once a data transfer is complete and DOUTA and DOUTB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CONVST low again. t1 CONVST BUSY tquiet t2 tconvert t3 CS SCLK SERIAL READ OPERATION 1 14 Figure 7. Normal Mode Operation SHUT-DOWN MODE This mode is intended for use in applications where slow throughput rates are required. This mode is suited to applications where a series of conversions performed at a relatively high throughput rate are followed by a long period of inactivity and thus, shut-down. When the AD7367 is in full power-down, all analog circuitry is powered down. As already stated, the falling edge of CONVST initiates the conversion. The BUSY output subsequently goes high to indicate that the conversion is in progress. Once the conversion is completed, the BUSY output returns low. If the CONVST signal is at logic low when BUSY goes low then the part will enter shut-down at the end of the conversion phase. While the part is in shut-down mode the digital output code from the last conversion on each ADC can still be read from the DOUT pins. To read the DOUT data CS must be brought low as described in the Serial Interface Section. The DOUT pins return to three-state once CS is brought back to logic high. To exit full power-down and power up the AD7367, A rising edge of CONVST is required. After the required power up time has elapsed, CONVST may be brought low again to initiate Rev. PrD | Page 13 of 16 AD7367 Preliminary Technical Data time section for power-up times associated with the AD7367. another conversion, as shown in Figure 8. See the Power up tpower-up ENTERS SHUT-DOWN CONVST BUSY t2 tconvert t3 CS SCLK SERIAL READ OPERATION 1 14 Figure 8. Auto-Shutdown Mode POWER-UP TIMES The AD7367 has one power down mode, which has already been described in detail. This section deals with the power-up time required when coming out of this modes. It should be noted that the power-up time, as explained in this section, applies with the recommended capacitors in place on the DCAPA and DCAPB pins. To power up from shut-down, CONVST must be brought high and remain high for a minimum of 100μs, as shown in Figure 8. When power supplies are first applied to the AD7367, the ADC may power up with CONVST in either the low or high logic state. Before attempting a valid conversion CONVST must be brought high and remain high for the recommended power up time of 100μs, it can then be brought low to initiate a conversion. With the AD7367 no dummy conversion is required before valid data can be read from the DOUT pins. If it is intended to place the part in shut-down mode when the supplies are first applied, then the AD7367 must be powered up as explained about and a conversion initiated, but CONVST should remain in the logic low state and when the BUSY signal goes low thus the part enters shut-down. Once supplies are applied to the AD7367, enough time must be allowed for any external reference to power up and charge the various reference buffer decoupling capacitors to their final values. Rev. PrD | Page 14 of 16 Preliminary Technical Data AD7367 SERIAL INTERFACE provided to AD7367 to access each conversion result. Figure 9 shows how a 14 SCLK read is used to access the conversion results. Figure 9 shows the detailed timing diagram for serial interfacing to the AD7367. On the falling edge of CONVST the AD7367 will simultaneously convert the selected channels. These conversions are performed using the on-chip oscillator. After the falling edge of CONVST the BUSY signal goes high, indicating the conversion has started. It returns low once the conversion has been completed. The data can now be read from the DOUT pins. On the rising edge of CS, the conversion will be terminated and DOUTA and DOUTB go back into three-state. If CS is not brought high, but is instead held low for a further 14 SCLK cycles on either DOUTA or DOUTB, the data from the other ADC follows on the DOUT pin. This is illustrated in Figure 10 where the case for DOUTA is shown. In this case, the DOUT line in use goes back into three-state on the rising edge of CS CS and SCLK signals are required to transfer data from the AD7367. The AD7367 has two output pins corresponding to each ADC. Data can be read from the AD7367 using both DOUTA & DOUTB, alternatively a single output pin of your choice can be used. The SCLK input signal provides the clock source for the serial interface. The CS goes low to access data from the AD7367. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the conversion result. The data stream consists of 14 bits of data MSB first. The first bit of the conversion result is valid on the first SCLK falling edge after the CS falling edge. The subsequent 13 bits of data are clocked out on the falling edge of the SCLK signal. A minimum of 14 Clock pulses must be If the falling edge of SCLK coincides with the falling edge of CS, then the falling edge of SCLK is not acknowledged by the AD7367, and the next falling edge of the SCLK will be the first registered after the falling edges of the CS. The CS pin can be brought low before the BUSY signal goes low indicating the end of a conversion. This feature can be utilized to ensure that the MSB is valid on the falling edge of BUSY by bring CS low a minimum of t4 nanoseconds before the BUSY signal goes low. The dotted CS line in Table 7 illustrates this. CS t8 SCLK 1 3 2 4 14 5 t7 DOUT A DOUT B 3-STATE DB12 DB11 t9 t6 t5 t4 DB10 DB2 DB1 DB0 3-STATE DB13 Figure 9. Serial Interface Timing diagram CS t8 2 1 3 4 5 12 14 13 28 15 t7 t4 DOUTA THREESTATE DB13 DB12 A t5 DB11A t10 t6 DB1A DB0A DB13 B DB12 B A Figure 10. Reading Data from Both ADC’s on ONE DOUT Line with 28 SCLK’s Rev. PrD | Page 15 of 16 DB1B DB0B THREESTATE 04603-035 SCLK AD7367 Preliminary Technical Data OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 11. Figure 12. 24-Lead TSSOP ORDERING GUIDE Model Temperature Range Package Description Package Option −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367ARUZ-REEL71 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367BRUZ1 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367BRUZ-REEL71 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367-5ARUZ1 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367-5ARUZ-REEL71 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367-5BRUZ1 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367-5BRUZ-REEL71 −40°C to +85°C Thin Shrink Small Outline Package RU-24 AD7367ARUZ 1 1 Z = Pb-free part. Rev. PrD | Page 16 of 16 PR06175-0-11/06(PrD)