a FEATURES Fast Throughput Rate: 1 MSPS Wide Input Bandwidth: 40 MHz Excellent DC Accuracy Performance Flexible Serial Interface Low Power: 80 mW (Full Power) and 3 mW (NAP Mode) STANDBY Mode: 2 A Max Single 5 V Supply Operation Internal 2.5 V Reference Full-Scale Overrange Indication 1 MSPS, Serial 14-Bit SAR ADC AD7485 FUNCTIONAL BLOCK DIAGRAM AVDD AGND CBIAS DVDD VDRIVE DGND 2.5 V REFERENCE BUF REFSEL VIN REFOUT REFIN 14-BIT ALGORITHMIC SAR T/H AD7485 GENERAL DESCRIPTION The AD7485 is a 14-bit, high speed, low power, successiveapproximation ADC. The part features a serial interface with throughput rates up to 1 MSPS. The part contains a low noise, wide bandwidth track-and-hold that can handle input frequencies in excess of 40 MHz. MCLK NAP STBY RESET CONTROL LOGIC AND I/O REGISTERS TFS SCO SDO CONVST SMODE The conversion process is a proprietary algorithmic successiveapproximation technique. The input signal is sampled and a conversion is initiated on the falling edge of the CONVST signal. The conversion process is controlled by an external master clock. Interfacing is via standard serial signal lines, making the part directly compatible with microcontrollers and DSPs. The AD7485 features an on-board 2.5 V reference, but the part can also accommodate an externally provided 2.5 V reference source. The nominal analog input range is 0 V to 2.5 V. The AD7485 provides excellent ac and dc performance specifications. Factory trimming ensures high dc accuracy resulting in very low INL, DNL, offset, and gain errors. The AD7485 also provides the user with overrange indication via a fifteenth bit. If the analog input range strays outside the 0 V to 2.5 V input range, the fifteenth data bit is set to a logic high. The part uses advanced design techniques to achieve very low power dissipation at high throughput rates. Power consumption in the normal mode of operation is 80 mW. There are two powersaving modes: a NAP mode keeps reference circuitry alive for quick power-up and consumes 3 mW, while a STANDBY mode reduces power consumption to a mere 10 µW. The AD7485 is powered from a 4.75 V to 5.25 V supply. The part also provides a VDRIVE pin that allows the user to set the voltage levels for the digital interface lines. The range for this VDRIVE pin is from 2.7 V to 5.25 V. The part is housed in a 48-lead LQFP package and is specified over a –40°C to +85°C temperature range. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 = 0 V, V = External, f = 1 MSPS; all specificafor V = 2.7 V to 5.25 V, unless otherwise noted.) AD7485–SPECIFICATIONS1 (Vtions=T5 VtoT5%,andAGNDvalid= DGND DD REF MIN Parameter MAX Specification Unit 76.5 78 77 –90 –95 –92 –88 dB min dB typ dB typ dB max dB typ dB typ dB max –96 –94 10 40 3.5 dB typ dB typ ns typ MHz typ MHz typ 14 ±1 ± 0.5 ± 0.75 ± 0.25 ±6 0.036 ±6 0.036 Bits LSB max LSB typ LSB max LSB typ LSB max %FSR max LSB max %FSR max 0 2.5 ±1 35 V min V max µA max pF typ REFERENCE INPUT/OUTPUT VREFIN Input Voltage VREFIN Input DC Leakage Current VREFIN Input Capacitance5 VREFIN Input Current6 VREFOUT Output Voltage VREFOUT Error @ 25°C VREFOUT Error TMIN to TMAX VREFOUT Output Impedance 2.5 ±1 25 220 2.5 ± 50 ± 100 1 V µA max pF typ A typ V typ mV typ mV max Ω typ LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN5 VDRIVE –1 0.4 ±1 10 V min V max µA max pF typ LOGIC OUTPUTS Output High Voltage, VOH7 Output Low Voltage, VOL7 Floating-State Leakage Current Floating-State Output Capacitance5 Output Coding 0.7 × VDRIVE V min 0.3 × VDRIVE V max ± 10 µA max 10 pF max Straight (Natural) Binary 2, 3 DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD)4 Total Harmonic Distortion (THD)4 Peak Harmonic or Spurious Noise (SFDR)4 Intermodulation Distortion (IMD)4 Second-Order Terms Third-Order Terms Aperture Delay Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity4 Differential Nonlinearity4 Offset Error4 Gain Error4 ANALOG INPUT Input Voltage DC Leakage Current Input Capacitance5 CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate SAMPLE DRIVE Test Conditions/Comments fIN = 500 kHz Sine Wave 24 100 70 1 MCLKs ns max ns max MSPS max –2– Internal Reference Internal Reference fIN1 = 95.053 kHz, fIN2 = 105.329 kHz @ 3 dB @ 0.1 dB Guaranteed No Missed Codes to 14 Bits ± 1% for Specified Performance External Reference Sine Wave Input Full-Scale Step Input REV. 0 AD7485 Parameter POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode (Static) Normal Mode (Operational) NAP Mode STANDBY Mode8 Power Dissipation Normal Mode (Operational) NAP Mode STANDBY Mode8 Specification Unit Test Conditions/Comments 5 2.7 5.25 V V min V max ± 5% 12 16 0.6 2 0.5 mA max mA max mA max µA max µA typ 80 3 10 mW max mW max µW max NOTES 1 Temperature ranges as follows: –40°C to +85°C. 2 SINAD figures quoted include external analog input circuit noise contribution of approximately 1 dB. 3 See Typical Performance Characteristics section for analog input circuits used. 4 See Terminology. 5 Sample tested @ 25°C to ensure compliance. 6 Current drawn from external reference during conversion. 7 ILOAD = 200 µA. 8 Digital input levels at GND or V DRIVE. Specifications subject to change without notice. TIMING CHARACTERISTICS1 (VDD = 5 V 5%, AGND = DGND = 0 V, VREF = External; all specifications TMIN to TMAX and valid for VDRIVE = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Symbol Min Master Clock Frequency MCLK Period Conversion Time CONVST Low Period (Mode 1)2 CONVST High Period (Mode 1)2 MCLK High Period MCLK Low Period CONVST Falling Edge to MCLK Rising Edge MCLK Rising Edge to MSB Valid Data Valid before SCO Falling Edge Data Valid after SCO Falling Edge CONVST Rising Edge to SDO Three-State CONVST Low Period (Mode 2)2 CONVST High Period (Mode 2)3 CONVST Falling Edge to TFS Falling Edge TFS Falling Edge to MSB Valid TFS Rising Edge to SDO Three-State TFS Low Period4 TFS High Period4 MCLK Fall Time MCLK Rise Time MCLK – SCO Delay fMCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 0.01 40 t1 24 t1 22 10 0.4 t1 0.4 t1 7 Typ Max Unit 25 100000 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.6 t1 0.6 t1 15 10 20 10 10 10 6 t1 2 30 8 t1 22 10 5 5 6 25 25 25 NOTES 1 All timing specifications given above are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. 2 CONVST idling high. See Serial Interface section for further details. 3 CONVST idling low. See Serial Interface section for further details. 4 TFS can also be tied low in this mode. Specifications subject to change without notice. REV. 0 –3– AD7485 JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 10°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog Input Voltage to GND . . . . . . –0.3 V to AVDD + 0.3 V Digital Input Voltage to GND . . . . . –0.3 V to VDRIVE + 0.3 V REFIN to GND . . . . . . . . . . . . . . . . –0.3 V to AVDD + 0.3 V Input Current to Any Pin except Supplies . . . . . . . . . ± 10 mA Operating Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Option AD7485BST –40°C to +85°C Low Profile Quad Flatpack ST-48 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7485 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE DGND DGND DGND CONVST SCO RESET DGND DGND DVDD AVDD AGND AGND PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 AVDD 1 CBIAS 2 36 SMODE PIN 1 IDENTIFIER 35 TFS AGND 3 34 DGND AGND 4 33 DGND AVDD 5 32 VDRIVE 31 DGND AD7485 AGND 6 TOP VIEW (Not to Scale) VIN 7 REFOUT 8 30 DGND 29 DVDD 28 DGND REFIN 9 REFSEL 10 27 DGND AGND 11 26 DGND AGND 12 25 DGND –4– DGND DGND DGND SDO DGND DGND MCLK NAP STBY AGND AVDD AGND 13 14 15 16 17 18 19 20 21 22 23 24 REV. 0 AD7485 PIN FUNCTION DESCRIPTIONS Pin No. 1, 5, 13, 46 2 Mnemonic AVDD CBIAS 3, 4, 6, 11, 12, 14, 15, 47, 48 7 8 VIN REFOUT 9 REFIN 10 REFSEL 16 STBY 17 NAP 18 MCLK 19, 20, 22–28 30, 31, 33, 34 37–39, 43, 44 21 DGND 29, 45 32 DVDD VDRIVE 35 TFS 36 SMODE 40 SCO 41 CONVST 42 RESET REV. 0 AGND SDO Description Positive Power Supply for Analog Circuitry Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND. Power Supply Ground for Analog Circuitry Analog Input. Single-ended analog input channel. Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor must be placed between this pin and AGND. Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external voltage reference source, the reference voltage should be applied to this pin. Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this pin to AGND. When using an external reference source, this pin should be connected directly to AGND. Standby Logic Input. When this pin is logic high, the device will be placed in STANDBY mode. See the Power Saving section for further details. Nap Logic Input. When this pin is logic high, the device will be placed in a very low power mode. See the Power Saving section for further details. Master Clock Input. This is the input for the master clock, which controls the conversion cycle. The frequency of this clock may be up to 25 MHz. Twenty-four clock cycles are required for each conversion. Ground Reference for Digital Circuitry Serial Data Output. The conversion data is latched out on this pin on the rising edge of SCO. It should be latched into the receiving serial port of the DSP on the falling edge of SCO. The overrange bit is latched out first, then 14 bits of data (MSB first) followed by a trailing zero. Positive Power Supply for Digital Circuitry Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface logic of the AD7485 will operate. Transmit Frame Sync Input. In Serial Mode 2, this pin acts as a framing signal for the serial data being clocked out on SDO. A falling edge on TFS brings SDO out of three-state and the data starts to get clocked out on the next rising edge of SCO. Serial Mode Input. A logic low on this pin selects Serial Mode 1 and a logic high selects Serial Mode 2. See the Serial Interface section for further details. Serial Clock Output. This clock is derived from MCLK and is used to latch conversion data from the device. See the Serial Interface section for further details. Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The input track/hold amplifier goes from track mode to hold mode and the conversion process commences. Reset Logic Input. A falling edge on this pin resets the internal state machine and terminates a conversion that may be in progress. Holding this pin low keeps the part in a reset state. –5– AD7485 TERMINOLOGY Integral Nonlinearity Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental. For the AD7485, it is defined as: 2 2 2 2 2 V2 + V3 + V4 + V5 + V6 THD (dB ) = 20 log V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through sixth harmonics. This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Offset Error This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB. Gain Error This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the offset error has been adjusted out. Intermodulation Distortion Track/Hold Acquisition Time With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa – fb), while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb). Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ±1/2 LSB, after the end of conversion (the point at which the track/hold returns to track mode). Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: The AD7485 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves while the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Signal to ( Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 14-bit converter this is 86.04 dB. –6– REV. 0 Typical Performance Characteristics–AD7485 –40 1.0 0.8 –50 0.6 100 –60 0.2 51 THD – dB DNL – LSB 0.4 0 –0.2 –70 10 –80 –0.4 0 –0.6 –90 –0.8 –1.0 –100 0 4096 8192 12288 1000 100 16384 10000 INPUT FREQUENCY – kHz ADC CODE TPC 1. Typical DNL TPC 4. THD vs. Input Tone for Different Input Resistances 1.0 0 100mV p-p SINE WAVE ON SUPPLY PINS 0.8 –10 0.6 –20 0.2 PSRR – dB INL – LSB 0.4 0 –0.2 –30 –40 –50 –0.4 –60 –0.6 –70 –0.8 –1.0 –80 0 4096 8192 12288 16384 100 10 ADC CODE 1000 FREQUENCY – kHz TPC 5. PSRR without Decoupling TPC 2. Typical INL 0.0004 80 0 –0.0004 SINAD – dB REFOUT – V 75 –0.0008 –0.0012 70 –0.0016 –0.0020 65 10 100 1000 –55 10000 TPC 3. SINAD vs. Input Tone (AD8021 Input Circuit) REV. 0 –25 5 35 65 TEMPERATURE – C INPUT FREQUENCY – kHz TPC 6. Reference Error –7– 95 125 AD7485 0 0 fIN = 10.7kHz SNR = 78.76dB SNR + D = 78.70dB THD = –97.10dB –20 fIN = 507.3kHz SNR = 78.35dB SNR + D = 78.33dB THD = –100.33dB –20 –40 –60 –60 dB dB –40 –80 –80 –100 –100 –120 –120 –140 –140 0 100 200 300 400 500 0 +VS 1k BIAS VOLTAGE 1k 3 + 2 – 7 VIN 6 AD829 4 5 1 –VS 220pF 150 Figure 1. Analog Input Circuit Used for 10 kHz Input Tone 50 BIAS VOLTAGE 220 8 2 7 + 6 AD8021 VIN 4 3 – 5 1 10pF 220 400 500 For higher input bandwidth applications, Analog Devices’ AD8021 op amp (also available as a dual AD8022) is the recommended choice to drive the AD7485. Figure 2 shows the analog input circuit used to obtain the data for the FFT plot shown in TPC 8. A bipolar analog signal is applied to the terminal shown and biased with a stable, low noise dc voltage connected as shown. A 10 pF compensation capacitor is connected between Pin 5 of the AD8021 and the negative supply. As with the previous circuit, the AD8021 is supplied with +12 V and –12 V supplies. The supply pins are decoupled as close to the device as possible with both a 0.1 µF and 10 µF capacitor connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two capacitors to the device. The AD8021 Logic Reference pin is tied to analog ground and the DISABLE pin is tied to the positive supply as shown. Detailed information on the AD8021 is available on the Analog Devices website. +VS AC SIGNAL 300 Figure 1 shows the analog input circuit used to obtain the data for the FFT plot shown in TPC 7. The circuit uses an Analog Devices AD829 op amp as the input buffer. A bipolar analog signal is applied as shown and biased up with a stable, low noise dc voltage connected to the labeled terminal shown. A 220 pF compensation capacitor is connected between Pin 5 of the AD829 and the analog ground plane. The AD829 is supplied with +12 V and –12 V supplies. The supply pins are decoupled as close to the device as possible, with both a 0.1 µF and 10 µF capacitor connected to each pin. In each case, the 0.1 µF capacitor should be the closer of the two capacitors to the device. More information on the AD829 is available on the Analog Devices website. 8 100 200 TPC 8. 64k FFT Plot with 500 kHz Input Tone TPC 7. 64k FFT Plot with 10 kHz Input Tone AC SIGNAL 100 FREQUENCY – kHz FREQUENCY – kHz –VS 10pF Figure 2. Analog Input Circuit Used for 500 kHz Input Tone –8– REV. 0 AD7485 CIRCUIT DESCRIPTION CONVERTER OPERATION CAPACITIVE DAC The AD7485 is a 14-bit algorithmic successive-approximation analog-to-digital converter based around a capacitive DAC. It provides the user with track-and-hold, reference, an A/D converter, and versatile interface logic functions on a single chip. The analog input signal range that the AD7485 can convert is 0 V to 2.5 V. The part requires a 2.5 V reference that can be provided from the part’s own internal reference or an external reference source. Figure 3 shows a very simplified schematic of the ADC. The Control Logic, SAR, and Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition. A VIN AGND Figure 5. ADC Acquisition Phase ADC TRANSFER FUNCTION The output coding of the AD7485 is straight binary. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size is V REF /16384. The nominal transfer characteristic for the AD7485 is shown in Figure 6. SWITCHES 111...111 111...110 CONTROL LOGIC ADC CODE SAR CONTROL INPUTS OUTPUT DATA 14-BIT SERIAL Figure 3. Simplified Block Diagram POWER SAVING The AD7485 uses advanced design techniques to achieve very low power dissipation at high throughput rates. In addition to this, the AD7485 features two power saving modes, NAP mode and STANDBY mode. These modes are selected by bringing either the NAP or STBY pin to a logic high. When operating the AD7485 with a 25 MHz MCLK in normal, fully powered mode, the current consumption is 16 mA during conversion and the quiescent current is 12 mA. Operating at a throughput rate of 500 kSPS, the conversion time of 960 ns contributes 38.4 mW to the overall power dissipation. (960 ns/2 s) × (5V × 16 mA) = 38.4 mW CONTROL LOGIC – For the remaining 1.04 µs of the cycle, the AD7485 dissipates 31.2 mW of power. COMPARATOR AGND (1.04 s/2 s) × (5V × 12 mA) = 31.2 mW Figure 4. ADC Conversion Phase Thus the power dissipated during each cycle is: At the end of conversion, track-and-hold returns to tracking mode and the acquisition time begins. The track/hold acquisition time is 70 ns. Figure 5 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN. REV. 0 +VREF –1.5LSB Figure 6. Transfer Characteristic + SW2 0.5LSB ANALOG INPUT A B 1LSB = V REF/16384 011...111 0V CAPACITIVE DAC VIN 111...000 000...010 000...001 000...000 Conversion is initiated on the AD7485 by pulsing the CONVST input. On the falling edge of CONVST, the track/hold goes from track to hold mode and the conversion sequence is started. Conversion time for the part is 24 MCLK periods. Figure 4 shows the ADC during conversion. When conversion starts, SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The ADC then runs through its successive approximation routine and brings the comparator back into a balanced condition. When the comparator is rebalanced, the conversion result is available in the SAR register. SW1 – COMPARATOR CAPACITIVE DAC VIN CONTROL LOGIC B SW2 COMPARATOR VREF + SW1 38.4 mW + 31.2 mW = 69.6 mW –9– AD7485 Figure 7 shows the AD7485 conversion sequence operating in normal mode. Figures 9 and 10 show a typical graphical representation of power versus throughput for the AD7485 when in normal and NAP modes, respectively. 2s 80 CONVST 78 76 READ DATA CONVERSION FINISHED 960ns 74 POWER – mW TFS 1.04s Figure 7. Normal Mode Power Dissipation In NAP mode, all the internal circuitry except for the internal reference is powered down. In this mode, the power dissipation of the AD7485 is reduced to 3 mW. When exiting NAP mode, a minimum of 300 ns when using an external reference must be waited before initiating a conversion. This is necessary to allow the internal circuitry to settle after power-up and for the track/hold to properly acquire the analog input signal. 68 66 64 62 60 0 100 200 300 400 500 600 700 800 900 1000 THROUGHPUT – kSPS If the AD7485 is put into NAP mode after each conversion, the average power dissipation will be reduced but the throughput rate will be limited by the power-up time. Using the AD7485 with a throughput rate of 100 kSPS while placing the part in NAP mode after each conversion would result in average power dissipation as follows: Figure 9. Normal Mode, Power vs. Throughput 50 45 40 The power-up phase contributes: 35 POWER – mW (300 ns/10 s) × (5V × 12 mA) = 1.8 mW The conversion phase contributes: (960 ns/10 s) × (5V × 16 mA) = 7.68 mW 5 0 300ns CONVST 50 100 150 200 250 300 350 400 450 500 Figure 10. NAP Mode, Power vs. Throughput 1.8 mW + 7.68 mW + 2.622 mW + 12.1 mW NAP 0 THROUGHPUT – kSPS Thus the power dissipated during each cycle is: 8.74s 20 10 (8.74 s/10 s) × (5V × 0.6 mA) = 2.622 mW Figure 8 shows the AD7485 conversion sequence if putting the part into NAP mode after each conversion. 30 25 15 While in NAP mode for the rest of the cycle, the AD7485 dissipates only 2.185 mW of power. 1.26s 72 70 In STANDBY mode, all the internal circuitry is powered down and the power consumption of the AD7485 is reduced to 10 µW. Because the internal reference has been powered down, the power-up time necessary before a conversion can be initiated is longer. If using the internal reference of the AD7485, the ADC must be brought out of STANDBY mode 500 ms before a conversion is initiated. Initiating a conversion before the required power-up time has elapsed will result in incorrect conversion data. If an external reference source is used and kept powered up while the AD7485 is in STANDBY mode, the power-up time required will be reduced to 80 µs. TFS 10s Figure 8. NAP Mode Power Dissipation –10– REV. 0 AD7485 SERIAL INTERFACE DIGITAL SUPPLY 4.75V–5.25V The AD7485 has two serial interface modes, selected by the state of the SMODE pin. In both these modes, the MCLK pin must be supplied with a clock signal of between 10 kHz and 25 MHz. This MCLK signal controls the internal conversion process and is also used to derive the SCO signal. As the AD7485 uses an algorithmic successive-approximation technique, 24 MCLK cycles are required to complete a conversion. Due to the error-correcting operation of this ADC, all bit trials must be completed before the conversion result is calculated. This results in a single sample delay in the result that is clocked out. In Serial Mode 1 (Figure 13), the CONVST pin is used to initiate the conversion and also frame the serial data. When CONVST is brought low, the SDO line is taken out of threestate, the overrange bit will be clocked out on the next rising edge of SCO followed by the 14 data bits (MSB first) and a trailing zero. CONVST must remain low for 22 SCO pulses to allow all the data to be clocked out and the conversion in progress to be completed. When CONVST returns to a logic high, the SDO line returns to three-state. TFS should be tied to ground in this mode. + + 10F 1nF 0.1F 47F 0.1F 0.1F ADM809 VDRIVE DVDD AVDD CBIAS RESET SMODE NAP STBY 1nF REFSEL AD780 2.5V REFERENCE REFIN 0.47F AD7485 C/P 25MHz XO CONVST TFS SCO SDO REFOUT MCLK 0.47F VIN 0V TO 2.5V Figure 11. Typical Connection Diagram Driving the CONVST Pin In Serial Mode 2 (Figure 14), the CONVST pin is used to initiate the conversion, but the TFS signal is used to frame the serial data. The CONVST signal can idle high or low in this mode. Idling high, the CONVST pulsewidth must be between 10 ns and two MCLK periods. Idling low, the CONVST pulsewidth must be at least 10 ns. TFS must remain low for a minimum of 22 SCO cycles in this mode but can also be tied permanently low. If TFS is tied low, the SDO line will always be driven. To achieve the specified performance from the AD7485, the CONVST pin must be driven from a low jitter source. Since the falling edge on the CONVST pin determines the sampling instant, any jitter that may exist on this edge will appear as noise when the analog input signal contains high frequency components. The relationship between the analog input frequency (fIN), timing jitter (tj), and resulting SNR is given by the equation below. SNRJITTER ( dB ) = 10 log The relationship between the MCLK and SCO signals is shown in Figure 15. Figure 11 shows a typical connection diagram for the AD7485. In this case, the MCLK signal is provided by a 25 MHz crystal oscillator module. It could also be provided by the second serial port of a DSP (e.g., ADSP-2189M) if one were available. In Figure 11 the VDRIVE pin is tied to DVDD, which results in logic output levels being either 0 V or DVDD. The voltage applied to VDRIVE controls the voltage value of the output logic signals. For example, if DVDD is supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic output levels would be either 0 V or 3 V. This feature allows the AD7485 to interface to 3 V devices while still enabling the A/D to process signals at 5 V supply. 1 (2π × f IN × t j )2 As an example, if the desired SNR due to jitter was 100 dB with a maximum full-scale analog input frequency of 500 kHz, ignoring all other noise sources we get an allowable jitter of 3.18 ps on the CONVST falling edge. For a 14-bit converter (ideal SNR = 86.04 dB), the allowable jitter will be greater than the figure given above; but due consideration needs to be given to the design of the CONVST circuitry to achieve 14-bit performance with large analog input frequencies. The maximum slew rate at the input of the ADC should be limited to 500 V/µs while the conversion is taking place. This will prevent corruption of the current conversion. In any multiplexed application, the channel switching should occur as early as possible after the first MCLK period. REV. 0 ANALOG SUPPLY 4.75V–5.25V –11– AD7485 Board Layout and Grounding To obtain optimum performance from the AD7485, it is recommended that a printed circuit board with a minimum of three layers is used. One of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. The board should be designed in such a way that the analog and digital circuitry are separated and confined to certain areas of the board. This practice, along with avoiding running digital and analog lines close together, should help to avoid coupling digital noise onto analog lines. The power supply lines to the AD7485 should be approximately 3 mm wide to provide a low impedance path and reduce the effects of glitches on the power supply lines. It is vital that good decoupling is also present. A combination of ferrites and decoupling capacitors should be used as shown in Figure 11. Figure 12a Figure 12b Figure 12c Figure 12d The decoupling capacitors should be as close to the supply pins as possible. This is made easier by the use of multilayer boards. The signal traces from the AD7485 pins can be run on the top layer while the decoupling capacitors and ferrites mounted on the bottom layer where the power traces exist. The ground plane between the top and bottom planes provides excellent shielding. Figures 12a–12e show a sample layout of the board area immediately surrounding the AD7485. Pin 1 is the bottom left corner of the device. Figure 12a shows the top layer where the AD7485 is mounted with vias to the bottom routing layer highlighted. Figure 12b shows the bottom layer where the power routing is with the same vias highlighted. Figure 12c shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. Figure 12d shows the silkscreen overlaid on the solder pads for the decoupling components, and Figure 12e shows the top and bottom routing layers overlaid. The black area in each figure indicates the ground plane present on the middle layer. Figure 12e C1-6 : 100 nF, C7–8: 470 nF, C9: 1 nF L1-4: Meggit-Sigma Chip Ferrite Beads (BMB2A0600RS2) –12– REV. 0 AD7485 t2 t4 t3 CONVST t7 t1 t5 MCLK t6 SCO t8 SDO t9 D14 D13 D12 D11 D10 D9 D8 D7 D6 t10 D5 D4 D3 D2 D1 t11 D0 Figure 13. Serial Mode 1 (SMODE = 0) Read Cycle t2 t12 t13 CONVST t7 t1 t5 MCLK t6 t14 SCO t9 SDO D14 D13 D12 D11 D10 D9 D8 D7 t10 D6 D5 D4 D3 D2 D1 D0 t16 t15 TFS t17 t18 Figure 14. Serial Mode 2 (SMODE = 1) Read Cycle t1 t6 MCLK t19 t20 t5 SCO t21 Figure 15. Serial Clock Timing REV. 0 –13– AD7485 OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 1.60 MAX 0.75 0.60 0.45 PIN 1 INDICATOR 9.00 BSC 37 48 36 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 SEATING PLANE SEATING PLANE 7.00 BSC TOP VIEW (PINS DOWN) 7 3.5 0 0.08 MAX COPLANARITY VIEW A 25 12 13 0.50 BSC VIEW A ROTATED 90 CCW 24 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC –14– REV. 0 –15– –16– PRINTED IN U.S.A. C02758–0–10/02(0)