8-Channel DAS with 14-Bit, Bipolar Input, Simultaneous Sampling ADC AD7607 Data Sheet FEATURES APPLICATIONS 8 simultaneously sampled inputs True bipolar analog input ranges: ±10 V, ±5 V Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE Fully integrated data acquisition solution Analog input clamp protection Input buffer with 1 MΩ analog input impedance Second-order antialiasing analog filter On-chip accurate reference and reference buffer 14-bit ADC with 200 kSPS on all channels Flexible parallel/serial interface SPI/QSPI™/MICROWIRE™/DSP compatible Pin-compatible solutions from 14 bits to 18 bits Performance 7 kV ESD rating on analog input channels Fast throughput rate: 200 kSPS for all channels 85.5 dB SNR at 50 kSPS INL ±0.25 LSB, DNL ±0.25 LSB Low power: 100 mW at 200 kSPS Standby mode: 25 mW typical 64-lead LQFP package Power-line monitoring and protection systems Multiphase motor control Instrumentation and control systems Multiaxis positioning systems Data acquisition systems (DAS) Table 1. High Resolution, Bipolar Input, Simultaneous Sampling DAS Solutions Resolution 18 Bits 16 Bits 14 Bits Single-Ended Inputs AD7608 AD7606 AD7606-6 AD7606-4 AD7607 Number of Simultaneous Sampling Channels 8 8 6 4 8 FUNCTIONAL BLOCK DIAGRAM AVCC CLAMP CLAMP V2 CLAMP V2GND CLAMP V3 CLAMP V3GND CLAMP V4 CLAMP V4GND CLAMP V5 CLAMP V5GND CLAMP V6 CLAMP V6GND CLAMP V7 CLAMP V7GND CLAMP V8 CLAMP V8GND CLAMP RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB 1MΩ RFB SECONDORDER LPF AVCC REGCAP REGCAP 2.5V LDO 2.5V LDO REFCAPB REFCAPA T/H REFIN/REFOUT SECONDORDER LPF T/H 2.5V REF SECONDORDER LPF T/H REF SELECT AGND OS 2 OS 1 OS 0 SECONDORDER LPF T/H SERIAL 8:1 MUX SECONDORDER LPF T/H DIGITAL FILTER 14-BIT SAR PARALLEL/ SERIAL INTERFACE DOUTA DOUTB RD/SCLK CS PAR/SER/BYTE SEL VDRIVE SECONDORDER LPF T/H PARALLEL DB[15:0] AD7607 SECONDORDER LPF SECONDORDER LPF T/H CLK OSC CONTROL INPUTS T/H AGND CONVST A CONVST B RESET RANGE BUSY FRSTDATA 08096-001 V1 V1GND 1MΩ Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010-2012 Analog Devices, Inc. All rights reserved. AD7607 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ADC Transfer Function ............................................................. 20 Applications ....................................................................................... 1 Internal/External Reference ...................................................... 21 Functional Block Diagram .............................................................. 1 Typical Connection Diagram ................................................... 22 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 22 General Description ......................................................................... 3 Conversion Control ................................................................... 23 Specifications..................................................................................... 4 Digital Interface .............................................................................. 24 Timing Specifications .................................................................. 6 Parallel Interface (PAR/SER/BYTE SEL = 0).......................... 24 Absolute Maximum Ratings .......................................................... 10 Parallel Byte Interface (PAR/SER/BYTE SEL = 1, DB15 = 1) .. 24 Thermal Resistance .................................................................... 10 Serial Interface (PAR/SER/BYTE SEL = 1) ............................. 24 ESD Caution ................................................................................ 10 Reading During Conversion ..................................................... 25 Pin Configuration and Function Descriptions ........................... 11 Digital Filter ................................................................................ 26 Typical Performance Characteristics ........................................... 14 Layout Guidelines ........................................................................... 29 Terminology .................................................................................... 18 Outline Dimensions ....................................................................... 31 Theory of Operation ...................................................................... 19 Ordering Guide .......................................................................... 31 Converter Details........................................................................ 19 Analog Input ............................................................................... 19 REVISION HISTORY 1/12—Rev. A to Rev. B Changes to Analog Input Ranges Section ....................................19 7/10—Rev. 0 to Rev. A Change to Table 1 .............................................................................. 1 7/10—Revision 0: Initial Version Rev. B | Page 2 of 32 Data Sheet AD7607 GENERAL DESCRIPTION The AD76071 is a 14-bit, simultaneous sampling, analog-todigital data acquisition system (DAS). The part contains analog input clamp protection; a second-order antialiasing filter; a trackand-hold amplifier; a 14-bit charge redistribution, successive approximation analog-to-digital converter (ADC); a flexible digital filter; a 2.5 V reference and reference buffer; and high speed serial and parallel interfaces. The AD7607 operates from a single 5 V supply and can accommodate ±10 V and ±5 V true bipolar input signals while sampling at throughput rates of up to 200 kSPS for all channels. The input 1 clamp protection circuitry can tolerate voltages of up to ±16.5 V. The AD7607 has 1 MΩ analog input impedance, regardless of sampling frequency. The single supply operation, on-chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. The AD7607 antialiasing filter has a 3 dB cutoff frequency of 22 kHz and provides 40 dB antialias rejection when sampling at 200 kSPS. The flexible digital filter is pin driven and can be used to simplify external filtering. Patent pending. Rev. B | Page 3 of 32 AD7607 Data Sheet SPECIFICATIONS VREF = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, fSAMPLE = 200 kSPS, TA = TMIN to TMAX, unless otherwise noted. 1 Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) (SINAD) 2, 3 Signal-to-Noise Ratio (SNR)2 Total Harmonic Distortion (THD)2 Peak Harmonic or Spurious Noise (SFDR)2 Intermodulation Distortion (IMD)2 Second-Order Terms Third-Order Terms Channel-to-Channel Isolation2 ANALOG INPUT FILTER Full Power Bandwidth tGROUP DELAY DC ACCURACY Resolution Differential Nonlinearity2 Integral Nonlinearity2 Positive/Negative Full-Scale Error2, 5 Positive Full-Scale Error Drift2 Negative Full-Scale Error Drift Positive/Negative Full-Scale Error Matching2 Bipolar Zero Code Error2, 6 Bipolar Zero Code Error Drift2 Bipolar Zero Code Error Matching Total Unadjusted Error (TUE) ANALOG INPUT Input Voltage Ranges Input Current Input Capacitance 7 Input Impedance Test Conditions/Comments fIN = 1 kHz sine wave, unless otherwise noted No oversampling; ±10 V range No oversampling; ±5 V range Oversampling by 4, fIN = 130 Hz No oversampling Min Typ 84 83.5 84.5 84.5 85.5 84.5 −107 −108 Max −95 Unit dB dB dB dB dB dB fa = 1 kHz, fb = 1.1 kHz fIN on unselected channels up to 160 kHz −110 −106 −95 dB dB dB −3 dB, ±10 V range −3 dB, ±5 V range −0.1 dB, ±10 V range −0.1 dB, ±5 V range ±10 V Range ±5 V Range 23 15 10 5 11 15 kHz kHz kHz kHz µs µs No missing codes 14 External reference Internal reference External reference Internal reference External reference Internal reference ±10 V range ±0.25 ±0.25 ±2 ±2 ±2 ±7 ±4 ±8 2 ±0.95 ±0.5 ±9 ±5 V range ±10 V range ±5 V range ±10 V range ±5 V range ±10 V range ±5 V range ±10 V range ±5 V range 4 ±0.5 ±1 10 5 1 3 ±0.5 ±1 10 ±2 ±3.5 RANGE = 1 RANGE = 0 +10 V +5 V 8 2.5 6 ±10 ±5 See the Analog Input section Rev. B | Page 4 of 32 5.4 2.5 5 1 Bits LSB 4 LSB LSB LSB ppm/°C ppm/°C ppm/°C ppm/°C LSB LSB LSB LSB µV/°C µV/°C LSB LSB LSB LSB V V µA µA pF MΩ Data Sheet Parameter REFERENCE INPUT/OUTPUT Reference Input Voltage Range DC Leakage Current Input Capacitance7 Reference Output Voltage Reference Temperature Coefficient LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance (CIN)7 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating-State Leakage Current Floating-State Output Capacitance7 Output Coding CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS AVCC VDRIVE ITOTAL Normal Mode (Static) Normal Mode (Operational)8 Standby Mode Shutdown Mode Power Dissipation 8 Normal Mode (Static) Normal Mode (Operational) Standby Mode Shutdown Mode AD7607 Test Conditions/Comments Min Typ Max Unit 2.475 2.5 2.525 ±1 V µA pF V REF SELECT = 1 REFIN/REFOUT 7.5 2.49/ 2.505 ±10 ppm/°C 0.9 × VDRIVE 0.1 × VDRIVE ±2 V V µA pF 0.2 ±20 V V µA pF 5 ISOURCE = 100 µA ISINK = 100 µA VDRIVE − 0.2 ±1 5 Twos complement All eight channels included; see Table 3 4 1 200 µs µs kSPS 5.25 5.25 V V 16 20 5 2 22 27 8 6 mA mA mA µA 80 100 25 10 115.5 142 42 31.5 mW mW mW µW All eight channels included 4.75 2.3 Digital inputs = 0 V or VDRIVE Temperature range for the B version is −40°C to +85°C. See the Terminology section. 3 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB and THD typically reduces by 3 dB. 4 LSB means least significant bit. With ±5 V input range, 1 LSB = 610.35 µV. With ±10 V input range, 1 LSB = 1.22 mV. 5 This specification includes the full temperature range variation and contribution from the internal reference buffer but does not include the error contribution from the external reference. 6 Bipolar zero code error is calculated with respect to the analog input voltage. 7 Sample tested during initial release to ensure compliance. 8 Operational power/current figure includes contribution when running in oversampling mode. 1 2 Rev. B | Page 5 of 32 AD7607 Data Sheet TIMING SPECIFICATIONS AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference/internal reference, TA = TMIN to TMAX, unless otherwise noted. 1 Table 3. Parameter PARALLEL/SERIAL/BYTE MODE tCYCLE Limit at TMIN, TMAX Min Typ Max Unit 5 µs 9.1 µs µs tWAKE-UP STANDBY 4.15 9.1 18.8 39 78 158 315 100 µs µs µs µs µs µs µs µs tWAKE-UP SHUTDOWN Internal Reference 30 ms External Reference 13 ms 5 tCONV 3.45 7.87 16.05 33 66 133 257 tRESET tOS_SETUP tOS_HOLD t1 t2 t3 t4 t5 2 t6 t7 PARALLEL/BYTE READ OPERATION t8 t9 t10 t11 t12 4 50 20 20 25 ns ns ns ns ns ns ns ms ns ns 0 0 ns ns 16 21 25 32 15 22 ns ns ns ns ns ns 40 25 25 0 0.5 25 Description 1/throughput rate Parallel mode, reading during or after conversion; or serial mode (VDRIVE = 3.3 V to 5.25 V), reading during a conversion using DOUTA and DOUTB lines Serial mode reading during conversion; VDRIVE = 2.7 V Serial mode reading after a conversion; VDRIVE = 2.3 V, DOUTA and DOUTB lines Conversion time Oversampling off Oversampling by 2 Oversampling by 4 Oversampling by 8 Oversampling by 16 Oversampling by 32 Oversampling by 64 STBY rising edge to CONVST x rising edge; power-up time from standby mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode STBY rising edge to CONVST x rising edge; power-up time from shutdown mode RESET high pulse width BUSY to OS x pin setup time BUSY to OS x pin hold time CONVST x high to BUSY high Minimum CONVST x low pulse Minimum CONVST x high pulse BUSY falling edge to CS falling edge setup time Maximum delay allowed between CONVST A, CONVST B rising edges Maximum time between last CS rising edge and BUSY falling edge Minimum delay between RESET low to CONVST x high CS to RD setup time CS to RD hold time RD low pulse width VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V RD high pulse width CS high pulse width (see Figure 5); CS and RD linked Rev. B | Page 6 of 32 Data Sheet Parameter t13 AD7607 Limit at TMIN, TMAX Min Typ Max Unit 16 20 25 30 ns ns ns ns 16 21 25 32 22 ns ns ns ns ns ns ns 23.5 17 14.5 11.5 MHz MHz MHz MHz 15 20 30 ns ns ns 17 23 27 34 ns ns ns ns ns ns 22 ns 15 20 25 30 15 20 25 30 ns ns ns ns ns ns ns ns ns 16 20 25 30 ns ns ns ns t143 t15 t16 t17 6 6 SERIAL READ OPERATION fSCLK t18 t19 3 t20 t21 t22 t23 0.4 tSCLK 0.4 tSCLK 7 FRSTDATA OPERATION t24 t25 t26 Description Delay from CS until DB[15:0] three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data access time after RD falling edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Data hold time after RD falling edge CS to DB[15:0] hold time Delay from CS rising edge to DB[15:0] three-state enabled Frequency of serial read clock VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS until DOUTA/DOUTB three-state disabled/delay from CS until MSB valid VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE = 2.3 V to 2.7 V Data access time after SCLK rising edge VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V SCLK low pulse width SCLK high pulse width SCLK rising edge to DOUTA/DOUTB valid hold time CS rising edge to DOUTA/DOUTB three-state enabled Delay from CS falling edge until FRSTDATA three-state disabled VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from CS falling edge until FRSTDATA high, serial mode VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Delay from RD falling edge to FRSTDATA high VDRIVE above 4.75 V VDRIVE above 3.3 V VDRIVE above 2.7 V VDRIVE above 2.3 V Rev. B | Page 7 of 32 AD7607 Data Sheet Limit at TMIN, TMAX Min Typ Max Parameter t27 Unit 19 24 ns ns 17 22 24 ns ns ns t28 t29 Description Delay from RD falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from 16th SCLK falling edge to FRSTDATA low VDRIVE = 3.3 V to 5.25 V VDRIVE = 2.3 V to 2.7 V Delay from CS rising edge until FRSTDATA three-state enabled Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V. The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <3 LSB performance matching between channel sets. 3 A buffer, which is equivalent to a load of 20 pF on the output pins, is used on the data output pins for these measurements. 1 2 Timing Diagrams t5 CONVST A, CONVST B tCYCLE CONVST A, CONVST B t2 t3 tCONV t1 BUSY t4 CS t7 08096-002 tRESET RESET Figure 2. CONVST Timing—Reading After a Conversion t5 CONVST A, CONVST B tCYCLE CONVST A, CONVST B t2 t3 tCONV t1 BUSY t6 CS t7 08096-003 tRESET RESET Figure 3. CONVST Timing—Reading During a Conversion CS t8 t16 t13 t14 DATA: DB[15:0] FRSTDATA INVALID t24 V1 t26 V2 V3 t17 t15 V4 t27 V7 V8 t29 Figure 4. Parallel Mode, Separate CS and RD Pulses Rev. B | Page 8 of 32 08096-004 RD t9 t11 t10 Data Sheet AD7607 t12 CS AND RD t16 t13 DATA: DB[15:0] V2 V3 V4 V5 V6 V7 V8 08096-005 V1 t17 FRSTDATA Figure 5. Linked Parallel Mode, CS and RD CS t21 SCLK t20 t19 t18 DOUTA, DOUTB DB13 t22 DB12 DB11 t23 DB1 DB0 t29 t28 08096-006 t25 FRSTDATA Figure 6. Serial Read Operation (Channel 1) CS t8 t9 t10 t16 t13 DATA: DB[7:0] INVALID HIGH BYTE V1 t14 t15 LOW BYTE V1 HIGH BYTE V8 t26 FRSTDATA t27 t24 Figure 7. BYTE Mode Read Operation Rev. B | Page 9 of 32 t17 LOW BYTE V8 t29 08096-007 RD t11 AD7607 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. Parameter AVCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range B Version Storage Temperature Range Junction Temperature Pb/SN Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow ESD (All Pins Except Analog Inputs) ESD (Analog Input Pins Only) 1 Rating −0.3 V to +7 V −0.3 V to AVCC + 0.3 V ±16.5 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VDRIVE + 0.3 V −0.3 V to AVCC + 0.3 V ±10 mA θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. These specifications apply to a 4-layer board. Table 5. Thermal Resistance Package Type 64-Lead LQFP ESD CAUTION −40°C to +85°C −65°C to +150°C 150°C 240 (+ 0)°C 260 (+ 0)°C 2 kV 7 kV Transient currents of up to 100 mA do not cause SCR latch-up. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 10 of 32 θJA 45 θJC 11 Unit °C/W Data Sheet AD7607 64 63 62 61 60 59 58 V1GND V1 V2 V3 V2GND V4 V3GND V5 V4GND V6 V5GND V6GND V7 V7GND V8 V8GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 AVCC 1 ANALOG INPUT 48 PIN 1 AGND 2 OS 0 3 DECOUPLING CAP PIN AVCC 47 AGND 46 REFGND POWER SUPPLY OS 1 4 45 REFCAPB GROUND PIN OS 2 5 44 REFCAPA AD7607 43 REFGND TOP VIEW (Not to Scale) 42 REFIN/REFOUT 41 AGND CONVST A 9 40 AGND CONVST B 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC CS 13 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 DB0 16 34 REF SELECT 33 DB15/BYTE SEL DATA OUTPUT PAR/SER/BYTE SEL 6 STBY 7 DIGITAL OUTPUT RANGE 8 DIGITAL INPUT REFERENCE INPUT/OUTPUT 08096-008 DB14/HBEN DB13 DB12 DB10 DB11 DB9 AGND DB8/DOUTB DB7/DOUTA VDRIVE DB6 DB5 DB4 DB3 DB2 DB1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 8. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 37, 38, 48 Type 1 P Mnemonic AVCC 2, 26, 35, 40, 41, 47 P AGND 5, 4, 3 DI OS[2:0] 6 DI PAR/SER/ BYTE SEL 7 DI STBY 8 DI RANGE Description Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. These supply pins should be decoupled to AGND. Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7607. All analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, and OS 0 is the LSB control bit. See the Digital Filter section for more details about the oversampling mode of operation and Table 9 for oversampling bit decoding. Parallel/Serial/Byte Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. Parallel byte interface mode is selected when this pin is logic high and DB15/BYTE SEL is logic high (see Table 8). In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA pin and the DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to ground. In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte mode of operation (see Table 8). DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion results in two RD operations, with DB0 as the LSB of the data transfers. Standby Mode Input. This pin is used to place the AD7607 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin, as shown in Table 7. When in standby mode, all circuitry, except the on-chip reference, regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down. Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended. See the Analog Input section for more information. Rev. B | Page 11 of 32 AD7607 Data Sheet Pin No. 9, 10 Type 1 DI Mnemonic CONVST A, CONVST B 11 DI RESET 12 DI RD/SCLK 13 DI CS 14 DO BUSY 15 DO FRSTDATA 22 to 16 DO DB[6:0] 23 P VDRIVE 24 DO DB7/DOUTA 25 DO DB8/DOUTB 31 to 27 DO DB[13:9] Description Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all 8 input channels CONVST A and CONVST B can be shorted together and a single convert start signal applied. Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4; and CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is possible only when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to hold. Reset Input. When set to logic high, the rising edge of RESET resets the AD7607. The part should receive a RESET pulse after power-up. The RESET high pulse should typically be 50 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET pulse is applied during a read, the contents of the output registers reset to all zeros. Parallel Data Read Control Input When the Parallel Interface Is Selected (RD)/Serial Clock Input When the Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out of tristate and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. For more information, see the Conversion Control section. Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in parallel mode, the DB[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. In serial mode, CS is used to frame the serial read transfer and clock out the MSB of the serial output data. Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and indicates that the conversion process has started. The BUSY output remains high until the conversion process for all channels is complete. The falling edge of BUSY signals that the conversion data is being latched into the output data registers and is available to read after a Time t4. Any data read while BUSY is high must be completed before the falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while the BUSY signal is high. Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel, parallel byte, or serial interface. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, which indicates that the result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS because this clocks out the MSB of V1 on DOUTA. It returns low on the 14th SCLK falling edge after the CS falling edge. See the Conversion Control section for more details. Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to DGND. When operating in parallel byte interface mode, DB[7:0] outputs the 14-bit conversion result in two RD operations. DB7 is the MSB, and DB0 is the LSB. Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface (that is, DSP and FPGA). Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER/BYTE SEL = 0, this pins acts as a three-state parallel digital input/ output pin. When CS and RD are low, this pin is used to output DB7 of the conversion result. When PAR/SER/BYTE SEL = 1, this pin functions as DOUTA and outputs serial conversion data (see the Conversion Control section for more details). When operating in parallel byte mode, DB7 is the MSB of the byte. Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital input/output pin. When CS and RD are low, this pin is used to output DB8 of the conversion result. When PAR/ SER/BYTE SEL = 1, this pin functions as DOUTB and outputs serial conversion data (see the Conversion Control section for more details). Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as three-state parallel digital input/output pins. When CS and RD are low, these pins are used to output DB13 to DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, these pins should be tied to DGND. Rev. B | Page 12 of 32 Data Sheet AD7607 Pin No. 32 Type 1 DO/DI Mnemonic DB14/HBEN 33 DO/DI DB15/ BYTE SEL 34 DI REF SELECT 36, 39 P REGCAP 42 REF REFIN/ REFOUT 43, 46 44, 45 REF REF 49, 51, 53, 55, 57, 59, 61, 63 50, 52, 54, 56, 58, 60, 62, 64 AI REFGND REFCAPA, REFCAPB V1 to V8 1 AI GND V1GND to V8GND Description Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB14 of the conversion result, which is a sign extended bit of the MSB, DB13. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7607 operates in parallel byte interface mode, in which the HBEN pin is used to select if the most significant byte (MSB) or the least significant byte (LSB) of the conversion result is output first. When HBEN = 1, the MSB byte is output first, followed by the LSB byte. When HBEN = 0, the LSB byte is output first, followed by the MSB byte. Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). When PAR/SER/BYTE SEL = 0, this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is used to output DB15, which is a sign extended bit of the MSB, DB13, of the conversion result. When PAR/ SER/BYTE SEL = 1, the BYTE SEL pin is used to select between serial interface mode or parallel byte interface mode (see Table 8). When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7607 operates in serial interface mode. When PAR/SER/BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7607 operates in parallel byte interface mode. Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. Decoupling Capacitor Pin for Voltage Output from Internal Regulator. These output pins should be decoupled separately to AGND using a 1 μF capacitor. The voltage on these pins is in the range of 2.5 V to 2.7 V. Reference Input (REFIN)/Reference Output (REFOUT). The gained up on-chip reference of 2.5 V is available on this pin for external use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled by setting the REF SELECT pin to a logic low, and an external reference of 2.5 V can be applied to this input (see the Internal/External Reference section). Decoupling is required on this pin for both the internal or external reference options. A 10 µF capacitor should be applied from this pin to ground close to the REFGND pins. Reference Ground Pins. These pins should be connected to AGND. Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to AGND using a low ESR 10 μF ceramic capacitor. Analog Inputs. These pins are single-ended analog inputs. The analog input range of these channels is determined by the RANGE pin. Analog Input Ground Pins. These pins correspond to Analog Input Pin V1 to Analog Input Pin V8. All analog input AGND pins should connect to the AGND plane of a system. P = power supply, DI = digital input, DO = digital output, REF = reference input/output, AI = analog input, GND = ground. Rev. B | Page 13 of 32 AD7607 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0.5 AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±10V RANGE SNR: 85.07dB THD: –107.33dB 16,384 POINT FFT fIN = 1kHz –40 SNR (dB) –60 AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±10V RANGE 0.4 0.3 0.2 DNL (LSB) –20 –80 –100 0.1 0 –0.1 –0.2 –120 –0.3 –140 10 20 30 40 50 60 70 80 90 100 INPUT FREQUENCY (kHz) –0.5 08096-018 0 0 4000 6000 8000 10,000 12,000 14,000 16,000 CODE Figure 9. FFT ± 10 V Range Figure 12. Typical DNL ± 10 V Range 0.5 0 AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±5V RANGE SNR: 84.82dB THD: –107.51dB 16,384 POINT FFT fIN = 1kHz –40 –60 AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±5V RANGE 0.4 0.3 0.2 INL (LSB) –20 SNR (dB) 2000 08096-020 –0.4 –160 –80 0.1 0 –0.1 –100 –0.2 –120 –0.3 –140 –0.5 0 10 20 30 40 50 60 70 80 90 100 INPUT FEQUENCY (kHz) 08096-017 –160 0 2000 8000 0.5 AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±10V RANGE 0.4 0.3 10,000 12,000 14,000 16,000 Figure 13. Typical INL ± 5 V Range 0.5 AVCC = VDRIVE = 5V INTERNAL REFERENCE 0.4 fSAMPLE = 200kSPS TA = 25°C ±5V RANGE 0.3 0.2 DNL (LSB) 0.2 0.1 0 –0.1 0.1 0 –0.1 –0.2 –0.2 –0.3 –0.3 –0.5 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 CODE Figure 14. Typical DNL ± 5 V Range Figure 11. Typical INL ± 10 V Range Rev. B | Page 14 of 32 08096-009 –0.4 –0.4 08096-019 INL (LSB) 6000 CODE Figure 10. FFT Plot ± 5 V Range –0.5 4000 08096-010 –0.4 Data Sheet AD7607 10 5.00 3.75 8 ±10V RANGE 1.25 ±5V RANGE 0 –1.25 –2.50 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) 2 AVCC, VDRIVE = 5V FSAMPLE = 200 kSPS TA = 25°C EXTERNAL REFERENCE SOURCE RESISTANCE IS MATCHED ON THE VxGND INPUT ±10V AND ±5V RANGE –2 08096-115 –5.00 –40 4 0 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE –3.75 6 0 20k 40k 60k 80k 100k 120k SOURCE RESISTANCE (Ω) Figure 15. NFS Error vs. Temperature 08096-118 PFS/NFS ERROR (%FS) NFS ERROR (LSB) 2.50 Figure 18. PFS and NFS Error vs. Source Resistance 86 5.00 3.75 85 84 1.25 SNR (dB) 0 ±5V RANGE 83 –1.25 82 ±10V RANGE AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±5V RANGE ALL 8 CHANNELS –2.50 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) 80 10 08096-116 –5.00 –40 81 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE –3.75 100 1k 10k 100k INPUT FREQUENCY (Hz) Figure 16. PFS Error vs. Temperature 08096-022 PFS ERROR (LSB) 2.50 Figure 19. SNR vs. Input Frequency ± 5 V Range 86 2.5 PFS ERROR 85 1.5 1.0 84 NFS ERROR SNR (dB) 0.5 0 –0.5 81 10V RANGE AVCC, VDRIVE = 5V EXTERNAL REFERENCE –2.0 –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) AVCC = VDRIVE = 5V INTERNAL REFERENCE fSAMPLE = 200kSPS TA = 25°C ±10V RANGE ALL 8 CHANNELS 80 10 100 1k 10k INPUT FREQUENCY (Hz) Figure 20. SNR vs. Input Frequency ± 10 V Range Figure 17. PFS and NFS Error Matching vs. Temperature Rev. B | Page 15 of 32 100k 08096-023 –1.5 –2.5 –40 83 82 –1.0 08096-117 NFS/PFS CHANNEL MATCHING (LSB) 2.0 AD7607 Data Sheet 0.25 –40 ±5V RANGE AVCC, VDRIVE = +5V –50 fSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS 0.15 –60 0.10 –70 THD (dB) 0 5V RANGE –0.05 10V RANGE –100 –0.15 –0.25 –40 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE –25 –10 5 20 35 50 65 80 TEMPERATURE (°C) –110 –120 1k 10k 100k INPUT FREQUENCY (Hz) Figure 21. Bipolar Zero Code Error vs. Temperature Figure 24. THD vs. Input Frequency for Various Source Impedances, ±5 V Range 1.00 2.5010 0.75 2.5005 5V RANGE AVCC = 5.25V AVCC = 5V REFOUT VOLTAGE (V) 0.50 0.25 10V RANGE 0 –0.25 2.5000 2.4995 AVCC = 4.75V 2.4990 –0.50 5 20 35 50 65 80 2.4980 –40 8 ±10V RANGE AVCC, VDRIVE = +5V –50 fSAMPLE = 200kSPS RSOURCE MATCHED ON Vx AND VxGND INPUTS 6 INPUT CURRENT (µA) –70 –80 105kΩ 48.7kΩ 23.7kΩ 10kΩ 5kΩ 1.2kΩ 100Ω 51Ω 0Ω 10k 35 50 65 80 AVCC, VDRIVE = 5V fSAMPLE = 200kSPS 100k INPUT FREQUENCY (Hz) Figure 23. THD vs. Input Frequency for Various Source Impedances, ±10 V Range 2 0 –2 –4 –6 +85°C +25°C –40°C –8 –10 –10 08096-121 –120 1k 20 4 –60 –110 5 Figure 25. Reference Output Voltage vs. Temperature for Different Supply Voltages –40 –100 –10 TEMPERATURE (°C) Figure 22. Bipolar Zero Code Error Matching vs. Temperature –90 –25 08096-125 –10 –8 –6 –4 –2 0 2 INPUT VOLTAGE (V) 4 6 8 10 08096-126 –25 08096-120 –1.00 –40 2.4985 200kSPS AVCC, VDRIVE = 5V EXTERNAL REFERENCE –0.75 TEMPERATURE (°C) THD (dB) 105kΩ 48.7kΩ 23.7kΩ 10kΩ 5kΩ 1.2kΩ 100Ω 51Ω 0Ω –90 –0.10 –0.20 BIPOLAR ZERO CODE ERROR MATCHING (LSB) –80 08096-122 0.05 08096-119 BIPOLAR ZERO CODE ERROR (LSB) 0.20 Figure 26. Analog Input Current vs. Input Voltage for Various Temperatures Rev. B | Page 16 of 32 Data Sheet AD7607 –50 18 16 14 12 AVCC, VDRIVE = 5V 10 TA = 25°C INTERNAL REFERENCE fSAMPLE VARIES WITH OS RATE 8 NO OS OS2 OS4 OS8 OS16 OS32 OS64 OVERSAMPLING RATIO 08096-127 AVCC SUPPLY CURRENT (mA) 20 Figure 27. Supply Current vs. Oversampling Rate 120 ±10V RANGE 110 ±5V RANGE 100 90 AVCC, VDRIVE = 5V INTERNAL REFERENCE AD7607 RECOMMENDED DECOUPLING USED fSAMPLE = 200kSPS TA = 25°C 60 0 100 200 300 400 500 600 700 800 AVCC NOISE FREQUENCY (kHz) 900 1000 1100 08096-128 POWER SUPPLY REJECTION RATIO (dB) 130 70 –90 ±10V RANGE –100 ±5V RANGE –110 –120 –130 –140 0 20 40 60 80 100 120 NOISE FREQUENCY (kHz) Figure 29. Channel-to-Channel Isolation 140 80 AVCC, VDRIVE = 5V INTERNAL REFERENCE AD7607 RECOMMENDED DECOUPLING USED fSAMPLE = 150kSPS –70 TA = 25°C INTERFERER ON ALL UNSELECTED CHANNELS –80 –60 Figure 28. PSRR Rev. B | Page 17 of 32 140 160 08096-129 CHANNEL-TO-CHANNEL ISOLATION (dB) 22 AD7607 Data Sheet TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, at ½ LSB below the first code transition; and full scale, at ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error The deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V – ½ LSB. Bipolar Zero Code Error Match The absolute difference in bipolar zero code error between any two input channels. Positive Full-Scale Error The deviation of the actual last code transition from the ideal last code transition (10 V − 1½ LSB (9.998) and 5 V − 1½ LSB (4.99908)) after bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference buffer. Positive Full-Scale Error Match The absolute difference in positive full-scale error between any two input channels. Negative Full-Scale Error The deviation of the first code transition from the ideal first code transition (−10 V + ½ LSB (−9.9993) and −5 V + ½ LSB (−4.99969)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference buffer. Negative Full-Scale Error Match The absolute difference in negative full-scale error between any two input channels. Signal-to-(Noise + Distortion) Ratio The measured ratio of signal-to-(noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 14-bit converter, the signal-to-(noise + distortion) is 86.04 dB. Total Harmonic Distortion (THD) The ratio of the rms sum of the harmonics to the fundamental. For the AD7607, it is defined as THD (dB) = 20log V2 2 + V32 + V4 2 + V5 2 + V6 2 + V72 + V82 + V92 V1 where: V1 is the rms amplitude of the fundamental. V2 to V9 are the rms amplitudes of the second through ninth harmonics. Peak Harmonic or Spurious Noise The ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is determined by a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3. Intermodulation distortion terms are those for which neither m nor n is equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (dB). Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. PSR is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSR ratio (PSRR) is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200 mV p-p sine wave applied to the ADC’s VDD and VSS supplies of frequency, fS. PSRR (dB) = 10log (Pf/PfS) where: Pf is equal to the power at Frequency f in the ADC output. PfS is equal to the power at Frequency fS coupled onto the AVCC supplies. Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale sine wave signal of up to 160 kHz to all unselected input channels, and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 29). Rev. B | Page 18 of 32 Data Sheet AD7607 THEORY OF OPERATION CONVERTER DETAILS Analog Input Clamp Protection The AD7607 is a data acquisition system that employs a high speed, low power, charge redistribution, successive approximation analog-to-digital converter (ADC) and allows the simultaneous sampling of eight analog input channels. The analog inputs on the AD7607 can accept true bipolar input signals. The RANGE pin is used to select either ±10 V or ±5 V as the input range. The AD7607 operates from a single 5 V supply. Figure 30 shows the analog input structure of the AD7607. Each AD7607 analog input contains clamp protection circuitry. Despite single 5 V supply operation, this analog input clamp protection allows for an input overvoltage of up to ±16.5 V. The AD7607 can handle true bipolar input voltages. The logic level on the RANGE pin determines the analog input range of all analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range; however, there is a typical settling time of ~80 µs, in addition to the normal acquisition time requirement. Recommended practice is to hardwire the RANGE pin according to the desired input range for the system signals. During normal operation, the applied analog input voltage should remain within the analog input range selected via the range pin. A RESET pulse must be applied after power-up to ensure the analog input channels are configured for the range selected. When in a power-down mode, it is recommended to tie the analog inputs to GND. As per the input clamp protection section, the overvoltage clamp protection is recommended for use in transient overvoltage conditions and should not remain active for extended periods. Stressing the analog inputs outside of the conditions mentioned here may degrade the Bipolar Zero Code error and THD performance of the AD7607. Analog Input Impedance 1MΩ 08096-032 CLAMP SECONDORDER LPF Figure 30. Analog Input Circuitry Figure 31 shows the voltage vs. current characteristic of the clamp circuit. For input voltages of up to ±16.5 V, no current flows in the clamp circuit. For input voltages that are above ±16.5 V, the AD7607 clamp circuitry turns on and clamps the analog input to ±16.5 V. AV , VDRIVE = 5V 30 T CC A = 25°C 20 10 0 –10 –20 –30 –40 –50 –20 –15 –10 –5 0 5 10 15 20 SOURCE VOLTAGE (V) 08096-051 Analog Input Ranges CLAMP Figure 31. Input Protection Clamp Profile A series resistor should be placed on the analog input channels to limit the current to ±10 mA for input voltages above ±16.5 V. In an application where there is a series resistance on an analog input channel, Vx, a corresponding resistance is required on the analog input GND channel, VxGND (see Figure 32). If there is no corresponding resistor on the VxGND channel, an offset error occurs on that channel. The analog input impedance of the AD7607 is 1 MΩ. This is a fixed input impedance that does not vary with the AD7607 sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7607, allowing for direct connection to the source or sensor. With the need for a driver amplifier eliminated, bipolar supplies (which are often a source of noise in a system) can be removed from the signal chain. Rev. B | Page 19 of 32 RFB AD7607 ANALOG INPUT SIGNAL R R C VINx VxGND CLAMP CLAMP 1MΩ 1MΩ RFB Figure 32. Input Resistance Matching on the Analog Input 08096-032 ANALOG INPUT Vx VxGND RFB INPUT CLAMP CURRENT (mA) The AD7607 contains input clamp protection, input signal scaling amplifiers, a second-order antialiasing filter, track-and-hold amplifiers, an on-chip reference, reference buffers, a high speed ADC, a digital filter, and high speed parallel and serial interfaces. Sampling on the AD7607 is controlled using the CONVST signals. RFB 1MΩ AD7607 Data Sheet Analog Input Antialiasing Filter The end of the conversion process across all eight channels is indicated by the falling edge of BUSY, and it is at this point that the track-and-holds return to track mode and the acquisition time for the next set of conversions begins. An analog antialiasing filter (a second-order Butterworth) is also provided on the AD7607. Figure 33 and Figure 34 show the frequency and phase response, respectively, of the analog antialiasing filter. In the ±5 V range, the −3 dB frequency is typically 15 kHz. In the ±10 V range, the −3 dB frequency is typically 23 kHz. The conversion clock for the part is internally generated, and the conversion time for all channels is 4 µs. On the AD7607, the BUSY signal returns low after all eight conversions to indicate the end of the conversion process. On the falling edge of BUSY, the track-and-hold amplifiers return to track mode. New data can be read from the output register via the parallel, parallel byte, or serial interface after BUSY goes low; or, alternatively, data from the previous conversion can be read while BUSY is high. Reading data from the AD7607 while a conversion is in progress has little effect on performance and allows a faster throughput to be achieved. In parallel mode at VDRIVE > 3.3 V, the SNR is reduced by ~1.5 dB when reading during a conversion. 5 0 ±5V RANGE –15 –20 –25 –30 –35 ±10V RANGE –40 +25 +85 0.1dB 10,303 9619 9326 3dB 24,365Hz 23,389Hz 22,607Hz ±5V RANGE –40 +25 +85 0.1dB 5225 5225 4932 3dB 16,162Hz 15,478Hz 14,990Hz –40 100 1k ADC TRANSFER FUNCTION 10k 100k INPUT FREQUENCY (Hz) Figure 33. Analog Antialiasing Filter Frequency Response The output coding of the AD7607 is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB, 3/2 LSB. The LSB size is FSR/16,384. The ideal transfer characteristic is shown in Figure 35. VIN × 8182 × 10V VIN ±5V CODE = × 8192 × 5V ±10V CODE = 18 011...111 011...110 16 ±5V RANGE ADC CODE 14 PHASE DELAY (µs) 12 10 ±10V RANGE 8 6 000...001 000...000 111...111 REF 2.5V REF 2.5V LSB = +FS – (–FS) 214 100...010 100...001 100...000 4 2 –FS + 1/2LSB 0V – 1LSB +FS – 3/2LSB ANALOG INPUT 0 +FS ±10V RANGE +10V ±5V RANGE +5V –2 –FS –10V –5V LSB 1.22mV 610µV Figure 35. Transfer Characteristics 10k INPUT FREQUENCY (Hz) 100k 08096-052 –4 AVCC, VDRIVE = 5V f = 200kSPS –6 SAMPLE TA = 25°C –8 10 1k MIDSCALE 0V 0V 08096-035 –10 08096-053 ATTENUATION (dB) –5 ±10V RANGE AVCC, VDRIVE = 5V fSAMPLE = 200kSPS TA = 25°C The LSB size is dependent on the analog input range selected. Figure 34. Analog Antialiasing Filter Phase Response Track-and-Hold Amplifiers The track-and-hold amplifiers on the AD7607 let the ADC accurately acquire an input sine wave of full-scale amplitude to 14-bit resolution. The track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of CONVST x. The aperture time for the track-and-hold (that is, the delay time between the external CONVST x signal and the track-and-hold actually going into hold) is well matched, by design, across all eight track-and-holds on one device and from device to device. This matching allows more than one AD7607 device to be sampled simultaneously in a system. Rev. B | Page 20 of 32 Data Sheet AD7607 INTERNAL/EXTERNAL REFERENCE Internal Reference Mode The AD7607 contains an on-chip 2.5 V bandgap reference. The REFIN/REFOUT pin allows access to the 2.5 V reference that generates the on-chip 4.5 V reference internally, or it allows an external reference of 2.5 V to be applied to the AD7607. An externally applied reference of 2.5 V is also gained up to 4.5 V, using the internal buffer. This 4.5 V buffered reference is the reference used by the SAR ADC. One AD7607 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7607 devices, which are configured to operate in external reference mode (see Figure 38). The REFIN/REFOUT pin of the AD7607, configured in internal reference mode, should be decoupled using a 10 μF ceramic decoupling capacitor. The other AD7607 devices, configured in external reference mode, should use a 100 nF decoupling capacitor on their REFIN/REFOUT pins. 10µF REFCAPB 2.5V REF Figure 36. Reference Circuitry AD7607 AD7607 AD7607 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT 100nF 100nF 100nF ADR421 0.1µF Figure 37. Single External Reference Driving Multiple AD7607 REFIN Pins VDRIVE AD7607 External Reference Mode One ADR421 external reference can be used to drive the REFIN/REFOUT pins of all AD7607 devices (see Figure 37). In this configuration, each REFIN/REFOUT pin of the AD7607 should be decoupled with a 100 nF decoupling capacitor. REFCAPB BUF 08096-038 When the AD7607 is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. For applications using multiple AD7607 devices, the following configurations are recommended, depending on the application requirements. SAR AD7607 AD7607 REF SELECT REF SELECT REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT + 10µF 100nF 100nF Figure 38. Internal Reference Driving Multiple AD7607 REFIN Pins. Rev. B | Page 21 of 32 08096-037 The AD7607 contains a reference buffer configured to gain the REF voltage up to ~4.5 V, as shown in Figure 36. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 μF applied to REFGND, to ensure that the reference buffer is in closed-loop operation. The reference voltage available at the REFIN/REFOUT pin is 2.5 V. REFIN/REFOUT 08096-036 The REF SELECT pin is a logic input pin that allows the user to select between the internal reference or an external reference. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. The internal reference buffer is always enabled. After a reset, the AD7607 operates in the reference mode selected by the REF SELECT pin. Decoupling is required on the REFIN/REFOUT pin for both the internal and external reference options. A 10 μF ceramic capacitor is required on the REFIN/REFOUT pin. AD7607 Data Sheet TYPICAL CONNECTION DIAGRAM The power-down mode is selected through the state of the RANGE pin when the STBY pin is low. Table 7 shows the configurations required to choose the desired power-down mode. When the AD7607 is placed in standby mode, current consumption is 8 mA maximum and power-up time is approximately 100 µs because the capacitor on the REFCAPA and REFCAPB pins must charge up. In standby mode, the on-chip reference and regulators remain powered up, and the amplifiers and ADC core are powered down. Figure 39 shows the typical connection diagram for the AD7607. There are four AVCC supply pins on the part, and each of the four pins should be decoupled using a 100 nF capacitor at each supply pin and a 10 µF capacitor at the supply source. The AD7607 can operate with the internal reference or an externally applied reference. In this configuration, the AD7607 is configured to operate with the internal reference. When using a single AD7607 device on the board, the REFIN/REFOUT pin should be decoupled with a 10 µF capacitor. When using an application with multiple AD7607 devices, refer to the Internal/External Reference section. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 µF ceramic capacitor. When the AD7607 is placed in shutdown mode, current consumption is 6 µA maximum and power-up time is approximately 13 ms (external reference mode). In shutdown mode, all circuitry is powered down. When the AD7607 is powered up from shutdown mode, a RESET signal must be applied to the AD7607 after the required power-up time has elapsed. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For layout, decoupling, and grounding hints, see the Layout Guidelines section. Table 7. Power-Down Mode Selection POWER-DOWN MODES ANALOG SUPPLY VOLTAGE 5V1 1µF REFIN/REFOUT 100nF 100nF REGCAP2 AVCC VDRIVE REFCAPA 10µF DB0 TO DB15 + REFCAPB REFGND EIGHT ANALOG INPUTS V1 TO V8 V1 V1GND V2 V2GND V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND CONVST A, CONVST B CS RD BUSY AD7607 RESET OS 2 OS 1 OS 0 REF SELECT PARALLEL INTERFACE OVERSAMPLING VDRIVE PAR/SER SEL RANGE STBY VDRIVE AGND 1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). 2DECOUPLING Figure 39. Typical Connection Diagram Rev. B | Page 22 of 32 08096-039 + DIGITAL SUPPLY VOLTAGE +2.3V TO +5V MICROPROCESSOR/ MICROCONVERTER/ DSP Two power-down modes are available on the AD7607: standby mode and shutdown mode. The STBY pin controls whether the AD7607 is in normal mode or in one of the two powerdown modes. 10µF STBY 0 0 Power-Down Mode Standby Shutdown RANGE 1 0 Data Sheet AD7607 CONVERSION CONTROL This is accomplished by pulsing the two CONVST pins independently and is possible only if oversampling is not in use. CONVST A is used to initiate simultaneous sampling of the first set of channels (V1 to V4), and CONVST B is used to initiate simultaneous sampling on the second set of analog input channels (V5 to V8), as illustrated in Figure 40. Simultaneous Sampling on All Analog Input Channels The AD7607 allows simultaneous sampling of all analog input channels. All channels are sampled simultaneously when both CONVST pins (CONVST A, CONVST B) are tied together. A single CONVST signal is used to control both CONVST x inputs. The rising edge of this common CONVST signal initiates simultaneous sampling on all analog input channels. On the rising edge of CONVST A, the track-and-hold amplifiers for the first set of channels are placed into hold mode. On the rising edge of CONVST B, the track-and-hold amplifiers for the second set of channels are placed into hold mode. The conversion process begins when both rising edges of CONVST x have occurred; therefore, BUSY goes high on the rising edge of the later CONVST x signal. In Table 3, Time t5 indicates the maximum allowable time between CONVST x sampling points. The AD7607 contains an on-chip oscillator that is used to perform the conversions. The conversion time for all ADC channels is tCONV. The BUSY signal indicates to the user when conversions are in progress, so when the rising edge of CONVST is applied, BUSY goes logic high and transitions low at the end of the entire conversion process. The falling edge of the BUSY signal is used to place all eight track-and-hold amplifiers back into track mode. The falling edge of BUSY also indicates that the new data can now be read from the parallel bus (DB[15:0]), the DOUTA and DOUTB serial data lines, or the parallel byte bus (DB[7:0]). There is no change to the data read process when using two separate CONVST x signals. Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. Simultaneously Sampling Two Sets of Channels The AD7607 also allows the analog input channels to be sampled simultaneously in two sets. This can be used in power-line protection and measurement systems to compensate for phase differences between current and voltage sensors. In a 50 Hz system, this allows for up to 9° of phase compensation; and in a 60 Hz system, it allows for up to 10° of phase compensation. V1 TO V4 TRACK-AND-HOLD ENTER HOLD V5 TO V8 TRACK-AND-HOLD ENTER HOLD CONVST A t5 CONVST B AD7607 CONVERTS ON ALL 8 CHANNELS BUSY tCONV CS/RD V1 V2 V3 V7 V8 08096-040 DATA: DB[15:0] FRSTDATA Figure 40. Simultaneous Sampling on Channel Sets While Using Independent CONVST A and CONVST B Signals—Parallel Interface Mode Rev. B | Page 23 of 32 AD7607 Data Sheet DIGITAL INTERFACE The AD7607 provides three interface options: a parallel interface, a high speed serial interface, and a parallel byte interface. The required interface mode is selected via the PAR/SER/BYTE SEL and the DB15/BYTE SEL pins. Table 8. Interface Mode Selection PAR/SER/BYTE SEL 0 1 1 DB15 0 0 1 Interface Mode Parallel interface mode Serial interface mode Parallel byte interface mode Interface mode operation is discussed in the following sections. PARALLEL INTERFACE (PAR/SER/BYTE SEL = 0) Data can be read from the AD7607 via the parallel data bus with standard CS and RD signals. To read the data over the parallel bus, the PAR/SER/BYTE SEL pin should be tied low. The CS and RD input signals are internally gated to enable the conversion result onto the data bus. The data lines, DB15 to DB0, leave their high impedance state when both CS and RD are logic low. When CS and RD are low, DB15 and DB14 are used to output a sign extended bit of the MSB (DB13) of the conversion result. AD7607 INTERRUPT BUSY 14 DB[15:0] 33:16 DIGITAL HOST 08096-041 CS 13 RD 12 Figure 41. Interface Diagram—One AD7607 Using the Parallel Bus, with CS and RD Shorted Together The rising edge of the CS input signal tristates the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines; it is the function that allows multiple AD7607 devices to share the same parallel data bus. The CS signal can be permanently tied low, and the RD signal can be used to access the conversion results as shown in Figure 4. A read operation of new data can take place after the BUSY signal goes low (see Figure 2); or, alternatively, a read operation of data from the previous conversion process can take place while BUSY is high (see Figure 3). The RD pin is used to read data from the output conversion results register. Applying a sequence of RD pulses to the RD pin of the AD7607 clocks the conversion results out from each channel onto the parallel output bus, DB[15:0], in ascending order. The first RD falling edge after BUSY goes low clocks out the conversion result from Channel V1. The next RD falling edge updates the bus with the V2 conversion result, and so on. The eighth falling edge of RD clocks out the conversion result for Channel V8. When the RD signal is logic low, it enables the data conversion result from each channel to be transferred to the digital host (DSP, FPGA). When there is only one AD7607 in a system/board and it does not share the parallel bus, data can be read using just one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 5. In this case, the data bus comes out of three-state on the falling edge of CS/RD. The combined CS and RD signal allows the data to be clocked out of the AD7607 and to be read by the digital host. In this case, CS is used to frame the data transfer of each data channel. PARALLEL BYTE INTERFACE (PAR/SER/BYTE SEL = 1, DB15 = 1) Parallel byte interface mode operates much like the parallel interface mode, except that each channel conversion result is read out in two 8-bit transfers. Therefore, 16 RD pulses are required to read all eight conversion results from the AD7607. To configure the AD7607 to operate in parallel byte interface mode, the PAR/SER/ BYTE SEL and BYTE SEL/DB15 pins should be tied to logic high (see Table 8). DB[7:0] are used to transfer the data to the digital host. DB0 is the LSB of the data transfer, and DB7 is the MSB of the data transfer. In parallel byte mode, DB14 acts as an HBEN pin. When the DB14/HBEN pin is tied to logic high, the most significant byte (MSB) of the conversion result is output first, followed by the LSB byte of the conversion result. When DB14/HBEN is tied to logic low, the LSB byte of the conversion result is output first, followed by the MSB byte of the conversion result. The FRSTDATA pin remains high until the entire 14 bits of the conversion result from V1 is read. If the MSB byte is always to be read first, the HBEN pin should be set high and remain high. If the LSB byte is always to be read first, the HBEN pin should be set low and remain low. In this circumstance, the MSB byte contains two sign extended bits in the two MSB positions. SERIAL INTERFACE (PAR/SER/BYTE SEL = 1) To read data back from the AD7607 over the serial interface, the PAR/SER/BYTE SEL pin must be tied high. The CS and SCLK signals are used to transfer data from the AD7607. The AD7607 has two serial data output pins, DOUTA and DOUTB. Data can be read back from the AD7607 using one or both of these DOUT lines. For the AD7607, conversion results from Channel V1 to Channel V4 first appear on DOUTA, and conversion results from Channel V5 to Channel V8 first appear on DOUTB. The CS falling edge takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data outputs, DOUTA and DOUTB. The CS input can be held low for the entire serial read, or it can be pulsed to frame each channel read of 14 SCLK cycles. Rev. B | Page 24 of 32 Data Sheet AD7607 Figure 42 shows a read of eight simultaneous conversion results using two DOUT lines on the AD7607. In this case, a 56 SCLK transfer is used to access data from the AD7607, and CS is held low to frame the entire 56 SCLK cycles. Data can also be clocked out using just one DOUT line; in which case, it is recommended that DOUTA be used to access all conversion data because the channel data is output in ascending order. For the AD7607 to access all eight conversion results on one DOUT line, a total of 112 SCLK cycles are required. These 112 SCLK cycles can be framed by one CS signal, or each group of 14 SCLK cycles can be individually framed by the CS signal. The disadvantage of using just one DOUT line is that the throughput rate is reduced if reading occurs after conversion. The unused DOUT line should be left unconnected in serial mode. If DOUTB is to be used as a single DOUT line, the channel results are output in the following order: V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA indicator returns low after V5 is read on DOUTB. Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7607 in serial mode. The SCLK input signal provides the clock source for the serial read operation. The CS goes low to access the data from the AD7607. The falling edge of CS takes the bus out of three-state and clocks out the MSB of the 14-bit conversion result. This MSB is valid on the first falling edge of the SCLK after the CS falling edge. The subsequent 13 data bits are clocked out of the AD7607 on the SCLK rising edge. Data is valid on the SCLK falling edge. To access each conversion result, 14 clock cycles must be provided. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of CS takes FRSTDATA out of three-state and sets the FRSTDATA pin high, indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 14th SCLK falling edge. If all channels are read on DOUTB, the FRSTDATA output does not go high when V1 is output on this serial data output pin. It goes high only when V1 is available on DOUTA (and this is when V5 is available on DOUTB). READING DURING CONVERSION Data can be read from the AD7607 while BUSY is high and the conversions are in progress. This has little effect the performance of the converter, and it allows a faster throughput rate to be achieved. A parallel, parallel byte, or serial read can be performed during conversions and when oversampling is or is not enabled. Figure 3 shows the timing diagram for reading while BUSY is high in parallel or serial mode. Reading during conversions allows the full throughput rate to be achieved when using the serial interface with VDRIVE above 3.3 V. Data can be read from the AD7607 at any time other than on the falling edge of BUSY because this is when the output data registers get updated with the new conversion data. Time t6, as outlined in Table 3, should be observed in this condition. CS 56 DOUTA V1 V2 V3 V4 DOUTB V5 V6 V7 V8 Figure 42. Serial Interface with Two DOUT Lines Rev. B | Page 25 of 32 08096-042 SCLK AD7607 Data Sheet DIGITAL FILTER The AD7607 contains an optional first-order digital sinc filter that should be used in applications where slower throughput rates are used and digital filtering is required. The oversampling ratio of the digital filter is controlled using the oversampling pins, OS[2:0] (see Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control bit. Table 9 lists the oversampling bit decoding to select the different oversample rates. The OS pins are latched on the falling edge of BUSY. This sets the oversampling rate for the next conversion (see Figure 43). Selection of the oversampling mode has the effect of adding a digital filter function after the ADC. The different oversampling rates and the CONVST x sampling frequency produce different digital filter frequency profiles. Table 9. Oversample Bit Decoding Oversampling Ratio No oversampling 2 4 8 16 32 64 Invalid 3 dB BW, 5 V Range (kHz) 15 15 13.7 10.3 6 3 1.5 3 dB BW, 10 V Range (kHz) 22 22 18.5 11.9 6 3 1.5 Maximum Throughput, CONVST Frequency (kHz) 200 100 50 25 12.5 6.25 3.125 CONVST A AND CONVST B CONVERSION N OVERSAMPLE RATE LATCHED FOR CONVERSION N + 1 CONVERSION N + 1 BUSY tOS_HOLD tOS_SETUP 08096-043 OS[2:0] 000 001 010 011 100 101 110 111 OS x Figure 43. OS x Pin Timing Rev. B | Page 26 of 32 Data Sheet AD7607 –10 –20 –30 –40 –50 –60 –30 –70 –40 –80 –50 –90 100 –60 10k 100k 1M 10M Figure 47. Digital Filter Response for Oversampling by 16 0 100k 1M 10M FREQUENCY (Hz) –10 –20 ATTENUATION (dB) Figure 44. Digital Filter Response for Oversampling by 2 0 –10 –20 –30 –40 –50 –60 –30 –70 –40 –80 –50 –90 100 AVCC = VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 32 1k 10k 100k 1M 10M FREQUENCY (Hz) –60 08096-015 10k 08096-011 AVCC = VDRIVE = 5V T = 25°C –80 A ±10V RANGE OS BY 2 –90 100 1k ATTENUATION (dB) 1k FREQUENCY (Hz) –70 Figure 48. Digital Filter Response for Oversampling by 32 –70 0 10k 100k 1M 10M FREQUENCY (Hz) 08096-012 AVCC = VDRIVE = 5V T = 25°C –80 A ±10V RANGE OS BY 4 –90 100 1k –10 –20 ATTENUATION (dB) Figure 45. Digital Filter Response for Oversampling by 4 0 –10 –20 –30 –40 –50 –60 –30 –70 –40 –80 –50 –90 100 –60 AVCC = VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 64 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 49. Digital Filter Response for Oversampling by 64 –70 AVCC = VDRIVE = 5V T = 25°C –80 A ±10V RANGE OS BY 8 –90 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 08096-013 ATTENUATION (dB) AVCC = VDRIVE = 5V TA = 25°C ±10V RANGE OS BY 16 Figure 46. Digital Filter Response for Oversampling by 8 Rev. B | Page 27 of 32 08096-016 ATTENUATION (dB) –20 –10 08096-014 0 0 ATTENUATION (dB) Figure 44 to Figure 49 show the digital filter frequency profiles for the different oversampling ratios. The combination of the analog antialiasing filter and the oversampling digital filter helps to reduce the complexity of the design of the filter before the AD7607. The digital filtering combines steep roll-off and linear phase response. AD7607 Data Sheet 2000 1600 Figure 51 shows that the conversion time extends as the oversampling rate is increased. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY high time. The falling edge of BUSY is used to update the output data registers with the new conversion data; therefore, the reading of conversion data should not occur on this edge. 1400 1200 1000 800 600 400 200 tCYCLE –2 –1 0 1 2 CODE 08096-130 0 CONVST A AND CONVST B Figure 50. Histogram of Codes, Oversampling by 64 tCONV 39µs 19µs If the OS[2:0] pins are set to select an oversampling ratio of 8, for example, the next CONVST x rising edge takes the first sample for each channel. The remaining seven samples for all channels are taken with an internally generated sampling signal. As the oversampling ratio is increased, the 3 dB frequency is reduced and the allowed sampling frequency is also reduced (see Table 9). The OS[2:0] pins should be configured to suit the filtering requirements of the application. The CONVST A and CONVST B pins must be tied/driven together when oversampling is turned on. When the oversampling function is turned on, the BUSY high time for the conversion 4µs BUSY OS = 0 OS = 4 OS = 8 t4 t4 t4 CS RD DATA: DB[15:0] Figure 51. No Oversampling, Oversampling by 4, and Oversampling by 8 Using Read After Conversion Rev. B | Page 28 of 32 08096-044 NUMBER OF OCCURANCES process extends. The actual BUSY high time depends on the oversampling rate that is selected: the higher the oversampling rate, the longer the BUSY high or total conversion time (see Table 3). AVCC = 5V VDRIVE = 5V TA = 25°C 10V RANGE OS64 1800 Data Sheet AD7607 LAYOUT GUIDELINES Figure 52 shows the recommended decoupling on the top layer of the AD7607 board. Figure 53 shows bottom layer decoupling, which is used for the four AVCC pins and the VDRIVE pin. The printed circuit board that houses the AD7607 should be designed so that the analog and digital sections are separated and confined to different areas of the board. At least one ground plane should be used. It can be common or split between the digital and analog sections. In the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7607. Avoid running digital lines under the devices because doing so couples noise onto the die. The analog ground plane should be allowed to run under the AD7607 to avoid noise coupling. Fast switching signals like CONVST A, CONVST B, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. 08096-048 If the AD7607 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at only one point: a star ground point that should be established as close as possible to the AD7607. Good connections should be made to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Figure 52. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins Good decoupling is also important in lowering the supply impedance presented to the AD7607 and in reducing the magnitude of the supply spikes. The decoupling capacitors should be placed close to (ideally, right up against) these pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/REFOUT pin and the REFCAPA and REFCAPB pins as close as possible to their respective AD7607 pins; and, where possible, they should be placed on the same side of the board as the AD7607 device. Rev. B | Page 29 of 32 08096-049 The power supply lines to the AVCC and VDRIVE pins should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make good connections between the AD7607 supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Figure 53. Bottom Layer Decoupling AD7607 Data Sheet To ensure good device-to-device performance matching in a system that contains multiple AD7607 devices, a symmetrical layout between the devices is important. Figure 54 shows a layout with two AD7607 devices. The AVCC supply plane runs to the right of both devices. The VDRIVE supply track runs to the left of the two AD7607 devices. The reference chip is positioned between the two AD7607 devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. These symmetrical layout principles can also be applied to a system that contains more than two AD7607 devices. The AD7607 devices can be placed in a north-south direction with the reference voltage located midway between the AD7607 devices and the reference track running in the north-south direction, similar to Figure 54. AVCC U2 08096-050 U1 Figure 54. Layout for Multiple AD7607 Devices—Top Layer and Supply Plane Layer Rev. B | Page 30 of 32 Data Sheet AD7607 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 55. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7607BSTZ AD7607BSTZ-RL EVAL-AD7607EDZ CED1Z 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Converter Evaluation Development Z = RoHS Compliant Part. Rev. B | Page 31 of 32 Package Option ST-64-2 ST-64-2 AD7607 Data Sheet NOTES ©2010-2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08096-0-1/12(B) Rev. B | Page 32 of 32