5-Bit Programmable Dual Power Supply Controller for Pentium® II Processor ADP3153 a FEATURES 5-Bit Digitally Programmable 1.8 V to 3.5 V Output Voltage Dual N-Channel Synchronous Driver Total Output Accuracy ⴞ1% (0ⴗC to +70ⴗC) High Efficiency Current-Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar On-Board Linear Regulator Controller VRM 8.2 Compatible Narrow Body TSSOP 20-Lead Package GENERAL DESCRIPTION The ADP3153 is a highly efficient synchronous switching regulator controller and a linear regulator controller. The switching regulator controller is optimized for Pentium II and Deschutes Processor applications where 5 V is stepped down to a digitally controlled output voltage between 1.8 V and 3.5 V. Using a 5-bit DAC to read a voltage identification (VID) code directly from the processor, the ADP3153 uses a current mode constant offtime architecture to generate its precise output voltage. The ADP3153 drives two N-channel MOSFETS in a synchronous rectified buck converter, at a maximum switching frequency of 250 kHz. Using the recommended loop compensation and guidelines, the ADP3153 provides a dc/dc converter that meets Intel’s stringent transient specifications with a minimum number of output capacitors and smallest footprint. Additionally, the current mode architecture also provides guaranteed short circuit protection and adjustable current limiting. APPLICATIONS Desktop PC Power Supply for: Pentium II Processor Deschutes Processor Pentium Pro Processor Pentium Processor AMD–K6 Processor VRM Modules The ADP3153’s linear regulator controller drives an external N-channel device. The output voltage is set by the ratio of the external feedback resistors. The controller has been designed for excellent load transient response. VCC +12V 22mF R1 + 1mF VCC SD VIN +5V VIN +5V DRIVE1 CMP R2 CCOMP IRL3103 CIN L 2.5mH ADP3153 SENSE+ VO2 +3.3V 1A IRL2703 VLDO RSENSE 7mV + 1nF CO VO 1.8V–3.5V 14A SENSE– 1000mF 35kV 150pF 10BQ015 DRIVE2 FB 20kV IRL3103 CT PGND AGND VID0–VID4 5-BIT CODE Figure 1. Typical Application Pentium is a registered trademark of Intel Corporation. All other trademarks are the property of their respective holders. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 ADP3153–SPECIFICATIONS (0ⴗC ≤ T ≤ +70ⴗC, V A Parameter CC = 12 V, VIN = 5 V, unless otherwise noted) Symbol Conditions Min VO With Respect to Nominal Output Voltage (Figure 1) –1.0 –1.0 –1.0 OUTPUT VOLTAGE LINE REGULATION ∆VO ILOAD = 10 A (Figure 2) VIN = 4.75 V to 5.25 V 0.05 % OUTPUT VOLTAGE LOAD REGULATION ∆VO (Figure 2) 200 mA < ILOAD < 14 A 0.1 % IQ VSD = 0.8 V TA = +25°C, VSD = 2.0 V 4.1 140 5.5 250 mA µA V11–V 10 V10 Forced to VOUT – 3% 145 165 mV 0.6 V V 220 µA OUTPUT ACCURACY 1.8 V Output Voltage 2.8 V Output Voltage 3.5 V Output Voltage INPUT DC SUPPLY CURRENT Normal Mode Shutdown Typ Max Units 1.0 1.0 1.0 % % % 1 CURRENT SENSE THRESHOLD VOLTAGE VID PINS THRESHOLD Low High V20, V1–V 4 VID PINS INPUT CURRENT I20 , I 1–I4 VID0–VID4 PULL-UP RESISTANCE RVID CT PIN DISCHARGE CURRENT I12 125 2.0 VID = 0 V 110 20 TA = +25°C VOUT in Regulation VOUT = 0 V kΩ 65 2 10 µA µA 2.45 3.2 µs OFFTIME tOFF CT = 150 pF DRIVER OUTPUT TRANSITION TIMES tR, tF CL = 7000 pF (Pins 16, 17) TA = +25°C 120 200 ns POSITIVE POWER GOOD TRIP POINT VPWRGD % Above Output Voltage 5 8 % NEGATIVE POWER GOOD TRIP POINT VPWRGD % Below Output Voltage POWER GOOD RESPONSE TIME tPWRGD CROWBAR TRIP POINT VCROWBAR ERROR AMPLIFIER OUTPUT IMPEDANCE ROERR 145 kΩ ERROR AMPLIFIER TRANSCONDUCTANCE GMERR 2.2 mmho ERROR AMPLIFIER MINIMUM OUTPUT VOLTAGE VCMPMIN V10 Forced to VOUT + 3% 0.8 V ERROR AMPLIFIER MAXIMUM OUTPUT VOLTAGE VCMPMAX V10 Forced to VOUT – 3% 2.4 V ERROR AMPLIFIER BANDWIDTH –3 dB BW ERR CMP = Open 500 kHz LINEAR REGULATOR FEEDBACK CURRENT IFB LINEAR REGULATOR OUTPUT VOLTAGE2 VO2 SHUTDOWN (SD) PIN Low Threshold High Threshold Input Current SDL SDH SDIB % Above Output Voltage 1.8 30 –8 9 Figure 2 RPROG = 35K, R3 = 20K, IO2 = 1 A 3.24 Part Active Part in Shutdown 2.0 –5 % 500 µs 15 24 % 0.35 1 µA 3.30 3.38 V 0.6 V V µA 10 NOTES 1 Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETS. 2 The LDO is tested in a V OUT = 3.3 V configuration with the circuit shown in Figure 2. By selecting a different R PROG value, any output voltage above 1.20 V can be set. All limits at temperature extremes are guaranteed via correlation using standard quality control methods. Specifications are subject to change without notice. –2– REV. 0 ADP3153 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function 1–4, 20 VID1–VID4, VID0 5 6 AGND SD 7 FB 8, 18 9 10 NC VLDO SENSE– 11 SENSE+ 12 13 CT CMP 14 PWRGD 15 16 VCC DRIVE2 Voltage Identification DAC Input Pins. These pins are internally pulled up to VREG providing a logic high if left open. The DAC output range is 600 mV to 1.167 V. Leaving all five DAC inputs open results in placing the ADP3153 into shutdown. Analog Ground Pin. This pin must be routed separately to the (–) terminal of COUT. Shutdown Pin. A logic high will place the ADP3153 in shutdown and disable both outputs. This pin is internally pulled down. This pin is the feedback connection for the linear controller. Connect this pin to the resistor divider network to set the output voltage of the linear regulator. No Connect. Gate Drive for the Linear Regulator N-channel MOSFET. Connects to the internal resistor divider which along with the VID code, sets the output voltage. Pin 10 is also the (–) input for the current comparator. The (+) input for the current comparator. A threshold between Pins 10 and 11 set by the error amplifier in conjunction with RSENSE, sets the current trip point. External Capacitor CT from Pin 12 to ground sets the off time of the device. Error Amplifier Compensation Point. The current comparator threshold increases with the Pin 13 voltage. Power Good Pin. An open drain signal to indicate that the output voltage is within a ± 5% regulation band. Input Voltage Pin. Gate Drive for the Synchronous Rectifier N-channel MOSFET. The voltage at Pin 16 swings from ground to VCC. 17 DRIVE1 Gate Drive for the buck switch N-channel MOSFET. The voltage at Pin 17 swings from ground to VCC. 19 PGND Driver Power Ground. Connects to the source of the bottom N-channel MOSFET onto the (–) terminal of CIN. ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION 20-Lead Thin Shrink Small Outline (TSSOP) (RU-20) Input Supply Voltage (Pin 15) . . . . . . . . . . . . –0.3 V to +16 V Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited Operating Temperature Range . . . . . . . . . . . . . 0°C to +70°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C θJA␣ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C/W Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C ADP3153ARU 0°C to +70°C VID0 PGND VID3 3 18 NC VID4 4 17 DRIVE 1 16 DRIVE 2 TOP VIEW 15 V CC (Not to Scale) 7 14 PWRGD FB Package Option NC 8 13 CMP VLDO 9 12 CT 11 SENSE+ SENSE– 10 NC = NO CONNECT Thin Shrink Small RU-20 Outline (TSSOP) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3153 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 ADP3153 SD 6 ORDERING GUIDE Model 20 19 AGND 5 *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Temperature Package Range Description VID1 1 VID2 2 –3– WARNING! ESD SENSITIVE DEVICE ADP3153 100kV 22V VO2 1 +3.3V 1A 2 RTN 22mF ADP3153 mP SYSTEM IRL2703 1000mF 1 VID1 2 VID2 VID3 NC 18 4 VID4 DRIVE1 17 5 AGND DRIVE2 16 6 SD VCC 15 7 FB PWRGD 14 8 NC CMP 13 9 VLDO SENSE– 10 RPROG 35kV 1mF +5V RTN +12V RTN 19 3 VIN +12V VCC +5V 1mF VID0 20 PGND L2 1.7mH 2700mF 33 (10V) L1 2.5mH IRL3103 2700mF 3 6 (10V) RSENSE 6.7mV VO 1.8V–3.5V 0-14A 10BQ015 IRL3103 RTN R1 150kV R2 39kV CT 12 SENSE+ 11 NC = NO CONNECT R3 20kV 2nF CCOMP CT 150pF 220V 1nF 220V Figure 2. Typical VRM8.2 Compliant Core DC/DC Converter Circuit VCC DRIVE1 DRIVE2 PGND AGND PWRGD 5 14 15 SENSE+ SENSE– 10 11 ADP3153 DELAY REFERENCE VREF +15% NONOVERLAP DRIVE SD 6 2R 9 VLDO CROWBAR FB 1.20V IN OFF VREF +5% VREF –5% VID0 CMPI Q S VT1 1 VID1 2 VID2 3 VID3 4 VID4 R gm VT2 VREF R CMPT OFF-TIME CONTROL VIN DAC SENSE– 12 13 CT CMP Figure 3. Functional Block Diagram –4– REV. 0 Typical Performance Characteristics–ADP3153 100 45 400 VOUT = +3.5V 40 85 VOUT = +2.8V 80 75 FREQUENCY – kHz 350 90 VOUT = +2.0V GATE CHARGE CURRENT – mA 95 EFFICIENCY – % 450 SEE FIGURE 2 300 250 200 150 100 70 50 Figure 4. Efficiency vs. Output Current 30 25 Qn + Qn = 100nC 20 15 10 5 0 50 65 1.4 2.8 4.2 5.6 7.0 8.4 9.8 11.2 12.6 14.0 OUTPUT CURRENT – Amps 35 0 45 100 200 300 400 500 600 700 800 TIMING CAPACITOR – pF Figure 5. Frequency vs. Timing Capacitor SEE FIGURE 2 VOUT = +3.5V, IOUT = 10A 58 83 134 OPERATING FREQUENCY – kHz 397 Figure 6. Gate Charge vs. Supply Current SEE FIGURE 2 PRIMARY N-DRIVE DRIVER OUTPUT OUTPUT VOLTAGE 20mV/DIV VCC = +12V VIN = +5V VOUT = +3.5V I OUT = 10A 1 SECONDARY N-DRIVE DRIVER OUTPUT OUTPUT CURRENT 14A TO 1A 2 DRIVE 1 AND 2 = 5V/DIV 500ns/DIV Figure 7. Gate Switching Waveforms 100ns/DIV 10ms/DIV Figure 8. Driver Transition Waveforms Figure 9. Transient Response, 14 A–1A of Figure 2 Circuit 25 TA = +258C SEE FIGURE 13 VCC VOLTAGE 5V/DIV OUTPUT VOLTAGE 20mV/DIV 3 REGULATOR OUTPUT VOLTAGE 1V/DIV OUTPUT CURRENT 1A TO 14A NUMBER OF PARTS 20 15 10 5 10ms/DIV 10ms/DIV 0 –0.55 –0.5 –0.45 –0.4 –0.35 –0.3 –0.25 –0.2 –0.15 –0.1 –0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 4 OUTPUT ACCURACY – % Figure 10. Transient Response, 1A–14 A of Figure 2 Circuit REV. 0 Figure 11. Power-On Start-Up Waveforms –5– Figure 12. Output Accuracy Distribution ADP3153 Table I. Output Voltage vs. VID Code 12V 5-BIT CODE VCC VID0– VID4 ␣ 1mF ADP3153 SD DRIVE1 DRIVE2 CMP 1kV SENSE+ CT SENSE– 4700pF AGND PGND VOUT 100kV VID4 VID3 VID2 VID1 VID0 VOUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.80 1.85 1.90 1.95 2.00 2.05 Shutdown 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 0.1mF OP27 1.2V 0.1mF Figure 13. Closed-Loop Test Circuit for Accuracy APPLICATION INFORMATION The ADP3153 uses a current-mode, constant-off-time control technique to switch a pair of external N-channel MOSFETs in a synchronous rectified buck converter application. Due to the constant-off-time operation, no slope compensation is needed. A unique feature of the constant-off-time control technique is that the converter’s frequency becomes a function of the ratio of input voltage to output voltage. The off time is determined by the value of the external capacitor connected to the CT pin. The on time varies in such a way that a regulated output voltage is maintained. The output voltage is sensed by an internal voltage divider that is connected to the SENSE– pin. A voltage-error amplifier gm compares the values of the divided output voltage with a reference voltage. The reference voltage is set by an on-board 5-bit DAC, which reads the code present at the voltage identification (VID) pins and converts it to a precise value between 600 mV and 1.167 V. Refer to Table I for the output voltage vs. VID pin code information. To prevent cross conduction of the external MOSFETs, feedback is incorporated to sense the state of the driver output pins. Before the low side drive output can go high, the high side drive output must be low. Likewise, the high side drive output is unable to go high while the low side drive output is high. During continuous-inductor-current mode of operation, the voltage-error amplifier gm and the current comparator CMPI are the main control elements. During the on time of the high side MOSFET, the current comparator CMPI monitors the voltage between the SENSE+ and SENSE– pins. When the voltage level between the two pins reaches the threshold level VT1, the high side drive output is switched to zero, which turns off the high side MOSFET. The timing capacitor CT is now discharged at a rate determined by the off time controller. In order to maintain a ripple current in the inductor, which is independent of the output voltage, the discharge current is made proportional to the value of the output voltage (measured at the SENSE– pin). While the timing capacitor is discharging, the low side drive output goes high, turning on the low side MOSFET. When the voltage level on the timing capacitor has discharged to the threshold voltage level V T2, comparator CMPT resets the SR flip-flop. The output of the flip-flop forces the low side drive output to go low and the high side drive output to go high. As a result, the low side switch is turned off and the high side switch is turned on. The sequence is then repeated. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the voltage-error amplifier, which, in turn, leads to an increase in the current comparator threshold VT1, thus tracking the load current. Power Good The ADP3153 has an internal monitor which monitors the output voltage and drives the PWRGD pin of the device. This pin is an open drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage has been within a ± 5% regulation band of the targeted value for more than 500 µs. The PWRGD pin will go low if the output is outside the regulation band for more than 500 µs. Output Crowbar An added feature of using an N-channel MOSFET as the synchronous switch is the ability to crowbar the output with the same MOSFET. If the output voltage is 15% greater than the desired regulated value, the ADP3153 will turn on the lower MOSFET, which will current-limit the source power supply or blow its fuse, pull down the output voltage, and thus save the expensive microprocessor from destruction. The crowbar function releases at approximately 50% of the nominal output voltage. For example, if the output is programmed to 2.0 V, but is pulled up to 2.3 V or above, the crowbar will turn on the lower MOSFET. If in this case the output is pulled down to less than –6– REV. 0 ADP3153 1.0 V, the crowbar will release, allowing the output voltage to recover to 2.0 V. heavy load, the operating frequency decreases due to the parasitic voltage drops across the power devices. The actual minimum frequency at VO = 2.8 V is calculated to be 160 kHz (see Equation 1 below), where: Shutdown The ADP3153 has a shutdown pin which is pulled logic low by an internal resistor. In this condition the device functions normally. This pin should be pulled high externally to disable the output drives. IIN R IN Calculation of Component Values The design parameters for a typical 300 MHz Pentium II application (Figure 2) are as follows: Input voltage: VIN = 5 V Auxiliary input: VCC = 12 V Output voltage: VO = 2.8 V R DS(ON)HSF Maximum output current: IOMAX = 14.2 Adc RL R DS(ON)LSF R SENSE Minimum output current: IOMIN = 0.8 Adc is the input dc current (assuming an efficiency of 90%, IIN = 9 A) is the resistance of the input filter (estimated value: 7 mΩ) is the resistance of the high side MOSFET (estimated value: 10 mΩ) is the resistance of the low side MOSFET (estimated value: 10 mΩ) is the resistance of the sense resistor (estimated value: 7 mΩ) is the resistance of the inductor (estimated value: 6 mΩ) C O Selection—Determining the ESR The selection of the output capacitor is driven by the required ESR and capacitance CO. The ESR must be small enough that both the resistive voltage deviation due to a step change in the load current and the output ripple voltage stay below the values defined in the specification of the supplied microprocessor. The capacitance, CO, must be large enough that the output is held up while the inductor current ramps up or down to the value corresponding to the new load current. Static tolerance of the supply voltage for the processor core: ∆VOST+ = 100 mV ∆VOST– = –60 mV Transient tolerance (for less than 2 µs) of the supply voltage for the processor core when the load changes between the minimum and maximum values with a di/dt of 30 A/µs: ∆VOTR+ = 130 mV ∆VOTR– = –130 mV The total static tolerance of the Pentium II processor is 160 mV. Taking into account the ±1% setpoint accuracy of the ADP3153, and assuming a 0.5% (or 14 mV) peak-to-peak ripple, the allowed static voltage deviation of the output voltage when the load changes between the minimum and maximum values is 0.08 V. Assuming a step change of ∆I = IOMAX – IOMIN = 13.4 A, and allocating all of the total allowed static deviation to the contribution of the ESR sets the following limit: Input current di/dt when the load changes between the minimum and maximum values: less than 0.1 A/µs The above requirements correspond to Intel’s published power supply requirements based on VRM 8.2 guidelines. C T Selection for Operating Frequency The ADP3153 uses a constant-off-time architecture with tOFF determined by an external timing capacitor CT. Each time the high side N-channel MOSFET switch turns on, the voltage across CT is reset to approximately 3.3 V. During the off time, CT is discharged by a constant current of 65 µA to 2.3 V, that is by 1 V. The value of the off time is calculated from the preferred continuous-mode operating frequency. Assuming a nominal operating frequency of fNOM = 200 kHz at an output voltage of VO = 2.8 V, the corresponding off time is: RE ( MAX ) = ESRMAX 1 = Inductor Selection The minimum inductor value can be calculated from ESR, off time, dc output voltage and allowed peak-to-peak ripple voltage. The timing capacitor can be calculated from the equation: LMIN1 = tOFF × 65 µA CT = = 143 pF 1V V OtOFF RE( MAX ) V RIPPLE , p −p = 2.8 × 2.2 µ × 5.9 m = 2.6 µH 14 m The minimum inductance gives a peak-to-peak ripple current of 2.15 A, or 15% of the maximum dc output current IOMAX. The converter operates at the nominal operating frequency only at the above specified VO and at light load. At higher VO, and REV. 0 = 5.9 mΩ 13. 4 The output filter capacitor must have an ESR of less than 5.9 mΩ. One can use, for example, six FA type capacitors from Panasonic, with 2700 µF capacitance, 10 V voltage rating, and 34 mΩ ESR. The six capacitors have a total typical ESR of ~ 5 mΩ when connected in parallel. VO 1 tOFF = 1– = 2.2 µs V IN f NOM f MIN = 0.08 1 V IN – I IN RIN – IOMAX (RDS(ON )HSF + RSENSE + RL ) –V O × = 160 kHz tOFF V IN – I IN RIN – IOMAX (RDS(ON )HSF + RSENSE + RL – RDS(ON )LSF ) –7– (1) ADP3153 The actual short-circuit current is less than the above calculated ISC(PK) value because the off time rapidly increases when the output voltage drops below 1 V. The relationship between the off time and the output voltage is: The inductor peak current in normal operation is: ILPEAK = IOMAX + IRPP /2 = 15.3 A The inductor valley current is: ILVALLEY = ILPEAK – IRPP = 13 A tOFF ≈ The inductor for this application should have an inductance of 2.6 µH at full load current and should not saturate at the worst-case overload or short circuit current at the maximum specified ambient temperature. A suitable inductor is the CTX12-13855 from Coiltronics, which is 4.4 µH at 1 A and about 2.5 µH at 14.2 A. With a short across the output, the off time will be about 70 µs. During that off time the inductor current gradually decays. The amount of decay depends on the L/R time constant in the output circuit. With an inductance of 2.5 µH and total resistance of 23 mΩ, the time constant will be 108 µs, which yields a valley current of 11.3 A and an average short-circuit current of about 16.3 A. To safely carry the short-circuit current, the sense resistor must have a power rating of at least 16.3 A2 × 6.8 mΩ = 1.8 W. Tips for Selecting Inductor Core Ferrite designs have very low core loss, so the design should focus on copper loss and on preventing saturation. Molypermalloy, or MPP, is a low loss core material for toroids, and it yields the smallest size inductor, but MPP cores are more expensive than cores or the Kool Mµ® cores from Magnetics, Inc. The lowest cost core is made of powdered iron, for example the #52 material from Micrometals, Inc., but yields the largest size inductor. Current Transformer Option An alternative to using low value and high power current sense resistor is to reduce the sensed current by using a low cost current transformer and a diode. The current can then be sensed with a small-size, low cost SMT resistor. If we use a transformer with one primary and 50 secondary turns, the worst-case resistor dissipation is reduced to a fraction of a mW. Another advantage of using this option is the separation of the current and voltage sensing, which makes the voltage sensing more accurate. C O Selection—Determining the Capacitance The minimum capacitance of the output capacitor is determined from the requirement that the output be held up while the inductor current ramps up (or down) to the new value. The minimum capacitance should produce an initial dv/dt which is equal (but opposite in sign) to the dv/dt obtained by multiplying the dt in the inductor and the ESR of the capacitor. CMIN = IOMAX – IOMIN RE (di/dt ) = 14.2 – 0.8 5.9 m (2.2 / 4. 4 µH ) CT × 1V VO + 2 µA 360 kΩ Power MOSFET = 4.5 mF Two external N-channel power MOSFETs must be selected for use with the ADP3153, one for the main switch, and an identical one for the synchronous switch. The main selection parameters for the power MOSFETs are the threshold voltage VGS(TH) and the on resistance RDS(ON). In the above equation the value of di/dt is calculated as the smaller voltage across the inductor (i.e., VIN – VO rather than VO) divided by the maximum inductance (4.4 µH) of the CTX1213855 inductor from Coiltronics. The parallel-connected six 2700 µF/10 V FA series capacitors from Panasonic have a total capacitance of 16,200 µF, so the minimum capacitance is met with ample margin. The minimum input voltage dictates whether standard threshold or logic-level threshold MOSFETs must be used. For VIN > 8 V, standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If VIN is expected to drop below 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. Only logic-level MOSFETs with VGS ratings higher than the absolute maximum of VCC should be used. RSENSE The value of RSENSE is based on the required output current. The current comparator of the ADP3153 has a threshold range that extends from 0 mV to 125 mV (minimum). Note that the full 125 mV range cannot be used for the maximum specified nominal current, as headroom is needed for current ripple, transients and inductor core saturation. The maximum output current IOMAX determines the RDS(ON) requirement for the two power MOSFETs. When the ADP3153 is operating in continuous mode, the simplifying assumption can be made that one of the two MOSFETs is always conducting the average load current. The current comparator threshold sets the peak of the inductor current yielding a maximum output current IOMAX, which equals the peak value less half of the peak-to-peak ripple current. Solving for RSENSE and allowing a margin for tolerances inside the ADP3153 and in the external component values yields: For VIN = 5 V and VO = 2.8 V, the maximum duty ratio of the high side FET is: DMAXHF = (1 – f MIN × tOFF) =(1 – 160 kHz × 2.2 µs) = 65% RSENSE = (125 mV )/[1.2(IOMAX + IRPP /2)] = 6.8 mΩ The maximum duty ratio of the low side (synchronous rectifier) FET is: A practical solution is to use three 20 mΩ resistors in parallel, with an effective resistance of about 6.7 mΩ. DMAXLF = 1 – DMAXHF = 35% The maximum rms current of the high side FET is: Once RSENSE has been chosen, the peak short-circuit current ISC(PK) can be predicted from the following equation: IRMSLS = [DMAXHF (ILVALLEY 2 + ILPEAK2 + ILVALLEY ILPEAK)/3]0.5 = 11.5 Arms ISC(PK) = (145 mV)/R SENSE = (145 mV)/(6.7 mΩ) = 21.5 A –8– REV. 0 ADP3153 The maximum rms current of the low side FET is: [DMAXLF (ILVALLEY2 IRMSLS = = 8.41 Arms 2 + ILPEAK + ILVALLEYILPEAK)/3] All of the above calculated junction temperatures are safely below the 175°C maximum specified junction temperature of the selected FET. 0.5 The maximum operating junction temperature of the ADP3153 is calculated as follows: The RDS(ON) for each FET can be derived from the allowable dissipation. If we allow 5% of the maximum output power for FET dissipation, the total dissipation will be: TJICMAX = TA + θJA (IICVCC + PDR) where θJA is the junction to ambient thermal impedance of the ADP3153 and PDR is the drive power. From the data sheet, θ JA is equal to 110°C/W and IIC = 2.7 mA. PDR can be calculated as follows: PFETALL = 0.05 VO IOMAX = 2 W Allocating two-thirds of the total dissipation for the high side FET and one-third for the low side FET, the required minimum FET resistances will be: PDR = (CRSS + CISS)VCC2 fMAX = 307 mW RDS(ON)HSF(MIN) = 1.33/11.52 = 10 mΩ RDS(ON)LSF(MIN) = 0.67/8.412 = 9.5 mΩ The result is: TJICMAX = 86°C Note that there is a tradeoff between converter efficiency and cost. Larger FETs reduce the conduction losses and allow higher efficiency but lead to increased cost. If efficiency is not a major concern the Fairchild MOSFET NDP6030L or International Rectifier IRL3103 is an economical choice for both the high side and low side positions. Those devices have an R DS(ON) of 14 mΩ at VGS = 10 V and at 25°C. The low side FET is turned on with at least 10 V. The high side FET, however, is turned on with only 12 V – 5 V = 7 V. If we check the typical output characteristics of the device in the data sheet, we find that for an output current of 10 A, and at a VGS of 7 V, the VDS is 0.15 V, which gives a RDS(ON) = VDS/ID = 15 mΩ. This value is only slightly above the one specified at a VGS of 10 V, so the resistance increase due to the reduced gate drive can be neglected. We have to modify, however, the specified RDS(ON) at the expected highest FET junction temperature of 140°C by a RDS(ON) multiplier, using the graph in the data sheet. In our case: C IN Selection and Input Current di/dt Reduction In continuous-inductor-current mode, the source current of the high side MOSFET is a square wave with a duty ratio of VO/ VIN. To keep the input ripple voltage at a low value, one or more capacitors with low equivalent series resistance (ESR) and adequate ripple-current rating must be connected across the input terminals. The maximum rms current of the input bypass capacitors is: ICINRMS ≈ [VO (VIN – VO )]0.5 IOMAX /VIN = 7 Arms Let us select the FA-type capacitor with 2700 µF capacitance and 10 V voltage rating. The ESR of that capacitor is 34 mΩ and the allowed ripple current at 100 kHz is 1.94 A. At 105°C we would need to connect at least four such capacitors in parallel to handle the calculated ripple current. At 50°C ambient, however, the ripple current can be increased, so three capacitors in parallel are adequate. RDS(ON)MULT = 1.7 Using this multiplier, the expected RDS(ON) at 140°C is 1.7 × 14 = 24 mΩ. The ripple voltage across the three paralleled capacitors is: The high side FET dissipation is: To further reduce the effect of the ripple voltage on the system supply voltage bus and to reduce the input-current di/dt to below the recommended maximum of 0.1 A/µs, an additional small inductor (L > 1.7 µH @ 10 A) should be inserted between the converter and the supply bus (see Figure 2). VCINRPL = IOMAX [ESRIN /3 + DMAXHF /(3CIN fMIN )] ⬇ 140 mV p-p PDFETHS = IRMSHS2RDS(ON) + 0.5 VINILPEAKQGf MAX/IG = 3.72 W where the second term represents the turn-off loss of the FET. (In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate current. From the data sheet, QG is about 50 nC – 70 nC and the gate drive current provided by the ADP3153 is about 1 A.) Feedback Loop Compensation Design To keep the peak-to-peak output voltage deviation as small as possible, the low frequency output impedance (i.e., the output resistance) of the converter should be made equal to the ESR of the output capacitor. That can be achieved by having a single-pole roll-off of the voltage gain of the gm error amplifier, where the pole frequency coincides with the ESR zero of the output capacitor. A gain with single-pole roll-off requires that the gm amplifier is terminated by the parallel combination of a resistor and capacitor. The required resistor value can be calculated from the equation: The low side FET dissipation is: PDFETLS = IRMSLS 2R DS(ON) = 1.7 W (Note that there are no switching losses in the low side FET.) To remove the dissipation of the chosen FETs, proper heatsinks should be used. The Thermalloy 6030 heatsink has a thermal impedance of 13°C/W with convection cooling. With this heatsink, the junction-to-ambient thermal impedance of the chosen high side FET θJAHS will be 13 (heatsink-to-ambient) + 2 (junctionto-case) + 0.5 (case-to-heatsink) = 15.5°C/W. 36 × RSENSE ( g m 145 kΩ储RCOMP At full load and at 50°C ambient temperature, the junction temperature of the high side FET is: = RE where gm = 2.2 ms and the quantities 36 and 145 kΩ are characteristic of the ADP3153. The calculated compensating resistance is: TJHSMAX = TA + θJAHS PDFETHS = 105°C R1储R2 = RCOMP = 31 kΩ A smaller heatsink may be used for the low side FET, e.g., the Thermalloy type 7141 (θ = 20.3°C/W). With this heatsink, the TJLSMAX = TA + θJALS PDFETLS = 106°C REV. 0 ) –9– ADP3153 The compensating capacitance is determined from the equality of the pole frequency of the error amplifier gain and the zero frequency of the impedance of the output capacitor. CCOMP = Linear Regulator Design Specifications RE COUT 5 m × 16.2 mF = = 2.6 nF RCOMP 31kΩ In the application circuit we tested, we found that the compensation scheme shown in Figure 2 gave the optimal response to meet the Pentium II dc/dc static and transient specifications with sufficient margins including the ADP3153’s initial error tolerance, the PCB layout trace resistances, and the external component parasitics. If we increase the load resistance to the COMP pin, the static regulation will improve. The load transient response, however, will get worse. In Figure 2, if we decrease the R1 = 150 kΩ resistor vs. the R2 = 39 kΩ resistor, the regulation band will shift positive in relation to the 2.8 V. If we increase the R1 resistor, the regulation band will shift negative. It may be necessary to adjust these resistor values to obtain the best static and dynamic regulation compliance depending on the output capacitor ESR and the parasitic trace resistances of the PCB layout. A detailed design procedure and published conference papers on the optimal compensation are available on ADI’s website (http://www.analog.com). Maximum Ambient Temperature . . . . . . . . . . . TAMB = 50°C Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN = 5 V Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VO2 = 3.3 V Maximum Output Current . . . . . . . . . . . . . . . IO2MAX = 0.5 A Maximum Output Load Transient Allowed . . VTR2 = 0.036 V Chosen FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRX3803 Junction-to-Ambient Thermal Impedance (FET)* θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W *Uses 1 inch square PCB cu-foil as heatsink The output voltage may be programmed by the resistor RPROG as follows: VO2 3.3 RPROG = – 1 × 20 kΩ = – 1 × 20 kΩ = 35 kΩ 1.2 1.2 The current sense resistor may be calculated as follows: RS2 = 0.6 0.6 = = 1.2 Ω IO2 MAX 0.5 The power rating is: ( ) 2 PS2 = RS2 × IO2 MAX × 1.1 = 0.36 W ADP3153 Linear Regulator The ADP3153 linear regulator provides a low cost, convenient, and versatile solution for generating an additional power supply rail that can be programmed between 1.2 V–5 V. The maximum output load current is determined by the size and thermal impedance of an external N-channel power MOSFET that is placed in series with the 5 V supply and controlled by the ADP3153. The output voltage, VO2 in Figure 14, is sensed at the FB pin of the ADP3153 and compared to an internal 1.2 V reference in a negative feedback loop which keeps the output voltage in regulation. Thus, if the load is being reduced or increased, the FET drive will also be reduced or increased by the ADP3153 to provide a well regulated ± 1% accurate output voltage. This accuracy is maintained even if the load changes at the very high rate typical of CPU-type loads. The output voltage is programmed by adjusting the value of the external resistor RPROG shown in Figure 14. Use a 0.5 Ω resistor. The maximum FET junction temperature at shorted output is: TFETMAX = TAMB + θ JA ×VIN × IO2 MAX × 1.1 = 50 + 40 × 5 × 0.5 × 1.1 = 160°C which is within the maximum allowed by the FET's data sheet. The maximum FET junction temperature at nominal output is: ( ) TFETMAX = TAMB + θ JA × VIN –VO2 × IO2 MAX = ( ) 50 + 40 × 5 – 3.3 × 0.5 = 84°C The output filter capacitor maximum allowed ESR is: ESR ~ VTR2/IOMAX = 0.036/0.5 = 0.072 Ω. Features This requirement is met using a 1000 µF/10 V LXV series capacitor from United Chemicon. For applications requiring higher output current, a heatsink and/or a larger MOSFET should be used to reduce the MOSFET’s junction to ambient thermal impedance. • Typical Efficiency: 66% at 3.3 V Output Voltage • Tight DC Regulation Due to 1% Reference and High Gain • Output Voltage Stays Within Specified Limits at Load Current Step with 30 A/µs Slope • Fast Response to Input Voltage or Load Current Transients The design in Figure 14 is for an output voltage, VO2 of 3.3 V with a maximum load current of 0.5 A. Additionally, overcurrent protection is provided by the addition of an external NPN transistor and an external resistor RS2. The design specifications and procedure is given below. VIN = +5V VO2 = 3.3V IO2 = 0.5A ADP3153 RS2 1.1V 2kV VLDO IRX3803 470pF FB 2N2222 1000mF/10V RPROG 35kV 20kV Figure 14. Linear Regulator with Overcurrent Protection –10– REV. 0 ADP3153 BOARD LAYOUT A multilayer PCB is recommended with a minimum of two copper layers. One layer on top should be used for traces interconnecting low power SMT components. The ground terminals of those components should be connected with vias to the bottom traces connecting directly to the ADP3153 ground pins. One layer should be a power ground plane. If four layers are possible, one additional layer should be an internal system ground plane, and one additional layer can be used for other system interconnections. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ADP3153. Board Layout Guidelines 1. The power loop should be routed on the PCB to encompass small areas to minimize radiated switching noise energy to the control circuit and thus to avoid circuit problems caused by noise. This technique also helps to reduce radiated EMI. The power loop includes the input capacitors, the two MOSFETs, the sense resistor, the inductor and the output capacitors. The ground terminals of the input capacitors, the low side FET, the ADP3153 and the output capacitors should be connected together with short and wide traces. It is best to use an internal ground plane. 2. The PGND (power ground) pin of the ADP3153 must return to the grounded terminals of the input and output capacitors and to the source of the low side MOSFET with the shortest and widest traces possible. The AGND (analog ground) pin has to be connected to the ground terminals of the timing capacitor and the compensating capacitor, again with the shortest leads possible, and before it is connected to the PGND pin. 3. The positive terminal of the input capacitors must be connected to the drain of the high side MOSFET. The source terminal of this FET is connected to the drain of the low side FET, (whose source is connected to the ground plane direct) with the widest and shortest traces possible. To kill parasitic ringing at the input of the buck inductor due to parasitic capacitances and inductances, a small (L > 3 mm) ferrite bead is recommended to be placed in the drain lead of the low side FET. Also, to minimize dissipation of the high side FET, a low voltage 1 A Schottky diode can be connected between the input of the buck inductor and the source of the low side FET. 4. The positive terminal of the bypass capacitors of the +12 V supply must be connected to the VIN pin of the ADP3153 with the shortest leads possible. The negative terminals must be connected to the PGND pin of the ADP3153. 5. The sense pins of the ADP3153 must be connected to the sense resistor with as short traces as possible. Make sure that the two sense traces are routed together with minimum separation (<1 mm). The output side of the sense resistor should be connected to the VCC pin(s) of the CPU with as short and wide PCB traces as possible to reduce the VCC voltage drop. (Each square unit of 1 ounce Cu-trace has a resistance of ~0.53 mΩ. At 14 A, each mΩ of PCB trace resistance between current sense resistor output and VCC terminal(s) of the CPU will reduce the regulated output voltage by 14 mV. The filter capacitors to ground at the sense terminals of the IC should be as close as possible (<8 mm) to the ADP3153. The common ground of the optional filter capacitors should be connected to the AGND pin of the ADP3153 with the shortest traces possible (<10 mm). 6. The microprocessor load should be connected to the output terminals of the converter with the widest and shortest traces possible. Use overlapping traces in different layers to minimize interconnection inductance. REV. 0 –11– ADP3153 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Thin Shrink Small Outline (TSSOP) (RU-20) 20 11 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 0.006 (0.15) 0.002 (0.05) PIN 1 0.0256 (0.65) BSC 10 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. 1 SEATING PLANE C3346–3–7/98 0.260 (6.60) 0.252 (6.40) –12– REV. 0