MIC2166 Adaptive On-Time DC-DC Controller Hyper Speed Control™ Family General Description Features The Micrel MIC2166 is a synchronous adaptive on-time buck controller targeting high performance, cost sensitive applications such as set-top boxes, gateways, routers, computing peripherals, and telecom/networking equipment. The MIC2166 operates over a supply range of 4.5V to 28V. It has an internal linear regulator which provides a regulated 5V supply to power the internal control circuitry. MIC2166 operates at a constant 600kHz switching frequency and can be used to drive up to 25A of output current. The output voltage is adjustable down to 0.8V. A unique Hyper Speed Control™ architecture enables ultra-fast transient response while reducing the output capacitance and also makes High VIN/Low VOUT operation possible. A UVLO feature is provided to ensure proper operation under power-sag conditions to prevent the external power MOSFET from over heating. Also, a soft-start feature is provided to reduce the inrush current. Short current sensing on the bottom MOSFET with hiccup mode operation ensures protection in case of an output short circuit. Further, the MIC2166 includes an EN pin to shut down the converter and a PGOOD pin to allow simple sequencing. The MIC2166 is available in a 10 pin MSOP ePad package with a junction operating termperature range from –40 ºC to +125 ºC. All support documentation can be found on Micrel’s web site at: www.micrel.com. • • • • • • • • • • • • • • • Hyper Speed Control™ architecture enables - High delta V operation (VIN=28V and VOUT=0.8V) - Smallest output capacitance Built-in 5V regulator for single-supply operation TM Any Capacitor stable - Zero ESR to high ESR Power-Good output Input voltage range: 4.5V to 28V 5μA typical shutdown current 25A output current drive capability Output down to +0.8V with ±1% accuracy 600kHz switching frequency Internal 5ms digital soft-start Thermal shutdown and hiccup current limit protection No external current-sense resistor required Pre-bias output safe 10-pin MSOP ePad package –40°C to +125°C junction temperature range Applications • • • • Set-top box, gateways, routers and DSL modems Printers, scanners, graphic and video cards Servers, PCs and processor core supply Low-Voltage Distributed Power Typical Application 12V to 3.3V Efficiency 100 90 EFFICIENCY (%) 80 70 60 50 40 30 20 10 0 MIC2166 Adjustable Output 600kHz Buck Converter 0 1 2 3 4 5 6 7 8 9 10 OUTPUT CURRENT (A) MLF and MicroLeadFrame are registered trademarks of Amkor Technology, Inc. Hyper Light Load and Any Capacitor are trademarks of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 2010 M9999-060810-B Micrel, Inc. MIC2166 Ordering Information Part Number Voltage Switching Frequency Junction Temp. Range Package Lead Finish MIC2166YMME Adj. 600kHz –40° to +125°C 10-pin ePad MSOP Pb-Free Pin Configuration 10-Pin ePad MSOP (MME) Pin Description Pin Number Pin Name Pin Function 1 FB 2 PGOOD 3 EN Enable (input): A logic level control of the output. The EN pin is CMOS-compatible. Logic high = enable, logic low = shutdown. In the off state, supply current of the device is greatly reduced (typically 5µA). The EN pin should not be left open. Connect to VIN if sequencing is not required. 4 VIN Supply Voltage: Input voltage for the internal +5V linear regulator. The VIN operating voltage range is from 4.5V to 28V. A 0.1µF capacitor between VIN and the ground is required. 5 VDD 5V Internal Linear Regulator (Output): VDD is the external MOSFET gate drive supply voltage and an internal supply bus for the IC. VDD is created by internal LDO from VIN. When VIN <+5.5V, VDD Should be tied to VIN. A 2.2µF (minimum) ceramic capacitor from VDD to GND is recommended for clean operation. 6 DL Low-Side Gate Drive (output): High-current driver output for external low-side MOSFET. The DL driving voltage swings from ground to VDD. 7 PGND Power Ground. PGND is the ground path for the MIC2166 buck converter power stage. The PGND pin connects to the sources of low-side N-Channel MOSFETs, the negative terminals of input capacitors, and the negative terminals of output capacitors. The loop for the power ground should be as small as possible and separate from the Signal ground (GND) loop. 8 DH High-Side Gate Drive (output): High-current driver output for external high-side MOSFET. The DH driving voltage is floating on the switch node voltage (SW). It swings from ground-to-VDD minus the diode drop. 9 SW Switch Node (input): High current output driver return. The SW pin connects directly to the switch node. Due to the high speed switching on this pin, the SW pin should be routed away from sensitive nodes. Feedback (input): Input to the transconductance amplifier of the control loop. The FB pin is regulated to 0.8V. A resistor divider the output an FB is used to set the desired output voltage. Power Good (Output): Open Drain Output. The PGOOD pin is externally tied with a resistor to VDD. High output when VOUT>90% nominal. Current Sense input (input): SW pin also senses the current by monitoring the voltage across the lowside MOSFET during OFF-time. The current sensing is necessary for short circuit protection. In order to sense the current accurately, connect the low-side MOSFET drain to SW using a Kelvin connection. 10 BST EP GND June 2010 Boost (output): Bootstrapped voltage to the high-side N-channel MOSFET driver. A Schottky diode is connected between the VDD pin and the BST pin. A boost capacitor of 0.1μF is connected between the BST pin and the SW pin. Adding a small resistor at BST pin can slow down the turn-on time of high-side N-Channel MOSFETs. Thermal Pad and Signal ground. GND is the ground path for VDD and the control circuitry. The loop for the signal ground should be separate from the power ground (PGND) loop. 2 M9999-060810-B Micrel, Inc. MIC2166 Absolute Maximum Ratings(1) Operating Ratings(2) VIN to GND ...................................................... -0.3V to +29V VDD, VFB, VPGOOD to GND .................................. -0.3V to +6V VBST to VSW ....................................................... -0.3V to +6V VBST to GND ................................................... -0.3V to +35V VEN to GND.............................................-0.3V to (VIN+0.3V) VDH to VSW ..........................................-0.3V to (VBST + 0.3V) VDL to GND ..........................................-0.3V to (VDD + 0.3V) PGND to GND ............................................... -0.3V to +0.3V Junction Temperature .............................................. +150°C Storage Temperature (TS)..........................-65°C to +150°C Lead Temperature (soldering, 10sec) ........................ 260°C Supply Voltage (VIN) .......................................... 4.5V to 28V Enable Input Voltage (VEN)..................................... 0V to VIN Junction Temperature (TJ) .........................-40°C to +125°C (3) Package Thermal Resistance MSOP-10L ePad (θJA) ......................................77°C/W MSOP-10L ePad (θJC) ......................................10°C/W Electrical Characteristics VIN = VEN= 12V; VBST – VSW = 5V; TJ = 25°C, unless noted. Bold values indicate -40°C ≤ TJ ≤ 125°C. Parameter Condition Min Typ Max Units 28 V 950 1500 µA 5 10 µA Power Input Supply Input Voltage Range (VIN) 4.5 Quiescent Supply Current VFB = 1.5V (non-switching) Shutdown Current VEN = 0V VDD Supply VDD Output Voltage VIN = 7V to 28V, IDD = 40mA 4.8 5.2 5.4 V VDD UVLO Threshold VDD rising 3.7 4.2 4.5 V VDD UVLO Hysteresis Dropout Voltage (VIN - VDD) 400 IDD = 25mA 380 mV 600 mV DC-DC Controller Output-Voltage Adjust Range (VOUT) V 0.8 Reference Feedback Regulation Voltage Load Regulation TJ = 25°C 0.792 0.808 V 0°C ≤ TJ ≤ 85°C 0.788 0.812 V -40°C ≤ TJ ≤ 125°C 0.784 0.816 V IOUT = 0A to 10A 0.8 0.25 % 0.25 % Depends on external components Line Regulation VIN = 4.5V to 28V Depends on external components FB Bias Current Enable Control VFB = 0.8V 50 nA (5) Enable Logic Level High V 1.6 Enable Logic Level Low 0.6 Enable Hysteresis Enable Bias Current June 2010 500 100 VEN = 12V 6 3 V mV 30 µA M9999-060810-B Micrel, Inc. Parameter MIC2166 Condition Min Typ Max Units Switching Frequency 450 600 750 kHz Minimum Off-Time 200 300 400 ns On Timer Maximum Duty Cycle Results from Switching Frequency and Minimum Off-Time 82 % Minimum Duty Cycle VFB = 1.0V 0 % Short Current Protection Current Limit Threshold VFB = 0.79V 98 133 182 mV Short Circuit Current VFB = 0V 24 48 72 mV 0.1 V FET Drives DH, DL Output Low Voltage ISINK = 10mA DH, DL Output High Voltage ISOURCE = 10mA DH On-Resistance Pull Up, ISOURCE = 20mA Pull Down, ISINK = 20mA 2 3 Ω 1.5 3 Ω Pull Up, ISOURCE = 20mA 2 3 Ω Pull Down, ISINK = 20mA 1 DL On-Resistance SW, BST Leakage Current V VDD-0.1V or VBST-0.1V VSW = VBST = 0 2 Ω 30 µA 95 %VOUT %VOUT Power Good Power Good Threshold Voltage Power Good Hysteresis Sweep VFB from Low to High Sweep VFB from High to Low Power Good Delay Time Sweep VFB from Low to High 100 Power Good Low Voltage VFB<0.9 × VNOM, IPGOOD = 1mA 70 TJ Rising 160 °C 15 °C 85 90 6.0 µs 200 mV Thermal Protection Over-temperature Shutdown Over-temperature Shutdown Hysteresis Notes: 1. Exceeding the absolute maximum rating may damage the device. 2. The device is not guaranteed to function outside its operating rating. 3. The maximum allowable power dissipation of any TA (ambient temperature) is PD(max) = (TJ(max) – TA) / θJA. Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown. 4. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5k in series with 100pF. 5. Enable pin should not be left open. June 2010 4 M9999-060810-B Micrel, Inc. MIC2166 Typical Characteristics 12V to 3.3V Efficiency 12V to 1.2V Efficiency 100 1.28 80 1.26 70 70 50 40 30 60 50 40 30 20 20 10 10 0 0 0 1 2 3 4 5 6 7 8 9 OUTPUT VOLTAGE (V) 90 80 60 10 1 2 3 4 5 6 7 8 9 1.18 V IN = 12V 1.16 V OUT = 1.2V 1.10 10 0 Feedback Voltage vs. Temperature 0.812 IOUT = 100mA 1.22 1.20 1.18 IOUT = 10A 1.14 6 8 10 Switching Frequency vs. Load 0.808 0.804 0.800 0.796 0.792 1.12 4 750 SWITCHING FREQUENCY (kHz) FEEDBACK VOLTAGE (V) 1.26 2 OUTPUT CURRENT (A) 1.28 720 690 660 630 600 VIN = 12V VOUT = 2.5V 570 540 510 VIN = 12V 480 VOUT = 2.5V 450 1.10 4 8 12 16 20 24 28 0.788 INPUT VOLTAGE (V) SWITCHING FREQUENCY (kHz) 690 660 630 600 VIN = 12V VOUT = 2.5V 540 510 V IN = 12V 480 40 80 V OUT = 2.5V 450 0 40 80 TEMPERATURE (°C) June 2010 4 6 8 10 OUTPUT CURRENT (A) 160 720 690 660 630 600 570 540 510 IOUT = 5A 480 450 -40 2 120 Switching Frequency vs. Input Voltage 750 720 570 0 TEMPERATURE (ºC) Switching Frequency vs. Temperature 750 0 -40 CURRENT LIMIT THRESHOLD (mV) OUTPUT VOLTAGE (V) 1.20 OUTPUT CURRENT (A) Output Voltage vs. Input Voltage SWITCHING FREQUENCY (kHz) 1.22 1.12 0 1.30 1.16 1.24 1.14 OUTPUT CURRENT (A) 1.24 Output Voltage vs. Load 1.30 90 EFFICIENCY (%) EFFICIENCY (%) 100 120 Current Limit Threshold vs. Feedback Voltage Percentage 140 120 100 80 60 40 20 0 4 8 12 16 20 INPUT VOLTAGE (V) 5 24 28 0 20 40 60 80 100 FEEDBACK VOLTAGE PERCENTAGE (%) M9999-060810-B Micrel, Inc. MIC2166 Typical Characteristics (Continued) Current Limit Threshold vs. Temperature 140 5.4 VFB = 0.79V 500 100 80 VFB = 0V 40 VDD DROPOUT (V) 5.3 120 60 5.2 5.1 5.0 4.9 450 400 350 4.8 4.7 20 300 VIN = 12V IDD = 25mA 4.6 250 0 0 40 80 120 4.5 TEMPERATURE (°C) 0 40 80 0 120 40 80 120 TEMPERATURE (°C) TEMPERATURE (°C) Enable Threshold vs. Input Voltage 1.40 -40 -40 Enable Threshold vs. Temperature 1.5 ENABLE THRESHOLD (V) 1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 Power Good Threshold vs. Temperature 100 POWER GOOD THRESHOLD (%) -40 ENABLE THRESHOLD (V) VDD Dropout vs. Temperature 550 5.5 VDD VOLTAGE (V) CURRENT LIMIT THRESHOLD (mV) 160 VDD vs. Temperature 1.2 0.9 0.6 0.3 97 94 91 88 VIN = 12V 0.95 85 0.0 0.90 4 8 12 16 20 24 -40 28 0 Quiescent Current vs. Input Voltage 1150 80 -40 120 0 990 950 910 870 830 120 VDD Dropout vs. VDD Load 600 80 VDD DROPOUT (mV) SHUTDOWN CURRENT (µA) 1030 80 700 90 1070 40 TEMPERATURE (°C) Shutdown Current vs. Input Voltage 100 1110 QUIESCENT CURRENT (µA) 40 TEMPERATURE (°C) INPUT VOLTAGE (V) 70 60 50 40 30 500 400 300 200 20 100 10 790 0 0 750 4 4 8 12 16 20 24 28 8 12 16 20 INPUT VOLTAGE (V) 24 28 0 5 10 15 20 25 30 35 40 VDD OUTPUT CURRENT (mA) INPUT VOLTAGE (V) June 2010 6 M9999-060810-B Micrel, Inc. MIC2166 Functional Characteristics June 2010 7 M9999-060810-B Micrel, Inc. MIC2166 Functional Characteristics (Continued) June 2010 8 M9999-060810-B Micrel, Inc. MIC2166 Functional Diagram Figure 1. MIC2166 Block Diagram June 2010 9 M9999-060810-B Micrel, Inc. MIC2166 The estimated ON-time method results in a constant switching frequency in the MIC2166. The actual ON-time varies slightly with the different rising and falling times of the external MOSFETs. Therefore, the type of the external MOSFETs and the output load current will modify the actual ON-time and the switching frequency. Also, the minimum TON results in a lower switching frequency in high VIN and low VOUT applications, such as 24V to 1.0V. The minimum TON measured on the MIC2166 evaluation board is about 100ns. During the load transient, the switching frequency is changed due to the varying OFF-time. To illustrate the control loop, the steady-state scenario and the load transient scenario are analyzed. For easy analysis, the gain of the gm amplifier is assumed to be 1. With this assumption, the inverting input of the error comparator is the same as VFB. Figure 2 shows the MIC2166 control loop timing during steady-state operation. During steady-state, the gm amplifier senses VFB ripple, which is proportional to the output voltage (VOUT) ripple and the inductor current ripple, to trigger the ON-time period. The ON-time is predetermined by the estimation. The ending of OFF-time is controlled by VFB. At the valley of VFB ripple, which occurs when VFB falls below VREF, the OFF period ends and the next ON-time period is triggered through the control logic circuitry. Functional Description The MIC2166 is an adaptive on-time buck controller built for low cost and high performance. Featuring an internal 5V linear regulator and PGOOD output, it is designed for a wide input voltage range from 4.5V to 28V, high output power buck converters. An estimated ON-time method is used in the MIC2166 to obtain a constant switching frequency and to simplify the control compensation. Over-current protection is implemented without the use of an external sense resistor. It includes an internal softstart function which reduces the power supply input surge current at start-up by controlling the output voltage rise time. Theory of Operation The MIC2166 is an adaptive on-time buck controller. Figure 1 illustrates the block diagram for the control loop. The output voltage variation will be sensed by the MIC2166 feedback pin FB via the voltage divider. The FB voltage VFB is compared to a 0.8V reference voltage VREF at the error comparator through a low gain transconductance (gm) amplifier at switching frequency. This gm amplifier improves the MIC2166 converter output voltage regulation. If the FB voltage VFB decreases and the output of the gm amplifier is below 0.8V, The error comparator will trigger the control logic and generate an ON-time period, in which DH pin is logic high and DL pin is logic low. The ON-time period length is predetermined by the “Fixed TON Estimator” circuitry: TON(estimated) = VOUT VIN × f sw (1) where VOUT is the output voltage, VIN is the power stage input voltage, and fSW is the switching frequency (600kHz for MIC2166). After an ON-time period, the MIC2166 goes into the OFF-time period, in which DH pin is logic low and DL pin is logic high. The OFF-time period length depends on VFB in most cases. When VFB decreases and the output of the gm amplifier is below 0.8V, the ON-time period is triggered and the OFF-time period ends. If the OFF-time period determined by VFB is less than the minimum OFF time TOFF(min), which is about 300ns typical, then the MIC2166 control logic will apply the TOFF(min) instead. TOFF(min) is required to maintain enough energy in the boost capacitor (CBST) to drive the high-side MOSFET. The maximum duty-cycle is obtained from the 300ns TOFF(min): DMAX = TS − TOFF(min) TS = 1− Figure 2. MIC2166 Control Loop Timing Figure 3 shows the load transient operation of the MIC2166 converter. The output voltage drops due to the sudden load increase, which causes VFB to be less than VREF. This will cause the error comparator to trigger an ON-time period. At the end of the ON-time period, a minimum OFF-time TOFF(min) is generated to charge CBST since VFB is still below VREF. Then, the next ON-time period is triggered due to the low VFB. Therefore, the switching frequency changes during the load transient. With the varying duty-cycle and switching frequency, the output recovery time is fast and the output voltage deviation is small in MIC2166 converter. 300ns TS where TS = 1/fSW. It is not recommended to use MIC2166 with a OFF-time close to TOFF(min) during steady state operation. June 2010 10 M9999-060810-B Micrel, Inc. MIC2166 In each switching cycle of the MIC2166 converter, the inductor current is sensed by monitoring the low-side MOSFET in the OFF period. The sensed voltage is compared with a current-limit threshold voltage VCL after a blanking time of 150ns. If the sensed voltage is over VCL, which is 133mV typical at 0.8V VFB, then the MIC2166 turns off the high-side and low-side MOSFETs and a soft-start sequence is triggered. This mode of operation is called “hiccup mode” and its purpose is to protect the downstream load in case of a hard short. The current limit threshold VCL has a back fold characteristic related to the FB voltage. Please refer to the “Typical Characteristics” for the curve of current limit threshold vs. FB voltage percentage. The circuit in Figure 4 illustrates the MIC2166 current limiting circuit. Figure 3. MIC2166 Load-Transient Response Unlike in current-mode control, the MIC2166 uses the output voltage ripple, which is proportional to the inductor current ripple if the ESR of the output capacitor is large enough, to trigger an ON-time period. The predetermined ON-time makes MIC2166 control loop have the advantage of constant ON-time mode control and eliminates the need for slope compensation. The MIC2166 has its own stability concern: VFB ripple should be in phase with the inductor current ripple and large enough to be sensed by the gm amplifier and the error comparator. The recommended VFB ripple is 20mV~100mV. If a low ESR output capacitor is selected, the VFB ripple may be too small to be sensed by the gm amplifier and the error comparator. Also, the VOUT ripple and the VFB ripple are not in phase with the inductor current ripple if the ESR of the output capacitor is very low. Therefore, ripple injection is required for a low ESR output capacitor. Please refer to “Ripple Injection” subsection in “Application Information” for more details. Figure 4. MIC2166 Current Limiting Circuit Using the typical VCL value of 133mV, the current limit value is roughly estimated as: ICL ≈ For designs where the current ripple is significant compared to the load current IOUT, or for low duty-cycle operation, calculating the current limit ICL should take into account that one is sensing the peak inductor current and that there is a blanking delay of approximately 150ns. Soft-Start Soft-start reduces the power supply input surge current at startup by controlling the output voltage rise time. The input surge appears while the output capacitor is charged up. A slower output rise time will draw a lower input surge current. The MIC2166 implements an internal digital soft-start by making the 0.8V reference voltage VREF ramp from 0 to 100% in about 5ms. Therefore, the output voltage is controlled to increase slowly by a stair-case VREF ramp. Once the soft-start cycle ends, the related circuitry is disabled to reduce current consumption. Current Limit The MIC2166 uses the RDS(ON) of the low-side power MOSFET to sense over-current conditions. This method will avoid adding cost, board space and power losses taken by discrete current sense resistors. The low-side MOSFET is used because it displays much lower parasitic oscillations during switching than the high-side MOSFET. June 2010 133mV RDS(ON) ICL = ΔIL(PP) ×t V 133mV + OUT DLY − R DS(ON) L 2 (2) VOUT × (1 − D) f SW ×L (3) ΔIL(PP) = where: VOUT = The output voltage tDLY = Current limit blanking time, 150ns typical ΔIL(PP) = Inductor current ripple peak-to-peak value D = Duty Cycle fSW = Switching frequency The MOSFET RDS(ON) varies between 30% to 40% with 11 M9999-060810-B Micrel, Inc. MIC2166 temperature; therefore, it is recommended to add 50% margin to ICL in the above equation to avoid false current limiting due to increased MOSFET junction temperature rise. It is also recommended to connect SW pin directly to the drain of the low-side MOSFET to accurately sense the MOSFETs RDS(ON). MOSFET Gate Drive The MIC2166 high-side drive circuit is designed to switch an N-Channel MOSFET. The typical application schematic shows a bootstrap circuit, consisting of D1 (a Schottky diode is recommended) and CBST. This circuit supplies energy to the high-side drive circuit. Capacitor CBST is charged while the low-side MOSFET is on and the voltage on the SW pin is approximately 0V. When the high-side MOSFET driver is turned on, energy from CBST is used to turn the MOSFET on. As the high-side MOSFET turns on, the voltage on the SW pin increases to approximately VIN. Diode D1 is reversed biased and June 2010 CBST floats high while continuing to keep the high-side MOSFET on. The bias current of the high-side driver is less than 10mA so a 0.1μF to 1μF is sufficient to hold the gate voltage with minimal droop for the power stroke (high-side switching) cycle, i.e., ΔBST = 10mA x 1.67μs/0.1μF = 167mV. When the low-side MOSFET is turned back on, CBST is recharged through D1. A small resistor RG at BST pin can be used to slow down the turn-on time of the high-side N-channel MOSFET. The drive voltage is derived from the internal linear regulator VDD. The nominal low-side gate drive voltage is VDD and the nominal high-side gate drive voltage is approximately VDD – VDIODE, where VDIODE is the voltage drop across D1. A dead-time of approximate 30ns delay between the high-side and low-side driver transitions is used to prevent current from simultaneously flowing unimpeded through both MOSFETs. 12 M9999-060810-B Micrel, Inc. MIC2166 Application Information For the Low-Side (LS) MOSFET: MOSFET Selection The MIC2166 controller works from an input voltage of 4.5V to 28V and has an internal 5V VDD supply to provide power to turn the external N-Channel power MOSFETs for the high-side and low-side switches. For applications where VIN < 5.5V, it is recommended to connect VDD-to-VIN to bypass the internal linear regulator. The external power MOSFETs should be logic-level MOSFETs, whose operation is specified at VGS = 4.5V. There are different criteria for choosing the high-side and low-side MOSFETs. These differences are more significant at lower duty cycles such as 24V to 1.2V conversion. In such an application, the high-side MOSFET is required to switch as quickly as possible to minimize transition losses, whereas the low-side MOSFET can switch slower, but must handle larger RMS currents. When the duty-cycle approaches 50%, the on-resistance of the high-side MOSFET starts to become critical. It is important to note that the on-resistance of a MOSFET increases with increasing temperature. For a MOSFET with a 0.4%/°C thermal coefficient a 75°C rise in junction temperature will increase the channel resistance of the MOSFET by 30% of the resistance specified at 25°C. This change in resistance must be accounted for when calculating MOSFET power dissipation and the value of current limit. Total gate charge is the charge required to turn the MOSFET on and off under specified operating conditions (VDS and VGS). The gate charge is supplied by the MIC2166 gatedrive circuit. At 600kHz switching frequency, the gate charge can be a significant source of power dissipation in the MIC2166. At light output load, this power dissipation is noticeable as a reduction in efficiency. The average current required to drive the high-side MOSFET is: IG[HS] (avg) = Q G × f SW IG[LS] (avg) = C ISS × VGS × f SW Since the current from the gate drive comes from the VDD, which is the output of the internal linear regulator power by VIN, the power dissipated in the MIC2166 due to gate drive is: PGATEDRIVE = VIN × (IG[high-side] (avg) + IG[low -side] (avg)) (6) A convenient figure of merit for switching MOSFETs is the on-resistance times the total gate charge (RDS(ON) × QG). Lower numbers translate into higher efficiency. Low gate-charge logic-level MOSFETs are a good choice for use with the MIC2166. Also, the RDS(ON) of the low-side MOSFET will determine the current limit value. Please refer to “Current Limit” subsection is “Functional Description” for more details. Parameters that are important to MOSFET switch selection are: • Voltage rating • On-resistance • Total gate charge The voltage ratings for the high-side and low-side MOSFETs are essentially equal to the power stage input voltage VIN. A safety factor of 20% should be added to the VDS(max) of the MOSFETs to account for voltage spikes due to circuit parasitic elements. The power dissipated in the MOSFETs is the sum of the conduction losses during the on-time (PCONDUCTION) and the switching losses during the period of time when the MOSFETs turn on and off (PAC). PSW = PCONDUCTION + PAC (7) PCONDUCTION = ISW(RMS) 2 × R DS(ON) PAC = PAC(off ) + PAC(on) (8) (9) where: RDS(ON) = on-resistance of the MOSFET switch D = Duty Cycle = VOUT / VIN Making the assumption that the turn-on and turn-off transition times are equal; the transition times can be approximated by: (4) where: IG[HS](avg) = Average High-Side (HS) MOSFET gate current QG = Total gate charge for the high-side MOSFET taken from the manufacturer’s data sheet for VGS = VDD. fSW = Switching Frequency The low-side MOSFET is turned on and off at VDS = 0V because an internal body diode or external freewheeling diode is conducting during this time. The switching loss for the low-side MOSFET is usually negligible. Also, the gate-drive current for the low-side MOSFET is more accurately calculated using CISS at VDS = 0 instead of gate charge. June 2010 (5) tT = C ISS × VDD + C OSS × VIN IG (10) where: CISS and COSS are measured at VDS = 0 IG = gate-drive current The total high-side MOSFET switching loss is: PAC = (VIN + VD ) × IPK × t T × f SW 13 (11) M9999-060810-B Micrel, Inc. MIC2166 Lower cost iron powder cores may be used but the increase in core loss will reduce the efficiency of the power supply. This is especially noticeable at low output power. The winding resistance decreases efficiency at the higher output current levels. The winding resistance must be minimized although this usually comes at the expense of a larger inductor. The power dissipated in the inductor is equal to the sum of the core and copper losses. At higher output loads, the core losses are usually insignificant and can be ignored. At lower output currents, the core losses can be a significant contributor. Core loss information is usually available from the magnetics vendor. Copper loss in the inductor is calculated by the equation below: 2 PINDUCTORCu=IL(RMS) × RWINDING (16) The resistance of the copper wire, RWINDING, increases with the temperature. The value of the winding resistance used should be at the operating temperature. RWINDING = RWINDING(20°C) × (1+ 0.0042 × (TH – T20°C)) (17) where: TH = temperature of wire under full load T20°C = ambient temperature RWINDING(20°C) = room temperature winding resistance (usually specified by the manufacturer) where: tT = Switching transition time VD = Diode drop fSW = Switching Frequency The high-side MOSFET switching losses increase with the switching frequency and the input voltage VIN. The low-side MOSFET switching losses are negligible and can be ignored for these calculations. Inductor Selection Values for inductance, peak, and RMS currents are required to select the output inductor. The input and output voltages and the inductance value determine the peak-to-peak inductor ripple current. Generally, higher inductance values are used with higher input voltages. Larger peak-to-peak ripple currents will increase the power dissipation in the inductor and MOSFETs. Larger output ripple currents will also require more output capacitance to smooth out the larger ripple current. Smaller peak-to-peak ripple currents require a larger inductance value and therefore a larger and more expensive inductor. A good compromise between size, loss and cost is to set the inductor ripple current to be equal to 20% of the maximum output current. The inductance value is calculated by the equation below. L= ( VOUT × VΙΝ(max) − VOUT ) VΙΝ(max) × f SW × 20% × IOUT(max) Output Capacitor Selection The type of the output capacitor is usually determined by its ESR (equivalent series resistance). Voltage and RMS current capability are two other important factors for selecting the output capacitor. Recommended capacitors are tantalum, low-ESR aluminum electrolytic, OS-CON, POSCAPS, and ceramic. The output capacitor’s ESR is usually the main cause of the output ripple. The output capacitor ESR also affects the control loop from a stability point of view. The maximum value of ESR is calculated: (12) where: fSW = switching frequency 20% = ratio of AC ripple current to DC output current VIN(max) = maximum power stage input voltage The peak-to-peak inductor current ripple is: ΔIL(PP ) = VOUT × ( VIN(max) − VOUT ) VIN(max) × f SW × L (13) ESR COUT ≤ The peak inductor current is equal to the average output current plus one half of the peak-to-peak inductor current ripple. IL(PK) = IOUT(max) + 0.5 × ΔIL(PP) 2 IL(RMS) = IOUT(max) + ΔIL(PP)2 12 (15) 2 ( ΔIL(PP) ⎞ ⎛ ⎟ + ΔIL(PP) × ESR C ΔVOUT(PP) = ⎜⎜ ⎟ OUT ⎝ COUT × fSW × 8 ⎠ Maximizing efficiency requires the proper selection of core material and minimizing the winding resistance. The high frequency operation of the MIC2166 requires the use of ferrite materials for all but the most cost sensitive applications. June 2010 (18) ΔIL(PP) where: ΔVOUT(PP) = peak-to-peak output voltage ripple ΔIL(PP) = peak-to-peak inductor current ripple The total output ripple is a combination of the ESR and output capacitance. The total ripple is calculated below: (14) The RMS inductor current is used to calculate the I R losses in the inductor. 2 ΔVOUT(pp) )2 (19) where: C = output capacitance value fSW = switching frequency OUT 14 M9999-060810-B Micrel, Inc. MIC2166 As described in the “Theory of Operation” subsection in “Functional Description”, MIC2166 requires at least 20mV peak-to-peak ripple at the FB pin to make the gm amplifier and the error comparator to behavior properly. Also, the output voltage ripple should be in phase with the inductor current. Therefore, the output voltage ripple caused by the output capacitor COUT should be much smaller than the ripple caused by the output capacitor ESR. If low ESR capacitors, such as ceramic capacitors, are selected as the output capacitors, a ripple injection method should be applied to provide the enough FB voltage ripples. Please refer to the “Ripple Injection” subsection for more details. The voltage rating of the capacitor should be twice the output voltage for a tantalum and 20% greater for aluminum electrolytic or OS-CON. The output capacitor RMS current is calculated below: ICOUT (RMS) = ΔIL(PP) 12 Figure 5. Voltage-Divider Configuration The output voltage is determined by the equation: R1 ) (25) R2 where VREF = 0.8V. If R1 is too large, it may allow noise to be introduced into the voltage feedback loop. If R1 is too small in value, it will decrease the efficiency of the power supply, especially at light loads. The total voltage divider resistance R1+R2 is recommended to be 7.5kΩ. Once R1 is selected, R2 can be calculated using: VOUT = VREF × (1 + (20) The power dissipated in the output capacitor is: PDISS(COUT ) = ICOUT (RMS) 2 × ESR COUT (21) R2 = Input Capacitor Selection The input capacitor for the power stage input VIN should be selected for ripple current rating and voltage rating. Tantalum input capacitors may fail when subjected to high inrush currents, caused by turning on a “hotplugging”. A tantalum input capacitor’s voltage rating should be at least two times the maximum input voltage to maximize reliability. Aluminum electrolytic, OS-CON, and multilayer polymer film capacitors can handle the higher inrush currents without voltage de-rating. The input voltage ripple will primarily depend upon the input capacitor’s ESR. The peak input current is equal to the peak inductor current, so: ΔVIN = IL(PK ) × ESR CIN ID(avg)CM = IOUT × 2 × 30ns × f SW VDIODE(rrm) = VIN The power dissipated by the Schottky diode is: PDIODE = ID(avg) × VF (28) where, VF = forward voltage at the peak diode current. An external Schottky diode is recommended, even though the low-side MOSFET contains a parasitic body diode since the Schottky diode has much less forward voltage than the body diode. The external diode will improve efficiency and reduce the high frequency noise. If the MOSFET body diode is used, it must be rated to handle the peak and average current. The body diode has a relatively slow reverse recovery time and a relatively high forward voltage drop. The power lost in the diode is proportional to the forward voltage drop of the diode. As the high-side MOSFET starts to turn on, (23) (24) Voltage Setting Components The MIC2166 requires two resistors to set the output voltage, as shown in Figure 5. June 2010 (27) The reverse voltage requirement of the diode is: (22) The power dissipated in the input capacitor is: PDISS(CIN ) = ICIN (RMS) 2 × ESR CIN (26) External Schottky Diode (Optional) An external freewheeling diode can be used to keep the inductor current flow continuous while both MOSFETs are turned off. The diode conducts current during the dead-time. The dead-time prevents current from flowing unimpeded through both MOSFETs and is typically 30ns. The diode conducts twice during each switching cycle. Although the average current through this diode is small, the diode must be able to handle the peak current. The input capacitor must be rated for the input current ripple. The RMS value of input capacitor current is determined at the maximum output current. Assuming the peak-to-peak inductor current ripple is low: ICIN (RMS) ≈ IOUT(max) × D × (1 − D) VREF × R1 VOUT − VREF 15 M9999-060810-B Micrel, Inc. MIC2166 the body diode becomes a short circuit for the reverse recovery period, dissipating additional power. The diode recovery and the circuit inductance will cause ringing during the high-side MOSFET turn-on. An external Schottky diode conducts at a lower forward voltage preventing the body diode in the MOSFET from turning on. The lower forward voltage drop dissipates less power than the body diode. The lack of a reverse recovery mechanism in a Schottky diode causes less ringing and less power loss. LSTRAY1 RDS LSTRAY3 LSTRAY2 Figure 7. Snubber Circuit The snubber components should be placed as close as possible to the low-side MOSFET and/or external schottky diode since it contributes to most of the stray capacitance. Placing the snubber too far from the MOSFET or using a trace that is too long or thin will add inductance to the snubber and diminishes its effectiveness. A proper snubber design requires that the parasitic inductance and capacitance be known. A method of determining these values and calculating the damping resistor value is outlined below. 1. Measure the ringing frequency at the switch node which is determined by parasitic LP and CP. Define this frequency as f1. 2. Add a capacitor CS (such as 2 times as big as the COSS of the FET) from the switch node to ground and measure the new ringing frequency. Define this new (lower) frequency as f2. LP and CP can now be solved using the values of f1, f2 and CS. 3. Add a resistor RS in series with CS to generate critical damping. Step 1: First measure the ringing frequency on the switch node voltage when the high-side MOSFET turns on. This ringing is characterized by the equation: L Q1 CIN VDC LSTRAY3 Sync_buck Controller Q2 COSS2 COUT LSTRAY4 – Figure 6. Output Parasitics One method of reducing the ringing is to use a resistor and capacitor to lower the Q of the resonant circuit, as shown in Figure 7. Capacitor CS is used to block DC and minimize the power dissipation in the resistor. This capacitor value should be between 2 and 10 times the parasitic capacitance of the MOSFET COSS. A capacitor that is too small will have high impedance and prevent the resistor from damping the ringing. A capacitor that is too large causes unnecessary power dissipation in the resistor, which lowers efficiency. June 2010 CS LSTRAY4 COSS1 LSTRAY1 RS COSS2 Snubber Design A snubber is used to damp out high frequency ringing caused by parasitic inductance and capacitance in the buck converter circuit. Figure 6 shows a simplified schematic of the buck converter. Stray capacitance consists mostly of the two MOSFETs’ output capacitance (COSS). The stray inductance consists mostly package inductance and trace inductance. The arrows show the resonant current path when the high side MOSFET turns on. This ringing causes stress on the semiconductors in the circuit as well as increased EMI. + LSTRAY2 f1 = 1 2π L P × C P (29) where CP and LP are the parasitic capacitance and inductance. Step 2: Add a capacitor, CS, in parallel with the synchronous MOSFET, Q2. The capacitor value should be approximately 2 times the COSS of Q2. Measure the frequency of the switch node ringing, f2: 16 M9999-060810-B Micrel, Inc. MIC2166 1 f2 = 2π Lp × (Cs + Cp) ΔVFB(pp) = (30) (36) where ΔVOUT = ESR COUT ⋅ ΔIL (PP) , ΔIL(PP) is the peak- Define f’ as: f' = to-peak value of the inductor current ripple. 2) Inadequate ripple at VOUT due to the small ESR of the output capacitors. The output voltage ripple is fed into the FB pin through a feedforward capacitor Cff in this situation, as shown in Figure 8b. The typical Cff value is between 1nF and 100nF. With the feedforward capacitor, VFB ripple is very close to the output voltage ripple: f1 f2 Combining the equations for f1, f2 and f’ to derive CP, the parasitic capacitance: CP = CS ' 2 (31) (f ) − 1 LP is solved by re-arranging the equation for f1: LP = 1 (2π)2 × CP × ( f1 ) 2 ΔVFB(pp) ≈ ΔVOUT (32) Q = RS × CP =1 LP (33) Solving for RS RS = LP Cp ΔVFB(PP) = VIN × K div × D × (1 - D) × (34) K div = Figure 7 shows the snubber in the circuit and the damped switch node waveform. The snubber capacitor, CS, is charged and discharged each switching cycle. The energy stored in CS is dissipated by the snubber resistor, RS, two times per switching period. This power is calculated in the equation below: PSNUBBER = fSW × CS × VIN2 (37) 3) Virtually no ripple at VOUT due to the very low ESR of the output capacitors. In this situation, the output voltage ripple is less than 20mV. Therefore, additional ripple is injected into the FB pin from the switching node SW via a resistor Rinj and a capacitor Cinj, as shown in Figure 8c. The injected ripple is: Step 3: Calculate the damping resistor. Critical damping occurs at Q = 1: 1 f SW × τ R1//R2 R inj + R1//R2 (38) (39) where: VIN = Power stage input voltage at VIN pin D = Duty Cycle fSW = switching frequency τ = (R1 // R2 // R inj ) ⋅ C ff (35) In equations (38) and (39), it is assumed that the time constant associated with Cff must be much greater than the switching period: Ripple Injection The VFB ripple required for proper operation of the MIC2166 gm amplifier and error comparator is 20mV to 100mV. However, the output voltage ripple is generally designed as 1% to 2% of the output voltage. For a low output voltage, such as a 1V, the output voltage ripple is only 10mV to 20mV, and the VFB ripple is less than 20mV. If the VFB ripple is so small that the gm amplifier and error comparator cannot sense it, the MIC2166 will lose control and the output voltage is not regulated. In order to have some amount of VFB ripple, a ripple injection method is applied for low output voltage ripple applications. The applications are divided into three situations according to the amount of the VFB ripple: 1) Enough ripple at VOUT due to the large ESR of the output capacitors. As shown in Figure 8a, the converter is stable without any ripple injection. The VFB ripple is: June 2010 R2 × ΔVOUT R1 + R2 1 f SW × τ = T << 1 τ If the voltage divider resistors R1 and R2 are in the kΩ range, a Cff of 1nF to 100nF can easily satisfy the large time constant consumption. Also, a 100nF injection capacitor Cinj is used in order to be considered as short for a wide range of the frequencies. 17 M9999-060810-B Micrel, Inc. MIC2166 The process of sizing the ripple injection resistor and capacitors is: Step 1. Select Cff to feed all output ripples into the feedback pin and make sure the large time constant assumption is satisfied. Typical choice of Cff is 1nF to 100nF if R1 and R2 are in kΩ range. Step 2. Select Rinj according to the expected feedback voltage ripple. According to the equation (38), Figure 8a. R2 × ΔVOUT > 20mV R1 + R2 K div = ΔVFB(PP ) VIN × f SW × τ D × (1 − D) (40) Then the value of Rinj is obtained as: R inj = (R1 // R2) × ( 1 K div − 1) (41) Step 3. Select Cinj as 100nF, which could be considered as short for a wide range of the frequencies. Figure 8b. R2 × ΔVOUT < 20mV and ΔVOUT > 20mV R1 + R2 Figure 8c. ΔVOUT < 20mV June 2010 18 M9999-060810-B Micrel, Inc. MIC2166 Inductor PCB Layout Guidelines Warning!!! To minimize EMI and output noise, follow these layout recommendations. PCB Layout is critical to achieve reliable, stable and efficient performance. A ground plane is required to control EMI and minimize the inductance in power, signal and return paths. The following guidelines should be followed to insure proper operation of the MIC2166 converter. IC • Place the IC and MOSFETs close to the point of load (POL). • Use fat traces to route the input and output power lines. • Signal and power grounds should be kept separate and connected at only one location. • The exposed pad (ePad) on the bottom of the IC must be connected to the ground through several vias. • The feedback resistors should be placed close to the FB pin. The top feedback resistor should connect directly to the output node. Run this trace away from the switch node (SW). Keep the inductor connection to the switch node (SW) short. • Do not route any digital lines underneath or close to the inductor. • Keep the switch node (SW) away from the feedback (FB) pin. • The SW pin should be connected directly to the drain of the low-side MOSFET to accurate sense the voltage across the low-side MOSFET. • To minimize noise, place a ground plane underneath the inductor. Output Capacitor The 10µF ceramic capacitor, which connects to the VDD terminal, must be located next to the IC. The VDD terminal is very noise sensitive and placement of the capacitor is very critical. Use wide traces to connect the VDD and PGND pins. • • • Use a wide trace to connect the output capacitor ground terminal to the input capacitor ground terminal. • Phase margin will change as the output capacitor value and ESR changes. Contact the factory if the output capacitor is different from what is shown in the BOM. • The feedback trace should be separate from the power trace and connected as close as possible to the output capacitor. Sensing a long high current load trace can degrade the DC load regulation. Schottky Diode • Place the Schottky diode on the same side of the board as the MOSFETs and VIN input capacitor. • The connection from the Schottky diode’s Anode to the input capacitors ground terminal must be as short as possible. Input Capacitor • Place the VIN input capacitor next. • • Place the VIN input capacitors on the same side of the board and as close to the MOSFETs as possible. • • Keep both the VIN and PGND connections short. • Place several vias to the ground plane close to the VIN input capacitor ground terminal. • Use either X7R or X5R dielectric input capacitors. Do not use Y5V or Z5U type capacitors. • Do not replace the ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor. • If a Tantalum input capacitor is placed in parallel with the input capacitor, it must be recommended for switching regulator applications and the operating voltage must be derated by 50%. • In “Hot-Plug” applications, a Tantalum or Electrolytic bypass capacitor must be used to limit the overvoltage spike seen on the input supply with power is suddenly applied. June 2010 The diode’s Cathode connection to the switch node (SW) must be keep as short as possible. RC Snubber Place the RC snubber on the same side of the board and as close to the MOSFETs as possible. MOSFETs 19 • Low-side MOSFET gate drive trace (DL pin to MOSFET gate pin) must be short and routed over a ground plane. The ground plane should be the connection between the MOSFET source and PGND. • Chose a low-side MOSFET with a high CGS/CGD ratio and a low internal gate resistance to minimize the effect of dv/dt inducted turn-on. • Do not put a resistor between the LSD output and the gate of the low-side MOSFET. • Use a 4.5V VGS rated MOSFET. Its higher gate threshold voltage is more immune to glitches than a 2.5V or 3.3V rated MOSFET. MOSFETs that are rated for operation at less than 4.5V VGS should not be used. M9999-060810-B Micrel, Inc. MIC2166 Evaluation Board Schematic Figure 9. Schematic of MIC2166 8V-24V to 1.2V/10A Evaluation Board June 2010 20 M9999-060810-B Micrel, Inc. MIC2166 Bill of Materials Item C1 C2,C3 Part Name B41125A7227M C7 12105C475KAZ2A AVX 06035C104KAT2A TDK C1608X7R1H102K 06035C472KAT2A GRM188R71H472KA01D C13 D1 AVX AVX TDK AVX Murata AVX SD103BWS 1nF Ceramic Capacitor, X7R, Size 0603, 50V Murata 12106D107MAT2A SD103BWS-7 10µF Ceramic Capacitor, X5R, Size 0805, 10V Murata TDK 6SEPC560MX 0.1µF Ceramic Capacitor, X7R, Size 0603, 50V (5) C1608X7R1H472K GRM32ER60J107ME20L C15 AVX C1608X7R1H104K 06035C102KAT2A 4.7µF Ceramic Capacitor, X7R, Size 1210, 50V (4) Murata GRM188R71H102KA01D C12 Murata Qty 220µF Aluminum Capacitor, SMD, 35V (3) GRM188R71H104KA93D 0805ZD106KAT2A Description (1) (2) Vishay GRM21BR61A106KE19L C11 EPCOS 222215095001E3 GRM32ER71H475KA88L C6,C8,C10 Manufacturer Murata (6) SANYO Diodes Inc Vishay Cooper Bussmann Q1 FDS6298 Fairchild (9) Q2 FDS8672S Fairchild (9) R1,R14 CRCW06032R21FKEA R2 R3 (8) 3 1 1 1 100µF Ceramic Capacitor, X5R, Size 1210, 6.3V 1 560µF OSCON Capacitor, 6.3V 1 1 Small Signal Schottky Diode HCF1305-1R0-R 2 4.7nF Ceramic Capacitor, X7R, Size 0603, 50V (7) L1 1 1.0µH Inductor, 24A Saturation Current 1 30V, 13A N-Channel MOSFET 12mΩ Rds(on) @ 4.5V 1 30V, 18A N-Channel MOSFET 7mΩ Rds(on) @ 4.5V 1 Vishay/Dale 2.21Ω Resistor, Size 0603, 1% 2 CRCW08051R21FKEA Vishay/Dale 1.21Ω Resistor, Size 0805, 1% 1 CRCW060319K6FKEA Vishay/Dale 19.6kΩ Resistor, Size 0603, 1% 1 R4 CRCW06032K49FKEA Vishay/Dale 2.49kΩ Resistor, Size 0603, 1% 1 R5 CRCW06034K99FKEA Vishay/Dale 4.99kΩ Resistor, Size 0603, 1% 1 R13* CRCW06030000Z0EA Vishay/Dale 0Ω Resistor, Size 0603, 1% 1 R15,R16 CRCW060310K0FKEA Vishay/Dale 10kΩ Resistor, Size 0603, 1% 2 R17* CRCW060349R9FKEA Vishay/Dale 49.9Ω Resistor, Size 0603, 1% 1 U1 MIC2166YMME 600kHz Buck Controller 1 (10) Micrel, Inc. *R13 and R17 are for test purpose only. June 2010 21 M9999-060810-B Micrel, Inc. MIC2166 Notes: 1. EPCOS: www.epcos.com 2. Vishay: www.vishay.com 3. AVX: www.avx.com 4. MuRata: www.murata.com 5. TDK: www.tdk.com 6. Sanyo: www.sanyo.com 7. Diode Inc.: www.diodes.com 8. Cooper Bussmann: www.cooperbussmann.com 9. Fairchild: www.fairchildsemi.com 10. Micrel, Inc: www.micrel.com June 2010 22 M9999-060810-B Micrel, Inc. MIC2166 PCB Layout Figure 10. MIC2166 10A Evaluation Board Top Layer Figure 11. MIC2166 10A Evaluation Board Bottom Layer June 2010 23 M9999-060810-B Micrel, Inc. MIC2166 Figure 12. MIC2166 10A Evaluation Board Mid-Layer 1 (GND Plane) Figure 13. MIC2166 10A Evaluation Board Mid-Layer 2 June 2010 24 M9999-060810-B Micrel, Inc. MIC2166 Package Information 10-Pin ePad MSOP (MME) June 2010 25 M9999-060810-B Micrel, Inc. MIC2166 Recommended Landing Pattern MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2010 Micrel, Incorporated. June 2010 26 M9999-060810-B