LTC3714 Intel Compatible, Wide Operating Range, Step-Down Controller with Internal Op Amp DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ True Current Mode with Ultrafast Transient Response Stable with Ceramic COUT tON(MIN) < 100ns for Operation from High Input Ranges Supports Active Voltage Positioning No Sense Resistor Required 5-Bit VID Programmable Output Voltage: 0.6V to 1.75V Dual N-Channel MOSFET Synchronous Drive Programmable Output Offsets Power Good Output Voltage Monitor Wide VIN Range: 4V to 36V ±1% 0.6V Reference Adjustable Frequency Programmable Soft-Start Output Overvoltage Protection Optional Short-Circuit Shutdown Timer Forced Continuous Control Pin Logic Controlled Micropower Shutdown: IQ ≤ 30µA Available in 0.209" Wide 28-Lead SSOP Package U APPLICATIO S ■ ■ Power Supply for Mobile Pentium® Processors and Transmeta Processors Notebook and Portable Computers The LTC®3714 is a synchronous step-down switching regulator controller for CPU power. An output voltage between 0.6V and 1.75V is selected by a 5-bit code (Intel mobile VID specification). The controller uses a constant on-time, valley current control architecture to deliver very low duty cycles without requiring a sense resistor. Operating frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. Discontinuous mode operation provides high efficiency operation at light loads. A forced continuous control pin reduces noise and RF interference and can assist secondary winding regulation by disabling discontinuous mode when the main output is lightly loaded. Internal op amp allows programmable offsets to the output voltage during power saving modes. Fault protection is provided by internal foldback current limiting, an output overvoltage comparator and optional short-circuit shutdown timer. Soft-start capability for supply sequencing is accomplished using an external timing capacitor. The regulator current limit level is user programmable. Wide supply range allows operation from 4V to 36V at the input. , LTC and LT are registered trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. U TYPICAL APPLICATIO LTC3714 PGOOD INTVCC CSS 0.1µF CC Transient Response of 8A to 23A Output Load Step RON ION VIN RUN/SS TG ITH SW RC CB, 0.22µF BOOST INTVCC VID3 5-BIT VID SENSE VID1 VID0 M2 IRF7811 ×3 BG VID2 + DB CMDSH-3 SGND VID4 10µF 35V ×4 M1 IRF7811 L1 ×2 0.68µH + CVCC 4.7µF COUT 270µF 2V ×4 VIN 5V TO 24V 1.395V VOUT 0.6V TO 1.75V 23A VOUT (1.35V) 50mV/DIV D1* UPS840 1.213V 0.003Ω* 23A ILOAD PGND VOSENSE 10A/DIV 3714 F01 8A *OPTIONAL Figure 1. High Efficiency Step-Down Converter 20µs/DIV 3714 TA03 3714f 1 LTC3714 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) ORDER PART NUMBER TOP VIEW Input Supply Voltage (VIN), ION ..................36V to – 0.3V Boosted Topside Driver Supply Voltage (BOOST) ................................................... 42V to – 0.3V SW, SENSE Voltages ................................... 36V to – 5V EXTVCC, (BOOST – SW), RUN/SS, VID0-VID4, PGOOD, FCB Voltages ............................... 7V to – 0.3V VON, VRNG Voltages ................(INTVCC + 0.3V) to – 0.3V ITH, VFB, VOSENSE Voltages ....................... 2.7V to – 0.3V TG, BG, INTVCC, EXTVCC Peak Currents .................... 2A TG, BG, INTVCC, EXTVCC RMS Currents .............. 50mA OPVIN, OP +, OP – ....................................................... 0V to 18V Operating Ambient Temperature Range LTC3714EG (Note 2) .......................... – 40°C to 85°C Junction Temperature (Note 3) ............................ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C BG 1 28 INTVCC PGND 2 27 VIN SENSE 3 26 EXTVCC SW 4 25 VID4 TG 5 24 VID3 BOOST 6 23 VOSENSE VID0 7 22 VFB VID1 8 21 ION VID2 9 20 FCB RUN/SS 10 VON 11 19 SGND 18 OPOUT PGOOD 12 17 OP + VRNG 13 16 OP – ITH 14 LTC3714EG 15 OPVIN G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/ W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 900 15 2000 30 µA µA 0.600 0.606 V Main Control Loop IQ Input DC Supply Current Normal Shutdown Supply Current VFB Feedback Reference Voltage ITH = 1.2V (Note 4) ∆VFB(LINEREG) Feedback Voltage Line Regulation VIN = 4V to 30V (Note 4), ITH = 1.2V ∆VFB(LOADREG) Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 4) ● – 0.05 – 0.3 % gm(EA) Error Amplifier Transconductance ITH = 1.2V (Note 4) ● 1.4 1.7 2 ms VFCB Forced Continuous Threshold ● 0.57 0.6 0.63 V IFCB Forced Continuous Current VFCB = 0.6V –1 –2 µA tON On-Time ION = 60µA, VON = 1.5V 200 250 300 ns tON(MIN) Minimum On-Time ION = 180µA, VON = 0V 50 100 ns tOFF(MIN) Minimum Off-Time ION = 60µA, VON = 1.5V VSENSE(MAX) Maximum Current Sense Threshold VRNG = 1V, VFB = 0.56V VRNG = 0V, VFB = 0.56V VRNG = INTVCC, VFB = 0.56V VSENSE(MIN) Minimum Current Sense Threshold VRNG = 1V, VFB = 0.64V VRNG = 0V, VFB = 0.64V VRNG = INTVCC, VFB = 0.64V ∆VFB(OV) Output Overvoltage Fault Threshold 7.5 10 12.5 % ∆VFB(UV) Output Undervoltage Fault Threshold 340 400 460 mV VRUN/SS(ON) RUN Pin Start Threshold 0.8 1.5 2 ● 0.594 0.002 ● ● ● 113 79 158 %/V 250 400 ns 133 93 186 153 107 214 mV mV mV – 67 – 33 – 93 ● mV mV mV V 3714f 2 LTC3714 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 15V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VRUN/SS(LE) RUN Pin Latchoff Enable Threshold VRUN/SS(LT) RUN Pin Latchoff Threshold IRUN/SS(C) Soft-Start Charge Current IRUN/SS(D) Soft-Start Discharge Current VIN(UVLO) Undervoltage Lockout Threshold VIN(UVLOR) TG RUP MIN TYP MAX UNITS RUN/SS Pin Rising 4 4.5 V RUN/SS Pin Falling 3.5 4.2 V – 0.5 –1.2 –3 µA 0.8 1.8 3 µA V VIN Falling ● 3.4 3.9 Undervoltage Lockout Threshold VIN Rising ● 3.5 4 V TG Driver Pull-Up On Resistance TG High 2 3 Ω TG RDOWN TG Driver Pull-Down On Resistance TG Low 2 3 Ω BG RUP BG Driver Pull-Up On Resistance BG High 3 4 Ω BG RDOWN BG Driver Pull-Down On Resistance BG Low 1 2 Ω TG tr TG Rise Time CLOAD = 3300pF 20 ns TG tf TG Fall Time CLOAD = 3300pF 20 ns BG tr BG Rise Time CLOAD = 3300pF 20 ns BG tf BG Fall Time CLOAD = 3300pF 20 ns Internal VCC Regulator VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V ∆VLDO(LOADREG) Internal VCC Load Regulation VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, VEXTVCC Rising ∆VEXTVCC EXTVCC Switch Drop Voltage ICC = 20mA, VEXTVCC = 5V ∆VEXTVCC(HYS) EXTVCC Switchover Hysteresis ● 4.7 ICC = 0mA to 20mA, VEXTVCC = 4V ● 4.5 5 5.3 V – 0.1 ±2 % 300 mV 4.7 150 V 200 mV PGOOD Output ∆VFBH PGOOD Upper Threshold VFB Rising 7.5 10 12.5 % ∆VFBL PGOOD Lower Threshold VFB Falling – 7.5 –10 –12.5 % ∆VFB(HYS) PGOOD Hysteresis VFB Returning 1 2.5 % VPGL PGOOD Low Voltage IPGOOD = 1mA 0.15 0.4 V 1.2 2 VID DAC VVID(T) VID0-VID4 Logic Threshold Voltage IVID(PULLUP) VID0-VID4 Pull-Up Current VVID0 to VVID4 = 0V 0.4 – 2.5 µA VVID(PULLUP) VID0-VID4 Pull-Up Voltage VVID0 to VVID4 Open 4.5 V IVID(LEAK) VID0-VID4 Leakage Current VVID0 to VVID4 = 5V, VRUN/SS = 0V RVID Resistance from VOSENSE to VFB ∆VOSENSE DAC Output Accuracy VOSENSE Programmed from 0.6V to 1.75V (Note 5) V 0.01 1 µA 6 10 14 KΩ – 0.45 0 0.25 % VIN = 5V unless otherwise noted. Internal Op Amp VOS Input Offset Voltage 400 1000 µV IOS Input Offset Current 4 10 nA IB Input Bias Current 45 80 nA CMRR Common Mode Rejection Ratio VCM = 0V to (VCC – 1V) VCM = 0V to 18V 100 80 dB dB 3714f 3 LTC3714 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VIN = 5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS PSRR Power Supply Rejection Ratio OPVIN = 3V to 12.5V, OPOUT = VO = 1V 100 dB AVOL Large-Signal Voltage Gain OPVIN = 5V, OPOUT = 500mV to 4.5V, RL = 10k 1500 V/mV VOL Output Voltage Swing LOW OPVIN = 5V, ISINK = 5mA ● VOH Output Voltage Swing HIGH OPVIN = 5V, ISOURCE = 5mA ● ISC Short-Circuit Current Short to GND Short to OPVIN IS Supply Current Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3714E is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the – 40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD as follows: LTC3714EG: TJ = TA + (PD • 130°C/W) MIN TYP 165 4.5 MAX 500 4.87 mV V 30 40 170 UNITS mA mA 300 µA Note 4: The LTC3714 is tested in a feedback loop that adjusts VFB to achieve a specified error amplifier output voltage (ITH). Note 5: The LTC3714 VID DAC is tested in a feedback loop that adjusts VOSENSE to achieve a specified feedback voltage (VFB = 0.6V) for each DAC VID code. 3714f 4 LTC3714 U W TYPICAL PERFOR A CE CHARACTERISTICS Transient Response (Discontinuous Mode) Transient Response VOUT 50mV/DIV Start-Up RUN/SS 2V/DIV VOUT 50mV/DIV VOUT 500mV/DIV IL 5A/DIV IL 5A/DIV 20µs/DIV LOAD STEP 0A TO 10A VIN = 15V VOUT = 1.5V FCB = 0V FIGURE 1 CIRCUIT 20µs/DIV LOAD STEP 1A TO 10A VIN = 15V VOUT = 1.5V FCB = INTVCC FIGURE 1 CIRCUIT 3714 G01 Efficiency vs Load Current Frequency vs Input Voltage 300 IOUT = 10A 80 IOUT = 1A IOUT = 23A 70 60 3 6 9 12 15 18 LOAD CURRENT (A) 21 0 5 10 15 20 INPUT VOLTAGE (V) 25 Load Regulation ITH VOLTAGE (V) ∆VOUT (%) 1.5 CONTINUOUS MODE 1.0 DISCONTINUOUS MODE 0.5 8 10 3714 G06 0 VRNG = FIGURE 1 CIRCUIT –0.3 6 4 LOAD CURRENT (A) 25 Current Sense Threshold vs ITH Voltage 2.0 –0.1 2 20 3714 G05 300 2.5 NO AVP FIGURE 1 CIRCUIT 0 15 INPUT VOLTAGE (V) ITH Voltage vs Load Current –0.2 10 5 3714 G04 3714 G03 0 IOUT = 0A 240 200 30 CURRENT SENSE THRESHOLD (mV) 0 260 220 VOUT = 1.35V FREQUENCY = 300kHz FIGURE 1 CIRCUIT 75 –0.4 FREQUENCY (kHz) EFFICIENCY (%) VIN = 24V 80 IOUT = 10A 90 VIN = 15V 85 FCB = 0V FIGURE 1 CIRCUIT 280 VIN = 8.5V 3714 G19 VIN = 15V VOUT = 1.25V RLOAD = 0.125Ω 100 90 70 50ms/DIV 3714 G02 Efficiency vs Input Voltage 95 EFFICIENCY (%) IL 5A/DIV 200 10 5 LOAD CURRENT (A) 15 3714 G07 1.4V 1V 0.7V 0.5V 100 0 –100 –200 0 2V 0 0.5 1.0 1.5 2.0 ITH VOLTAGE (V) 2.5 3.0 3714 G08 3714f 5 LTC3714 U W TYPICAL PERFOR A CE CHARACTERISTICS On-Time vs ION Current 10k On-Time vs VON Voltage 1000 VVON = 0V On-Time vs Temperature 300 IION = 30µA 250 ON-TIME (ns) 1k ON-TIME (ns) ON-TIME (ns) 800 100 600 400 10 10 ION CURRENT (µA) 1 150 0 100 50 2 1 VON VOLTAGE (V) 0 200 150 100 50 1.0 1.25 1.5 VRNG VOLTAGE (V) 1.75 VRNG = 1V 125 100 75 50 25 0 1.5 2.0 2 2.5 3 RUN/SS VOLTAGE (V) 3.5 Feedback Reference Voltage vs Temperature VRNG = 1V 140 130 120 110 100 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3714 G11 Error Amplifier gm vs Temperature 2.0 0.62 1.8 0.61 gm (mS) FEEDBACK REFERENCE VOLTAGE (V) 150 3714 G23 3714 G10 125 Maximum Current Sense Threshold vs Temperature MAXIMUM CURRENT SENSE THRESHOLD (mV) MAXIMUM CURRENT SENSE THRESHOLD (mV) 250 150 100 3714 G22 Maximum Current Sense Threshold vs RUN/SS Voltage 300 0.75 50 25 75 0 TEMPERATURE (°C) 3714 G21 Maximum Current Sense Threshold vs VRNG Voltage 0.5 0 –50 –25 3 3714 G20 MAXIMUM CURRENT SENSE THRESHOLD (mV) 200 100 200 0 IION = 30µA VVON = 0V 0.60 1.6 1.4 0.59 1.2 0.58 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 3714 G12 1.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3714 G13 3714f 6 LTC3714 U W TYPICAL PERFOR A CE CHARACTERISTICS Input and Shutdown Currents vs Input Voltage EXTVCC OPEN SHUTDOWN 600 30 400 20 200 10 ∆INTVCC (%) 40 –0.1 SHUTDOWN CURRENT (µA) –0.2 –0.3 –0.4 8 6 4 2 EXTVCC = 5V 0 –0.5 0 20 15 25 10 INPUT VOLTAGE (V) 5 30 35 0 10 30 40 20 INTVCC LOAD CURRENT (mA) 50 0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 3714 G14 3714 G25 3714 G24 RUN/SS Pin Current vs Temperature FCB Pin Current vs Temperature 0 3 –0.25 2 FCB PIN CURRENT (µA) FCB PIN CURRENT (µA) –0.50 –0.75 –1.00 PULL-DOWN CURRENT 1 0 PULL-UP CURRENT –1 –1.25 –1.50 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 –2 –50 –25 125 50 25 0 75 TEMPERATURE (°C) 5.0 4.5 LATCHOFF ENABLE 4.0 3.5 LATCHOFF THRESHOLD –25 75 0 25 50 TEMPERATURE (°C) 125 Undervoltage Lockout Threshold vs Temperature RUN/SS Latchoff Thresholds vs Temperature 3.0 –50 100 3714 G16 3714 G15 UNDERVOLTAGE LOCKOUT THRESHOLD (V) 0 RUN/SS THRESHOLD (V) INPUT CURRENT (µA) 50 800 10 0 60 EXTVCC SWITCH RESISTANCE (Ω) 1200 1000 EXTVCC Switch Resistance vs Temperature INTVCC Load Regulation 100 125 3714 G17 4.0 3.5 3.0 2.5 2.0 –50 –25 75 0 25 50 TEMPERATURE (C) 100 125 3714 G18 3714f 7 LTC3714 U U U PI FU CTIO S BG (Pin 1): Bottom Gate Drive. Drives the gate of the bottom N-channel MOSFET between ground and INTVCC. PGND (Pin 2): Power Ground. Connect this pin closely to the bottom of the sense resistor or if no sense resistor is used, to the source of the bottom N-channel MOSFET, the (–) terminal of CVCC and the (–) terminal of CIN. SENSE (Pin 3): Current Sense Comparator Input. The (+) input to the current comparator is normally connected to the SW node unless using a sense resistor (see Applications Information). SW (Pin 4): Switch Node. The (–) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below ground up to VIN. TG (Pin 5): Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW. BOOST (Pin 6): Boosted Floating Driver Supply. The (+) terminal of the bootstrap capacitor CB connects here. This pin swings from a diode voltage drop below INTVCC up to VIN + INTVCC. VID0-VID4 (Pins 7, 8, 9, 24, 25): VID Digital Inputs. The voltage identification (VID) code sets the internal feedback resistor divider ratio for different output voltages as shown in Table 1. If unconnected, the pins are pulled high by internal 2.5µA current sources. RUN/SS (Pin 10): Run Control and Soft-Start Input. A capacitor to ground at this pin sets the ramp time to full output current (approximately 3s/µF) and the time delay for overcurrent latchoff (see Applications Information). Forcing this pin below 0.8V shuts down the device. VON (Pin 11): On-Time Voltage Input. Voltage trip point for the on-time comparator. Tying this pin to the output voltage makes the on-time proportional to VOUT. The comparator input defaults to 0.7V when the pin is grounded, 2.4V when the pin is tied to INTVCC. mum output current and can be set from 0.5V to 2V by a resistive divider from INTVCC. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to INTVCC. ITH (Pin 14): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. The voltage ranges from 0V to 2.4V with 0.8V corresponding to zero sense voltage (zero current). OPVIN (Pin 15): Internal Op Amp Supply. Connect to INTVCC or a separate supply greater than 5V. OP – (Pin 16): Negative Input of the Internal Op Amp. OP + (Pin 17): Positive Input of the Internal Op Amp. OPOUT (Pin 18): Output of the Internal Op Amp. SGND (Pin 19): Signal Ground. All small-signal components and compensation components should connect to this ground, which in turn connects to PGND at one point. FCB (Pin 20): Forced Continous Input. Tie this pin to ground to force continuous synchronous operation at low load, to INTVCC to enable discontinuous mode operation at low load or to a resistive divider from a secondary output when using a secondary winding. ION (Pin 21): On-Time Current Input. Tie a resistor from VIN to this pin to set the one-shot timer current and thereby set the switching frequency. VFB (Pin 22): Error Amplifier Feedback Input. This pin connects to both the error amplifier input and to the output of the internal resistive divider. It can be used to attach additional compensation components if desired. VOSENSE (Pin 23): Output Voltage Sense. The output voltage connects here to the input of the internal resistive feedback divider. PGOOD (Pin 12): Power Good Output. Open drain logic output that is pulled to ground when the output voltage is not within ±10% of the regulation point. EXTVCC (Pin 26): External VCC Input. When EXTVCC exceeds 4.7V, an internal switch connects this pin to INTVCC and shuts down the internal regulator so that controller and gate drive power is drawn from EXTVCC. Do not exceed 7V at this pin and ensure that EXTVCC < VIN. VRNG (Pin 13): Sense Voltage Range Input. The voltage at this pin is ten times the nominal sense voltage at maxi- VIN (Pin 27): Main Input Supply. Decouple this pin to SGND with an RC filter (1Ω, 0.1µF). 3714f 8 LTC3714 U U U PI FU CTIO S INTVCC (Pin 28): Internal 5V Regulator Output. The driver and control circuits are powered from this voltage. De- couple this pin to power ground with a minimum of 4.7µF tantalum or other low ESR capacitor. W FU CTIO AL DIAGRA U RON VIN 11 VON 21 ION 20 FCB 27 VIN 26 EXTVCC + 4.7V CIN 0.7V + 1µA 2.4V – 0.6V REF 0.6V 1 5V REG + – F OST 6 V tON = VON (10pF) IION R TG S Q FCNT 4 L1 SENSE SWITCH LOGIC IREV 3 – – M1 SW + ICMP CB 5 ON 20k + BOOST VOUT INTVCC 28 SHDN 1.4V BG OV + CVCC COUT M2 1 VRNG PGND 13 X 2 (0.5 TO 2) PGOOD 0.7V 12 3.3µA VOSENSE 23 1 240k + 1V Q2 Q4 0.54V R2 10k 5× (ALL VID PINS) UV – Q6 INTVCC 2.5µA 7 VID0 Q3 Q1 + Q5 8 VID1 OV + – – 0.8V – ×5.3 SS VID DAC 0.66V RUN SHDN + 9 VID2 24 VID3 1.2µA EA 6V 25 VID4 + – – + 0.6V 0.6V 14 ITH RC CC1 0.4V 10 RUN/SS CSS 22 VFB R1 19 SGND 3714 FD 15 OPVIN OP + 17 + OP – 16 – OP AMP 18 OPOUT 19 SGND 3714f 9 U LTC3714 U OPERATIO Main Control Loop The LTC3714 is a constant on-time, current mode controller for DC/DC step-down converters. In normal operation, the top MOSFET is turned on for a fixed interval determined by a one-shot timer OST. When the top MOSFET is turned off, the bottom MOSFET is turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between the PGND and SENSE pins using either the bottom MOSFET on-resistance or a separate sense resistor. The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal VFB from the output voltage with an internal 0.6V reference. The feedback voltage is derived from the output voltage by a resistive divider DAC that is set by the VID code pins VID0VID4. If the load current increases, it causes a drop in the feedback voltage relative to the reference. The ITH voltage then rises until the average inductor current again matches the load current. At low load currents, the inductor current can drop to zero and become negative. This is detected by current reversal comparator IREV which then shuts off M2, resulting in discontinuous operation. Both switches will remain off with the output capacitor supplying the load current until the ITH voltage rises above the zero current level (0.8V) to initiate another cycle. Continuous synchronous operation can be forced in the LTC3714 by bringing the FCB pin below 0.6V. The benefit of forced continuous operation is lower output voltage ripple, faster transient response to current load steps and a much quieter frequency spectrum so that it won’t interfere with any neighboring noise sensitive components. The operating frequency is determined implicitly by the top MOSFET on-time and the duty cycle required to maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus holding frequency approximately constant with changes in VIN and VOUT. The nominal frequency can be adjusted with an external resistor RON. Overvoltage and undervoltage comparators OV and UV pull the PGOOD output low if the output feedback voltage exits a ±10% window around the regulation point. Furthermore, in an overvoltage condition, M1 is turned off and M2 is turned on and held on until the overvoltage condition clears. Foldback current limiting is provided if the output is shorted to ground. As VFB drops, the buffered current threshold voltage ITHB is pulled down by clamp Q3 to a 1V level set by Q2 and Q6. This reduces the inductor valley current level to one sixth of its maximum value as VFB approaches ground. Pulling the RUN/SS pin low forces the controller into its shutdown state, turning off both M1 and M2. Releasing the pin allows an internal 1.2µA current source to charge up an external soft-start capacitor CSS. When this voltage reaches 1.5V, the controller turns on and begins switching, but with the ITH voltage clamped at approximately 0.6V below the RUN/SS voltage. As CSS continues to charge, the soft-start current limit is removed. 3714f 10 LTC3714 U OPERATIO Internal Op Amp INTVCC/EXTVCC Power The internal op amp allows the user to program accurate offsets to the output voltage during power saving modes. By connecting the OP + pin to the output, the OPOUT pin to the VOSENSE pin and an external resistor R1 between the OP –and OPOUT pins, the op amp is hooked up as a unitygain feedback amplifier. Resistors R2 and R3, together with series switches, can then be placed on the OP – pin to allow negative offsets to be switched onto the output voltage (see Figures 2a and 2b). The accuracy of the offset will depend on the matching of the external resistors R1 to R2 and R3.* Power for the top and bottom MOSFET drivers and most of the internal controller circuitry is derived from the INTVCC pin. The top MOSFET driver is powered from a floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode DB when the top MOSFET is turned off. When the EXTVCC pin is grounded, an internal 5V low dropout regulator supplies the INTVCC power from VIN. If EXTVCC rises above 4.7V, the internal regulator is turned off, and an internal switch connects EXTVCC to INTVCC. This allows a high efficiency source connected to EXTVCC, such as an external 5V supply or a secondary output from the converter, to provide the INTVCC power. Voltages up to 7V can be applied to EXTVCC for additional gate drive. If the input voltage is low and INTVCC drops below 3.5V, undervoltage lockout circuitry prevents the power switches from turning on. For applications that require less accurate output offsets, or none at all, the user can use the internal op amp for true differential remote sensing of the output voltage by connecting OPOUT to VOSENSE and using OP + and OP – for differential sensing across the output capacitor as shown in Figure 2c. *An alternate configuration, shown in Figure 2b, can be used to program offsets as well. Either configuration can be used, depending upon the logic of control signals. If offsets are not required, the op amp can be used to remotely sense the output voltage, proving true differential sense. VOUT VOUT R1 15 OPVIN OP + 15 OPVIN OP + + 17 17 + OP – 16 – OPOUT VOSENSE 18 23 VID DAC 18 OP – 16 BATTERY MODE OFFSET VFB R1 VID DAC R2 – 23 VFB 22 22 R2 R1 R2 SLEEP MODE OFFSET R3 R3 BATTERY MODE OFFSET 3714 F02b 3714 F02b SLEEP MODE OFFSET Figure 2a Figure 2b VOUT+ 15 OPVIN OP + R 17 + OP – 16 – OPOUT VOSENSE R VOUT– 18 R 23 3714 F02c R Figure 2c 3714f 11 LTC3714 U W U U APPLICATIO S I FOR ATIO The basic LTC3714 application circuit is shown in Figure 1. External component selection is primarily determined by the maximum load current and begins with the selection of the sense resistance and power MOSFET switches. The LTC3714 can use either a sense resistor or the on-resistance of the synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and operating frequency largely determines the inductor value. Finally, CIN is selected for its ability to handle the large RMS current into the converter and COUT is chosen with low enough ESR to meet the output voltage ripple and transient specification. Maximum Sense Voltage and VRNG Pin Inductor current is determined by measuring the voltage across a sense resistance that appears between the PGND and SENSE pins. The maximum sense voltage is set by the voltage applied to the VRNG pin and is equal to approximately (0.133)VRNG. The current mode control loop will not allow the inductor current valleys to exceed (0.133)VRNG/RSENSE. In practice, one should allow some margin for variations in the LTC3714 and external component values and a good guide for selecting the sense resistance is: RSENSE = VRNG 10 • IOUT(MAX) An external resistive divider from INTVCC can be used to set the voltage of the VRNG pin between 0.5V and 2V resulting in nominal sense voltages of 50mV to 200mV. Additionally, the VRNG pin can be tied to SGND or INTVCC in which case the nominal sense voltage defaults to 70mV or 140mV, respectively. The maximum allowed sense voltage is about 1.33 times this nominal value. Connecting the SENSE Pin The LTC3714 can be used with or without a sense resistor. When using a sense resistor, it is placed between the source of the bottom MOSFET M2 and ground. Connect the SENSE pin to the source of the bottom MOSFET so that the resistor appears between the SENSE and PGND pins. Using a sense resistor provides a well defined current limit, but adds cost and reduces efficiency. Alternatively, one can eliminate the sense resistor and use the bottom MOSFET as the current sense element by simply connecting the SENSE pin to the switch node SW at the drain of the bottom MOSFET. This improves efficiency, but one must carefully choose the MOSFET on-resistance as discussed below. Power MOSFET Selection The LTC3714 requires two external N-channel power MOSFETs, one for the top (main) switch and one for the bottom (synchronous) switch. Important parameters for the power MOSFETs are the breakdown voltage V(BR)DSS, threshold voltage V(GS)TH, on-resistance RDS(ON), reverse transfer capacitance CRSS and maximum current IDS(MAX). The gate drive voltage is set by the 5V INTVCC supply. Consequently, logic-level threshold MOSFETs must be used in LTC3714 applications. If the input voltage is expected to drop below 5V, then sub-logic level threshold MOSFETs should be considered. When the bottom MOSFET is used as the current sense element, particular attention must be paid to its onresistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this case, additional margin is required to accommodate the rise in MOSFET on-resistance with temperature: RDS(ON)(MAX) = RSENSE ρT The ρT term is a normalization factor (unity at 25°C) accounting for the significant variation in on-resistance with temperature, typically about 0.4%/°C as shown in Figure 3. Junction-to-case temperature is about 30°C in most applications. For a maximum ambient temperature of 70°C, using a value ρ100°C = 1.3 is reasonable. The power dissipated by the top and bottom MOSFETs strongly depends upon their respective duty cycles and the load current. When the LTC3714 is operating in continuous mode, the duty cycles for the MOSFETs are: VOUT VIN V –V = IN OUT VIN DTOP = DBOT 3714f 12 LTC3714 U W U U APPLICATIO S I FOR ATIO Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down converter, this results in approximately constant frequency operation as the input supply varies: ρT NORMALIZED ON-RESISTANCE 2.0 1.5 1.0 f= 0.5 0 – 50 50 100 0 JUNCTION TEMPERATURE (°C) 150 3714 F02 Figure 3. RDS(ON) vs Temperature The resulting power dissipation in the MOSFETs at maximum output current are: PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX) + k VIN2 IOUT(MAX) CRSS f PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX) Both MOSFETs have I2R losses and the top MOSFET includes an additional term for transition losses, which are largest at high input voltages. The constant k = 1.7A–1 can be used to estimate the amount of transition loss. The bottom MOSFET losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. Operating Frequency The choice of operating frequency is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses but requires larger inductance and/or capacitance in order to maintain low output ripple voltage. The operating frequency of LTC3714 applications is determined implicitly by the one-shot timer that controls the on-time tON of the top MOSFET switch. The on-time is set by the current into the ION pin and the voltage at the VON pin according to: tON = VOUT VVONRON(10pF ) To hold frequency constant during output voltage changes, tie the VON pin to VOUT. The VON pin has internal clamps that limit its input to the one-shot timer. If the pin is tied below 0.7V, the input to the one-shot is clamped at 0.7V. Similarly, if the pin is tied above 2.4V, the input is clamped at 2.4V. Because the voltage at the ION pin is about 0.7V, the current into this pin is not exactly inversely proportional to VIN, especially in applications with lower input voltages. To correct for this error, an additional resistor RON2 connected from the ION pin to the 5V INTVCC supply will further help to stabilize the frequency. RON2 = 5V RON 0.7 V Changes in the load current magnitude will also cause frequency shift. Parasitic resistance in the MOSFET switches and inductor reduce the effective voltage across the inductance, resulting in increased duty cycle as the load current increases. By lengthening the on-time slightly as current increases, constant frequency operation can be maintained. This is accomplished with a resistive divider from the ITH pin to the VON pin and VOUT. The values required will depend on the parasitic resistances in the specific application. A good starting point is to feed about 25% of the voltage change at the ITH pin to the VON pin as shown in Figure 4a. Place capacitance on the VON pin to filter out the ITH variations at the switching frequency. The resistor load on ITH reduces the DC gain of the error amp and degrades load regulation, which can be avoided by using the PNP emitter follower of Figure 4b. VVON (10pF) IION 3714f 13 LTC3714 U W U U APPLICATIO S I FOR ATIO RVON1 30k RVON1 3k VON VOUT CVON 0.01µF RVON2 100k VOUT LTC3714 RC 10k INTVCC LTC3714 ITH CC 3714 F04a (4a) VON RC Q1 2N5087 ITH CC CVON 0.01µF RVON2 10k 3714 F04b (4b) Figure 4. Correcting Frequency Shift with Load Current Changes Inductor Selection Schottky Diode D1 Selection Given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: The Schottky diode D1 shown in Figure 1 conducts during the dead time between the conduction of the power MOSFET switches. It is intended to prevent the body diode of the bottom MOSFET from turning on and storing charge during the dead time, causing a modest (about 1%) efficiency loss. The diode can be rated for about one half to one fifth of the full load current since it is on for only a fraction of the duty cycle. In order for the diode to be effective, the inductance between it and the bottom MOSFET must be as small as possible, mandating that these components be placed adjacently. The diode can be omitted if the efficiency loss is tolerable. V V ∆IL = OUT 1 − OUT VIN fL Lower ripple current reduces cores losses in the inductor, ESR losses in the output capacitors and output voltage ripple. Highest efficiency operation is obtained at low frequency with small ripple current. However, achieving this requires a large inductor. There is a tradeoff between component size, efficiency and operating frequency. A reasonable starting point is to choose a ripple current that is about 40% of IOUT(MAX). The largest ripple current occurs at the highest VIN. To guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: VOUT VOUT L= 1− f∆IL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must be selected. A variety of inductors designed for high current, low voltage applications are available from manufacturers such as Sumida and Panasonic. CIN and COUT Selection The input capacitance CIN is required to filter the square wave current at the drain of the top MOSFET. Use a low ESR capacitor sized to handle the maximum RMS current. IRMS ≅ IOUT(MAX) VOUT VIN VIN –1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT(MAX) / 2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to derate the capacitor. 3714f 14 LTC3714 U W U U APPLICATIO S I FOR ATIO The selection of COUT is primarily determined by the ESR required to minimize voltage ripple and load step transients. The output ripple ∆VOUT is approximately bounded by: to store about 100 times the gate charge required by the top MOSFET. In most applications 0.1µF to 0.47µF is adequate. Discontinuous Mode Operation and FCB Pin 1 ∆VOUT ≤ ∆IL ESR + 8 fCOUT Since ∆IL increases with input voltage, the output ripple is highest at maximum input voltage. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the necessary RMS current rating. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirements. Dry tantalum, special polymer, POSCAP aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR but have lower capacitance density than other types. Tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR, but can be used in cost-sensitive applications providing that consideration is given to ripple current ratings and long term reliability. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. When used as input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the power switches and controller. High performance throughhole capacitors may also be used, but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance. The FCB pin determines whether the bottom MOSFET remains on when current reverses in the inductor. Tying this pin above its 0.6V threshold (typically to INTVCC) enables discontinuous operation where the bottom MOSFET turns off when inductor current reverses. The load current at which current reverses and discontinuous operation begins, depends on the amplitude of the inductor ripple current. The ripple current depends on the choice of inductor value and operating frequency as well as the input and output voltages. Tying the FCB pin below the 0.6V threshold forces continuous synchronous operation, allowing current to reverse at light loads. In addition to providing a logic input to force continuous operation, the FCB pin provides a means to maintain a flyback winding output when the primary is operating in discontinuous mode. The secondary output VSEC is normally set as shown in Figure 5 by the turns ratio N of the transformer. However, if the controller goes into discontinuous mode and halts switching due to a light primary load current, then VSEC will droop. An external resistor divider from VSEC to the FCB pin sets a minimum voltage VSEC(MIN) below which continuous operation is forced until VSEC has risen above its minimum. R4 VSEC(MIN) = 0.6V 1 + R3 CIN VIN Top MOSFET Driver Supply (CB, DB) An external bootstrap capacitor CB connected to the BOOST pin supplies the gate drive voltage for the topside MOSFET. This capacitor is charged through diode DB from INTVCC when the switch node is low. When the top MOSFET turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs VIN + OPTIONAL EXTVCC CONNECTION 5V < VSEC < 7V TG 1N4148 • + LTC3714 EXTVCC SW R4 FCB R3 SENSE T1 1:N • + VSEC CSEC 1µF VOUT COUT BG SGND PGND 3714 F05 Figure 5. Secondary Output Loop and EXTVCC Connection 3714f 15 LTC3714 U W U U APPLICATIO S I FOR ATIO Fault Conditions: Current Limit and Foldback The maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. In the LTC3714, the maximum sense voltage is controlled by the voltage on the VRNG pin. With valley current control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSNS(MAX) 1 + ∆IL *RDS(ON)ρT 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit generally occurs with the lowest VIN at the highest ambient temperature. Note that it is important to check for selfconsistency between the assumed junction temperature and the resulting value of ILIMIT which heats the MOSFET switches. Caution should be used when setting the current limit based upon the RDS(ON) of the MOSFETs. The maximum current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and maximum values for RDS(ON), but not a minimum. A reasonable assumption is that the minimum RDS(ON) lies the same amount below the typical value as the maximum lies above it. Consult the MOSFET manufacturer for further guidelines. To further limit current in the event of a short circuit to ground, the LTC3714 includes foldback current limiting. If the output falls by more than 50%, then the maximum sense voltage is progressively lowered to about one sixth of its full value. Minimum Off-Time and Dropout Operation The minimum off-time tOFF(MIN) is the smallest amount of time that the LTC3714 is capable of turning on the bottom MOSFET, tripping the current comparator and turning the MOSFET back off. This time is generally about 250ns. The minimum off-time limit imposes a maximum duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached, due to a dropping input voltage for example, then the output will drop out of regulation. The minimum input voltage to avoid dropout is: VIN(MIN) = VOUT tON + tOFF(MIN) tON Output Voltage Programming The output voltage is digitally set to levels between 0.6V and 1.75V using the voltage identification (VID) inputs VID0-VID4. An internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in increments according to Table 1. The VID codes are compatible with Intel Mobile Pentium® III processor specifications. Each VID input is pulled up by an internal 2.5µA current source from the INTVCC supply and includes a series diode to prevent damage from VID inputs that exceed the supply. *Use RSENSE value here if a sense resistor is connected between SENSE and PGND. 3714f 16 LTC3714 U W U U APPLICATIO S I FOR ATIO INTVCC Regulator An internal P-channel low dropout regulator produces the 5V supply that powers the drivers and internal circuitry within the LTC3714. The INTVCC pin can supply up to 50mA RMS and must be bypassed to ground with a minimum of 4.7µF tantalum or other low ESR capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate drivers. Applications using large MOSFETs with a high input voltage and high frequency of operation may cause the LTC3714 to exceed its maximum junction temperature rating or RMS current rating. Most of the supply current drives the MOSFET gates unless an external EXTVCC source is used. In continuous mode operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)). The junction temperature can be estimated from the equations given in Note 2 of the Electrical Characteristics. For example, the LTC3714EG is limited to less than 14mA from a 30V supply: TJ = 70°C + (14mA)(30V)(130°C/W) = 125°C For larger currents, consider using an external supply with the EXTVCC pin. Table 1. VID Output Voltage Programming VID4 VID3 VID2 VID1 VID0 VOUT (V) 0 0 0 0 0 1.75V 0 0 0 0 1 1.70V 0 0 0 1 0 1.65V 0 0 0 1 1 1.60V 0 0 1 0 0 1.55V 0 0 1 0 1 1.50V 0 0 1 1 0 1.45V 0 0 1 1 1 1.40V 0 1 0 0 0 1.35V 0 1 0 0 1 1.30V 0 1 0 1 0 1.25V 0 1 0 1 1 1.20V 0 1 1 0 0 1.15V 0 1 1 0 1 1.10V 0 1 1 1 0 1.05V 0 1 1 1 1 1.00V 1 0 0 0 0 0.975V 1 0 0 0 1 0.950V 1 0 0 1 0 0.925V 1 0 0 1 1 0.900V 1 0 1 0 0 0.875V 1 0 1 0 1 0.850V 1 0 1 1 0 0.825V 1 0 1 1 1 0.800V 1 1 0 0 0 0.775V 1 1 0 0 1 0.750V 1 1 0 1 0 0.725V 1 1 0 1 1 0.700V 1 1 1 0 0 0.675V 1 1 1 0 1 0.650V 1 1 1 1 0 0.625V 1 1 1 1 1 0.600V 3714f 17 LTC3714 U W U U APPLICATIO S I FOR ATIO EXTVCC Connection The EXTVCC pin can be used to provide MOSFET gate drive and control power from the output or another external source during normal operation. Whenever the EXTVCC pin is above 4.7V the internal 5V regulator is shut off and an internal 50mA P-channel switch connects the EXTVCC pin to INTVCC. INTVCC power is supplied from EXTVCC until this pin drops below 4.5V. Do not apply more than 7V to the EXTVCC pin and ensure that EXTVCC ≤ VIN. The following list summarizes the possible connections for EXTVCC: 1. EXTVCC grounded. INTVCC is always powered from the internal 5V regulator. 2. EXTVCC connected to an external supply. A high efficiency supply compatible with the MOSFET gate drive requirements (typically 5V) can improve overall efficiency. 3. EXTVCC connected to an output derived boost network. The low voltage output can be boosted using a charge pump or flyback winding to greater than 4.7V. The system will start-up using the internal linear regulator until the boosted output supply is available. External Gate Drive Buffers The LTC3714 drivers are adequate for driving up to about 60nC into MOSFET switches with RMS currents of 50mA. Applications with larger MOSFET switches or operating at frequencies requiring greater RMS currents will benefit from using external gate drive buffers such as the LTC1693. Alternately, the external buffer circuit shown in Figure 6 can be used. Note that the bipolar devices reduce the signal swing at the MOSFET gate, and benefit from increased EXTVCC voltage of about 6V. INTVCC BOOST 10Ω Q1 FMMT619 GATE OF M1 TG Q2 FMMT720 SW 10Ω Q3 FMMT619 GATE OF M2 BG Q4 FMMT720 PGND 3714 F06 Figure 6. Optional External Gate Driver 3714f 18 LTC3714 U W U U APPLICATIO S I FOR ATIO Soft-Start and Latchoff with the RUN/SS Pin troller turns off both power MOSFETs, shutting down the converter permanently. The RUN/SS pin must be actively pulled down to ground in order to restart operation. The RUN/SS pin provides a means to shut down the LTC3714 as well as a timer for soft-start and overcurrent latchoff. Pulling the RUN/SS pin below 1.5V puts the LTC3714 into a low quiescent current shutdown (IQ ≤ 30µA). Releasing the pin allows an internal 1.2µA internal current source to charge up the external timing capacitor CSS. If RUN/SS has been pulled all the way to ground, there is a delay before starting of about: tDELAY = ( The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has reached the 4V threshold. In general, this will depend upon the size of the output capacitance, output voltage and load current characteristic. A minimum soft-start capacitor can be estimated from: ) 1.5V CSS = 1.3s/µF CSS 1.2µA CSS > COUT VOUT RSENSE (10 – 4 [F/Vs]) Generally 0.1µF is more than sufficient. When the voltage on RUN/SS reaches 1.5V, the LTC3714 begins operating with a clamp on ITH of approximately 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH is raised until its full 2.4V range is available. This takes an additional 1.3s/µF, during which the load current is folded back until the output reaches 50% of its final value. The pin can be driven from logic as shown in Figure 7. Diode D1 reduces the start delay while allowing CSS to charge up slowly for the soft-start function. Overcurrent latchoff operation is not always needed or desired. Load current is already limited during a shortcircuit by the current foldback circuitry and latchoff operation can prove annoying during troubleshooting. The feature can be overridden by adding a pull-up current of > 5µA to the RUN/SS pin. The additional current prevents the discharge of CSS during a fault and also shortens the soft-start period. Using a resistor to VIN as shown in Figure 7a is simple, but slightly increases shutdown current. Connecting a resistor to INTVCC as shown in Figure 7b eliminates the additional shutdown current, but requires a diode to isolate CSS. Any pull-up network must be able to pull RUN/SS above the 4.5V maximum threshold that arms the latchoff circuit and overcome the 4µA maximum discharge current. After the controller has been started and given adequate time to charge up the output capacitor, CSS is used as a short-circuit timer. After the RUN/SS pin charges above 4V, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. A 1.7µA current then begins discharging CSS. If the fault condition persists until the RUN/SS pin drops to 3.5V, then the con- INTVCC RSS* VIN 3.3V OR 5V D1 RUN/SS RSS* D2* RUN/SS CSS CSS 3714 F07 *OPTIONAL TO OVERRIDE OVERCURRENT LATCHOFF (7a) (7b) Figure 7. RUN/SS Pin Interfacing with Latchoff Defeated 3714f 19 LTC3714 U W U U APPLICATIO S I FOR ATIO Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in LTC3714 circuits: 1. DC I2R losses. These arise from the resistances of the MOSFETs, inductor and PC board traces and cause the efficiency to drop at high output currents. In continuous mode the average output current flows through L, but is chopped between the top and bottom MOSFETs. If the two MOSFETs have approximately the same RDS(ON), then the resistance of one MOSFET can simply be summed with the resistances of L and the board traces to obtain the DC I2R loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the loss will range from 15mW up to 1.5W as the output current varies from 1A to 10A for a 1.5V output. 2. Transition loss. This loss arises from the brief amount of time the top MOSFET spends in the saturated region during switch node transitions. It depends upon the input voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input voltages above 20V and can be estimated from: Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f 3. INTVCC current. This is the sum of the MOSFET driver and control currents. This loss can be reduced by supplying INTVCC current through the EXTVCC pin from a high efficiency source, such as an output derived boost network or alternate supply if available. 4. CIN loss. The input capacitor has the difficult job of filtering the large RMS input current to the regulator. It must have a very low ESR to minimize the AC I2R loss and sufficient capacitance to prevent the RMS current from causing additional upstream losses in fuses or batteries. Other losses, including COUT ESR loss, Schottky diode D1 conduction loss during dead time and inductor core loss generally account for less than 2% additional loss. When making any adjustments to improve efficiency, the final arbiter is the total input current for the regulator at your operating point. If you make a change and the input current decreases, then you improved the efficiency. If there is no change in input current, then there is no change in efficiency. Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ∆ILOAD (ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. The ITH pin external components shown in Figure 8 will provide adequate compensation for most applications. For a detailed explanation of switching control loop theory see Linear Technology Application Note 76. Design Example As a design example, take a supply with the following specifications: V IN = 7V to 24V (15V nominal), VOUT = 1.15V ±100mV, IOUT(MAX) = 15A, f = 300kHz. First, calculate the timing resistor with VON = VOUT: RON = ( 1 )( 300kHz 10pF ) = 330k and choose the inductor for about 40% ripple current at the maximum VIN: L= 1.15V 1.15V 1− = 0.6µH (300kHz)(0.4)(15A) 24V Choosing a standard value of 0.68µH results in a maximum ripple current of: ∆IL = 1.15V 1.15V 1– = 5.4A (300kHz)(0.68µH) 24V 3714f 20 LTC3714 U W U U APPLICATIO S I FOR ATIO Next, choose the synchronous MOSFET switch. Because of the narrow duty cycle and large current, a single SO-8 MOSFET will have difficulty dissipating the power lost in the switch. Choosing two IRF7811s (RDS(ON) = 0.013Ω, CRSS = 60pF) yields a nominal sense voltage of: ILIMIT ≥ and double check the assumed TJ in the MOSFET: 2 VSNS(NOM) = (15A)(0.5)(1.3)(0.013Ω) = 127mV PBOT Tying VRNG to INTVCC will set the current sense voltage range for a nominal value of 140mV with current limit occurring at 186mV. To check if the current limit is acceptable, assume a junction temperature of about 100°C above a 50°C ambient with ρ150°C = 1.6: 9 CSS 0.1µF 10 11 RPG 100k 12 CC1 2.2nF 13 RC 20k 14 CC2 100pF 19 VID2 VID1 RUN/SS VID0 VON BOOST PGOOD TG VRNG ITH SW SENSE LTC3714 SGND PGND 186mV 1 + (5.4A ) = 20A (0.5)(1.6)(0.013Ω) 2 24V – 1.15V 20A = (1.6)(0.013Ω) = 1.98 W 2 24V TJ = 50°C + (1.98W)(50°C/W) = 149°C 8 7 DB CMDSH-3 6 CB 0.33µF 5 CIN 22µF 25V ×3 M1 L1 IRF7811 0.68µH 4 M2 IRF7811 ×2 3 2 D1 UPS840 VIN 7V TO 24V VOUT 1.15V 15A COUT 270µF 2V ×5 CION 0.01µF 21 22 CFB 100pF 20 23 RON 330k 24 15 16 ION VFB FCB VOSENSE VID3 OPVIN OP – BG INTVCC VIN EXTVCC VID4 OPOUT OP + 1 CVCC 4.7µF 28 RF 1Ω 27 26 5V CF 0.1µF 25 18 17 3714 F08 CIN: UNITED CHEMICON THCR70EIH226ZT COUT: PANASONIC EEFUE0D271 L1: SUMIDA CEP125-4712-T007 Figure 8. CPU Core Voltage Regulator 1.15V/15A at 300kHz without Active Voltage Positioning 3714f 21 LTC3714 U W U U APPLICATIO S I FOR ATIO Because the top MOSFET is on for such a short time, a single IRF7811 will be sufficient. Checking its power dissipation at current limit with ρ80°C = 1.2: PTOP 1.15V 2 20A ) (1.2)(0.013Ω) + = ( 24V (1.7)(24V)2 (20A)(60pF )(300kHz) = 0.299W + 0.353 W = 0.652W TJ = 50°C + (0.652W)(50°C/W) = 82.6°C The junction temperatures will be significantly less at nominal current, but this analysis shows that careful attention to heat sinking will be necessary in this circuit. CIN is chosen for an RMS current rating of about 6A at temperature. The output capacitors are chosen for a low ESR of 0.005Ω to minimize output voltage changes due to inductor ripple current and load steps. The ripple voltage will be only: ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR) = (5.4A) (0.005Ω) = 27mV However, a 0A to 15A load step will cause an output change of up to: ∆VOUT(STEP) = ∆ILOAD (ESR) = (15A) (0.005Ω) = ±75mV The complete circuit is shown in Figure 8. Active Voltage Positioning Active voltage positioning (also termed load “deregulation” or droop) describes a technique where the output voltage varies with load in a controlled manner. It is useful in applications where rapid load steps are the main cause of error in the output voltage. By positioning the output voltage at or above the regulation point at zero load, and below the regulation point at full load, one can use more of the error budget for the load step. This allows one to reduce the number of output capacitors by relaxing the ESR requirement. In the design example, Figure 8, five 0.025Ω capacitors are required in parallel to keep the output voltage within tolerance. Using active voltage positioning, the same specification can be met with only three capacitors. In this case, the load step will cause an output voltage change of: 1 ∆VOUT (STEP) = (15A ) (0.025Ω) = 125mV 3 By positioning the output voltage 60mV above the regulation point at no load, it will drop 65mV below the regulation point after the load step. However, when the load disappears or the output is stepped from 15A to 0A, the 65mV is recovered. This way, a total of 65mV change is observed on VOUT in all conditions, whereas a total of ±75mV or 150mV is seen on VOUT without voltage positioning. Implementing active voltage positioning requires setting a precise gain between the sensed current and the output voltage. Because of the variability of MOSFET on-resistance, it is prudent to use a sense resistor with active voltage positioning. In order to minimize power lost in this resistor, a low value of 0.003Ω is chosen. The nominal sense voltage will now be: VSNS(NOM) = (0.003Ω)(15A) = 45mV To maintain a reasonable current limit, the voltage on the VRNG pin is reduced to 0.5V by connecting it between INTVCC and GND, corresponding to a 50mV nominal sense voltage. Next, the gain of the LTC3714 error amplifier must be determined. The change in ITH voltage for a corresponding change in the output current is: 12V ∆ITH = RSENSE ∆IOUT VRNG = (24)(0.003Ω)(15A ) = 1.08V The corresponding change in the output voltage is determined by the gain of the error amplifier and feedback divider. The LTC3714 error amplifier has a transconductance gm that is constant over both temperature and a wide ± 40mV input range. Thus, by connecting a load resistance RVP to the ITH pin, the error amplifier gain can be precisely set for accurate voltage positioning. 0.6V ∆ITH = gm RVP ∆VOUT VOUT 3714f 22 LTC3714 U W U U APPLICATIO S I FOR ATIO Solving for this resistance value: nominal value of the ITH pin voltage when the error amplifier input is zero. To set the beginning of the load line at the regulation point, the ITH pin voltage must be set to correspond to zero output current. The relation between voltage and the output current is: VOUT ∆ITH (0.6V)gm ∆VOUT (1.15V)(1.08V) = = 20.3k (0.6V)(1.7mS)(60mV) RVP = 12V 1 ITH(NOM) = RSENSE IOUT – ∆IL + 0.75V VRNG 2 The gain setting resistance RVP is implemented with two resistors, RVP1 connected from ITH to ground and RVP2 connected from ITH to INTVCC. The parallel combination of these resistors must equal RVP and their ratio determines 9 CSS 0.1µF 10 11 RRNG1 RRNG2 10k 90.1k RPG 100k 12 13 CC1 2.2nF RC 20k VID2 VID1 RUN/SS VID0 VON BOOST TG PGOOD SW VRNG 1 12V = (0.003Ω) 0A – 5.4A + 0.75V 0.5V 2 = 0.55V 8 7 DB CMDSH-3 6 CB 0.33µF 5 M1 L1 IRF7811 0.68µH 4 M2 IRF7811 ×2 LTC3714 RVP2 185k 14 RVP1 23k CC1 100pF 19 ITH SGND SENSE PGND ION BG VFB INTVCC 20 FCB VIN 23 24 RON 330k INTVCC 0.1µF 15 16 CIN: UNITED CHEMICON THCR70EIH226ZT COUT: PANASONIC EEFUE0D271 L1: SUMIDA CEP125-4712-T007 VOSENSE VID3 OPVIN OP – EXTVCC VID4 OPOUT OP + VIN 7V TO 24V VOUT 1.15V/15A COUT 270µF 2V ×3 RSENSE 0.003Ω 2 1 CVCC 4.7µF CFB 100pF 22 D1 UPS840 3 CION 0.01µF 21 CIN 10µF 25V ×3 28 RF 1Ω 27 26 5V CF 0.1µF 25 18 17 3714 F08 Figure 9. CPU Core Voltage Regulator with Active Voltage Positioning 1.15V/15A at 300kHz 3714f 23 LTC3714 U W U U APPLICATIO S I FOR ATIO Solving for the required values of the resistors: RVP1 = The modified circuit is shown in Figure 9. Refer to Linear Technology Design Solutions 10 for additional information about output voltage positioning. 5V 5V RVP = 20.3k 5V – ITH(NOM) 5V – 0.55V PC Board Layout Checklist = 23k RVP2 = 5V ITH(NOM) RVP When laying out the printed circuit board, use the following checklist to ensure proper operation of the controller. 5V = 20.3k = 185k 0.55V CVCC + VIN LTC3714 M1 CIN 1 D1 M2 INTVCC 28 CF – 2 PGND – VOUT BG 3 COUT DB + 4 5 SENSE VIN EXTVCC SW VID4 TG VID3 27 26 RF 25 RON 24 CB 6 7 BOOST VOSENSE VID0 VFB 23 22 CION 8 9 VID1 ION VID2 FCB 21 CFB 20 CSS 10 11 12 13 CC1 RC 14 RUN/SS VON SGND 19 OPOUT 18 PGOOD OP + 17 VRNG OP – 16 ITH OPVIN 15 CC2 BOLD LINES INDICATE HIGH CURRENT PATHS 3714 F10 Figure 10. LTC3714 Layout Diagram 3714f 24 LTC3714 U W U U APPLICATIO S I FOR ATIO These items are also illustrated in Figures 10 and 11. • Segregate the signal and power grounds. All small signal components should return to the SGND pin at one point which is then tied to the PGND pin close to the source of M2. • Place M2 as close to the controller as possible, keeping the PGND, BG and SENSE traces short. • Connect the input capacitor(s) CIN close to the power MOSFETs. This capacitor carries the MOSFET AC current. • Keep the high dV/dT SW, BOOST and TG nodes away from sensitive small-signal nodes. • Connect the INTVCC decoupling capacitor CVCC closely to the INTVCC and PGND pins. • Connect the top driver boost capacitor CB closely to the BOOST and SW pins. • Connect the VIN pin decoupling capacitor CF closely to the VIN and PGND pins. • VID0-VID4 interface circuitry must return to SGND. VIN CIN CIN CIN TO PGND (PIN 2) PGND CIN RSENSE SW M1 M2 D1 M1 SENSE TO SENSE (PIN 3) M2 M2 L1 PGND COUT COUT COUT COUT VOUT 3714 F11 Figure 11. General Layout of External Power Components 3714f 25 LTC3714 U TYPICAL APPLICATIO Performance Data for Intel Compatible Mobile Microprocessor Power Supply with Active Voltage Positioning Line Transient Reponse from VIN = 9V to 17V Load Transient Reponse for IOUT = 8A to 23A VIN 5V/DIV 1.395V VOUT (1.35V) 50mV/DIV 1.213V VOUT 50mV/DIV AC COUPLED 23A ILOAD 10A/DIV 8A 50µs/DIV 20µs/DIV 3714 TA02 3714 TA03 Efficiency 95 VOUT = 1.35V EFFICIENCY (%) 90 VIN = 8.5V VIN = 15V 85 VIN = 24V 80 75 70 0 3 6 9 12 15 18 LOAD CURRENT (A) 21 3714 TA04 3714f 26 LTC3714 U TYPICAL APPLICATIO Transmeta CrusoeTM Microprocessor Power Supply with Active Voltage Positioning 200k VID2 3.3V INTVCC VID1 VID0 VRON 9 VIN 1µF 0.1µF 10 1k 0.01µF 11 VOUT 100Ω 3.3V LTC3714EG VID2 VID1 RUN/SS VID0 8 200k 7 200k CMDSH-3 1k 2k U1 BAT54 1M 3.2k 12 POWER GOOD VON BOOST TG PGOOD 6 5 IRF7811 0.22µF 220pF 10k 13 20k SW VRNG 820pF SENSE 13k 1% 80.6k 1% 14 19 0.1µF PGND ITH BG SGND 3 10k 1 IRF7811 4.7µF 20 21 330k INTVCC FCB + 2 BAT54 1000pF VOUT 0.6V To 1.75V 8A COUT 270µF 2V ×2 1µF 6.3V MBRS340 28 1Ω VIN ION 0.005Ω 0.1µF VIN 22 100pF 23 VID3 200k 24 3.3V DPSLP LTC3714EG 4 L1 1.8µH VIN 5V TO 24V CIN 10µF 35V ×2 VFB VIN VOSENSE VID4 EXTVCC VID3 27 25 26 3.3V 200k 5V VID4 BAT54C 18 START R22 100k 15 OPOUT OP + 17 OPVIN OP – 16 0.01µF 75k 1% VOUT 100k 1% START 453k 1% DPSLP 3714 TA01 U PACKAGE DESCRIPTIO G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 5.20 – 5.38** (.205 – .212) 1.73 – 1.99 (.068 – .078) 10.07 – 10.33* (.397 – .407) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0° – 8° .13 – .22 (.005 – .009) .65 (.0256) BSC .55 – .95 (.022 – .037) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 7.65 – 7.90 (.301 – .311) .25 – .38 (.010 – .015) .05 – .21 (.002 – .008) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 G28 SSOP 0501 Crusoe is a trademark of Transmeta Corporation. 3714f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC3714 U TYPICAL APPLICATIO Intel Compatible Mobile Microprocessor Power Supply with Active Voltage Positioning 3.3V INTVCC 200k 3.3V 2k VRON 9 100Ω 1µF VID2 VID1 RUN/SS VID0 8 200k 7 200k 0.1µF 1k 10 7V ≤ VIN ≤ 24V POWER GOOD 11 3.2k 12 10k 13 VON BOOST PGOOD TG VRNG SW SENSE 220pF 20k 200k 1% INTVCC 14 19 220pF LTC3714 PGND ITH BG SGND 6 0.22µF 5 IRF7811 ×2 L1 0.68µH CIN 10µF 35V ×4 VOUT 0.6V TO 1.75V 23A 4 3 CMDSH-3 IRF7811 ×3 2 MBRS 340T3 RSENSE 0.003Ω + COUT 270µF 2V ×4 1 10nF 21 20.5k 1% INTVCC ION 28 + 100pF 22 20 1k 23 200k 3.3V 24 18 15 INTVCC VFB 1Ω FCB VIN VOSENSE VID4 EXTVCC VID3 4.7µF 10V 27 25 26 OPOUT 17 OP + OPVIN OP – 0.1µF 200k 3.3V 5V 806k 1% 16 10k 1% 0.1µF GMUXSEL 10k 1% 330k INTVCC 806k 1% 10k 277k 1% 100Ω DPSLP# DPRSLPVR 3714 TA01 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1778 Low Duty Cycle, No RSENSETM Step-Down Controller GN-16 Package, 0.8V Reference, Burst Mode Operation LTC3711 5-Bit Adjustable, Low Duty Cycle, No RSENSE, Step-Down Controller GN-24 Package, 5-Bit VID, 0.8VREF, Burst Mode Operation, 0.925V ≤ VOUT ≤ 2V LTC3716 Dual Phase, High Efficiency Step-Down Controller 2-Phase, 5-Bit VID (0.6V to 1.75V), Narrow 36-Pin SSOP, 3.5V ≤ VIN ≤ 36V LTC3778 Wide VIN, No RSENSE Step-Down Controller 4V ≤ VIN ≤ 36V, True Current Mode Control, 1A ≤ IOUT ≤ 20A No RSENSE is a trademark of Linear Technology Corporation. 3714f 28 Linear Technology Corporation LT/TP 0602 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001