TC55VZM216AJJN/AFTN08,10,12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 262,144-WORD BY 16-BIT CMOS STATIC RAM DESCRIPTION The TC55VZM216AJJN/AFTN is a 4,194,304-bit high-speed static random access memory (SRAM) organized as 262,144 words by 16 bits. Fabricated using CMOS technology and advanced circuit techniques to provide high speed, it operates from a single 3.3 V power supply. Chip enable ( CE ) can be used to place the device in a low-power mode, and output enable ( OE ) provides fast memory access. Data byte control signals ( LB , UB ) provide lower and upper byte access. This device is well suited to cache memory applications where high-speed access and high-speed storage are required. All inputs and outputs are directly LVTTL compatible. The TC55VZM216AJJN/AFTN is available in plastic 44-pin SOJ and TSOP with 400mil width for high density surface assembly. FEATURES • • Fast access time (the following are maximum values) TC55VZM216AJJN/AFTN08:8 ns TC55VZM216AJJN/AFTN10:10 ns TC55VZM216AJJN/AFTN12:12 ns Low-power dissipation (IDDO2) (the following are maximum values) Cycle Time 8 10 12 ns Operation (max) 140 130 120 mA • • • • • • Single power supply voltage of 3.3 V ± 0.3 V Fully static operation All inputs and outputs are LVTTL compatible Output buffer control using OE Data byte control using LB (I/O1 to I/O8) and UB (I/O9 to I/O16) Package: SOJ44-P-400-1.27 (AJJN) (Weight: 1.64 g typ) TSOP II44-P-400-0.80 (AFTN) (Weight: 0.45 g typ) Standby:4 mA (both devices) PIN ASSIGNMENT (TOP VIEW) PIN NAMES 44 PIN TSOP 44 PIN SOJ A0 to A17 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 (TC55VZM216AJJN) A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VDD GND I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 GND VDD I/O12 I/O11 I/O10 I/O9 NU A8 A9 A10 A11 A17 I/O1 to I/O16 Address Inputs Data Inputs/Outputs CE Chip Enable Input WE Write Enable Input OE Output Enable Input LB , UB Data Byte Control Inputs VDD Power (+3.3 V) GND Ground NU Not Usable (Input) (TC55VZM216AFTN) 2003-01-17 1/11 TC55VZM216AJJN/AFTN08,10,12 DATA INPUT BUFFER I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I/O16 VDD GND MEMORY CELL ARRAY 1,024 × 256 × 16 (4,194,304) CE DATA OUTPUT BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA INPUT BUFFER ROW ADDRESS BUFFER A0 A1 A4 A5 A8 A9 A13 A14 A15 A17 ROW DECODER BLOCK DIAGRAM DATA OUTPUT BUFFER SENSE AMP COLUMN DECODER CE COLUMN ADDRESS BUFFER CLOCK GENERATOR A2 A3 A6 A7 A10 A11 A12 A16 WE OE UB LB CE CE MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VDD Power Supply Voltage −0.5 to 4.6 V VIN Input Terminal Voltage −0.5* to 4.6 V VI/O Input/Output Terminal Voltage −0.5* to VDD + 0.5** V PD Power Dissipation 1.4 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −65 to 150 °C Topr Operating Temperature −10 to 85 °C *: −1.5 V with a pulse width of 20% of tRC min (4 ns max) **: VDD + 1.5 V with a pulse width of 20% of tRC min (4 ns max) 2003-01-17 2/11 TC55VZM216AJJN/AFTN08,10,12 DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C) SYMBOL PARAMETER MIN TYP MAX UNIT VDD Power Supply Voltage 3.0 3.3 3.6 V VIH Input High Voltage 2.0 VDD + 0.3** V VIL Input Low Voltage −0.3* 0.8 V *: −1.0 V with a pulse width of 20% of tRC min (4 ns max) **: VDD + 1.0 V with a pulse width of 20% of tRC min (4 ns max) DC CHARACTERISTICS (Ta = 0° to 70°C, VDD = 3.3 V ± 0.3 V) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT −1 1 µA −1 1 µA −1 1 µA 2.4 VDD − 0.2 IOL = 2 mA 0.4 IOL = 100 µA 0.2 tcycle = 8 ns 170 IIL Input Leakage Current VIN = 0 to VDD (Except NU pin) ILO Output Leakage Current II (NU) Input Leakage Current VIN = 0 V (NU pin) VOH Output High Voltage VOL Output Low Voltage CE = VIH or WE = VIL or OE = VIH, VOUT = 0 to VDD IOH = −2 mA IOH = −100 µA CE = VIL, IOUT = 0 mA, IDDO1 OE = VIH, tcycle = 10 ns 160 Other Input = VIH/VIL tcycle = 12 ns 150 CE = 0.2 V, IOUT = 0 mA, tcycle = 8 ns 140 OE = VDD − 0.2 V, tcycle = 10 ns 130 Other Input = VDD − 0.2 V/0.2 V tcycle = 12 ns 120 CE = VIH, Other Input = VIH or VIL 55 CE = VDD − 0.2 V, Other Input = VDD − 0.2 V or 0.2 V 4 Operating Current IDDO2 IDDS1 Standby Current IDDS2 V mA mA CAPACITANCE (Ta = 25°C, f = 1 .0 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 6 pF CI/O Input/Output Capacitance VI/O = GND 8 pF Note: This parameter is periodically sampled and is not 100% tested. 2003-01-17 3/11 TC55VZM216AJJN/AFTN08,10,12 OPERATING MODE MODE Read CE L Write L OE L * WE H L LB UB L L Output Output IDDO H L High Impedance Output IDDO L H Output High Impedance IDDO L L Input Input IDDO H L High Impedance Input IDDO L H Input High Impedance IDDO High Impedance High Impedance IDDO High Impedance High Impedance IDDS L H H * * L * * H H H * * * * Outputs Disable Standby I/O1 to I/O8 I/O9 to I/O16 POWER * : Don’t care Note: The NU pin must be left unconnected or tied to GND. You must not apply a voltage of more than 0.8 V to the NU. 2003-01-17 4/11 TC55VZM216AJJN/AFTN08,10,12 AC CHARACTERISTICS (Ta = 0° to 70°C (See Note 1) , VDD = 3.3 V ± 0.3 V) READ CYCLE TC55VZM216AJJN/AFTN SYMBOL PARAMETER 08 10 UNIT 12 MIN MAX MIN MAX MIN MAX tRC Read Cycle Time 8 10 12 tACC Address Access Time 8 10 12 tCO Chip Enable Access Time 8 10 12 tOE Output Enable Access Time 4 5 6 tBA Upper Byte, Lower Byte Access Time 4 5 6 tOH Output Data Hold Time from Address Change 3 3 3 tCOE Output Enable Time from Chip Enable 3 3 3 tOEE Output Enable Time from Output Enable 0 0 0 tBE Output Enable Time from Upper Byte, Lower Byte 0 0 0 tCOD Output Disable Time from Chip Enable 4 5 6 tODO Output Disable Time from Output Enable 4 5 6 tBD Output Disable Time from Upper Byte, Lower Byte 4 5 6 ns WRITE CYCLE TC55VZM216AJJN/AFTN SYMBOL PARAMETER 08 10 UNIT 12 MIN MAX MIN MAX MIN MAX tWC Write Cycle Time 8 10 12 tWP Write Pulse Width 6 7 8 tCW Chip Enable to End of Write 6 7 8 tBW Upper Byte, Lower Byte Enable to End of Write 6 7 8 tAW Address Valid to End of Write 6 7 8 tAS Address Setup Time 0 0 0 tWR Write Recovery Time 0 0 0 tDS Data Setup Time 4 5 6 tDH Data Hold Time 0 0 0 tOEW Output Enable Time from Write Enable 3 3 3 tODW Output Disable Time from Write Enable 4 5 6 AC TEST CONDITIONS ns Fig.1 3.3 V PARAMETER Input Pulse Level TEST CONDITION 3.0 V/ 0.0 V Input Pulse Rise and Fall Time 2 ns Input Timing Measurement Reference Level 1.5 V Output Timing Measurement Reference Level 1.5 V Output Load Fig.1 1200 Ω I/O pin Z0 = 50 Ω CL = 30 pF I/O pin RL = 50 Ω VL = 1.5 V CL = 5 pF 870 Ω (For tCOE, tOEE, tBE, tCOD, tBD, tODO, tOEW and tODW ) 2003-01-17 5/11 TC55VZM216AJJN/AFTN08,10,12 TIMING DIAGRAMS READ CYCLE (See Note 2) tRC Address tACC tOH tCO CE tOE (See Note 6) tCOD OE tBA (See Note 6) tODO UB , LB (See Note 6) tBE tOEE DOUT tBD (See Note 6) (See Note 6) VALID DATA OUT Hi-Z tCOE Hi-Z (See Note 6) INDETERMINATE WRITE CYCLE 1 ( WE CONTROLLED) INDETERMINATE (See Note 5) tWC tAW Address tAS tWP tWR WE tCW CE tBW UB , LB tODW DOUT (See Note 3) INDETERMINATE DIN (See Note 6) tOEW Hi-Z tDS (See Note 6) (See Note 4) tDH INDETERMINATE VALID DATA IN 2003-01-17 6/11 TC55VZM216AJJN/AFTN08,10,12 WRITE CYCLE 2 ( CE CONTROLLED) (See Note 5) tWC tAW Address tAS tWP tWR WE tCW CE tBW UB , LB (See Note 6) DOUT Hi-Z tBE tODW (See Note 6) Hi-Z tCOE (See Note 6) INDETERMINATE tDS tDH VALID DATA IN DIN WRITE CYCLE 2 ( UB, LB CONTROLLED) (See Note 5) tWC tAW Address tAS tWP tWR WE tCW CE tBW UB , LB (See Note 6) DOUT tCOE tODW (See Note 6) Hi-Z Hi-Z tBE (See Note 6) INDETERMINATE tDS DIN tDH VALID DATA IN 2003-01-17 7/11 TC55VZM216AJJN/AFTN08,10,12 Note: (1) Operating temperature (Ta) is guaranteed for transverse air flow exceeding 400 linear feet per minute. (2) WE remains HIGH for the Read Cycle. (3) If CE goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedance. (4) If CE goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedance. (5) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (6) The parameters specified below are measured using the load shown in Fig.1. (A) tCOE, tOEE, tBE, tOEW ････････････ Output Enable Time (B) tCOD, tODO, tBD, tODW ････････････ Output Disable Time CE , OE UB , LB WE (A) (B) 0.2 V DOUT Hi-Z 0.2 V 0.2 V INDETERMINATE VALID DATA OUT Hi-Z INDETERMINATE 0.2 V 2003-01-17 8/11 TC55VZM216AJJN/AFTN08,10,12 PACKAGE DIMENSIONS SOJ44-P-400-1.27 Weight: 1.64 g (typ) 2003-01-17 9/11 TC55VZM216AJJN/AFTN08,10,12 PACKAGE DIMENSIONS Weight: 0.45 g (typ) 2003-01-17 10/11 TC55VZM216AJJN/AFTN08,10,12 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • • • The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 2003-01-17 11/11