TC55V040AFT-55,-70 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT FULL CMOS STATIC RAM DESCRIPTION The TC55V040AFT is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 0.5 µA standby current (at VDD = 3 V, Ta = 25°C, maximum) when chip enable ( CE1 ) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed operating extreme temperature range of −40° to 85°C, the TC55V040AFT can be used in environments exhibiting extreme temperature conditions. The TC55V040AFT is available in normal and reverse pinout plastic 40-pin thin-small-outline package (TSOP). FEATURES • • • • • • • • Low-power dissipation Operating: 10.8 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE1 and CE2 Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): 3.6 V 7 µA 3.0 V 5 µA Access Times (maximum): TC55V040AFT • -55 -70 Access Time 55 ns 70 ns CE1 Access Time 55 ns 70 ns CE2 Access Time 55 ns 70 ns OE Access Time 30 ns 35 ns Package: TSOPⅠ40-P-1014-0.50 (AFT) (Weight: 0.32 g typ) PIN ASSIGNMENT (TOP VIEW) PIN NAMES 40 PIN TSOP 1 A0~A18 40 CE1 , CE2 20 (Normal) Chip Enable R/W Read/Write Control OE Output Enable I/O1~I/O8 21 Address Inputs Data Inputs/Outputs VDD Power GND Ground NC No Connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name A16 A15 A14 A13 A12 A11 A9 A8 R/W CE2 NC NC A18 A7 A6 A5 A4 A3 A2 A1 Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Name A0 CE1 GND OE I/O1 I/O2 I/O3 I/O4 NC VDD VDD I/O5 I/O6 I/O7 I/O8 A10 NC NC GND A17 2003-08-06 1/11 TC55V040AFT-55,-70 BLOCK DIAGRAM VDD GND ROW ADDRESS DECODER ROW ADDRESS REGISTER MEMORY CELL ARRAY 2,048 × 256 × 8 (4,194,304) 8 SENSE AMP COLUMN ADDRESS DECODER CLOCK GENERATOR I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA CONTROL A4 A5 A6 A7 A8 A9 A11 A12 A13 A14 A18 ROW ADDRESS BUFFER CE COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A0 A1 A2 A3 A10A15A16 A17 OE R/W CE1 CE CE2 OPERATING MODE MODE CE1 CE2 OE R/W Read L H L H Output IDDO Write L H * L Input IDDO Output Deselect Standby I/O1~I/O8 POWER L H H H High-Z IDDO H * * * High-Z IDDS * L * * High-Z IDDS * = don't care H = logic high L = logic low MAXIMUM RATINGS SYMBOL RATING VALUE UNIT VDD Power Supply Voltage −0.3~4.6 V VIN Input Voltage −0.3*~4.6 V VI/O Input/Output Voltage −0.5~VDD + 0.5 V PD Power Dissipation 0.6 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −55~150 °C Topr Operating Temperature −40~85 °C *: −3.0 V when measured at a pulse width of 50ns 2003-08-06 2/11 TC55V040AFT-55,-70 DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) 2.3 V~3.6 V SYMBOL PARAMETER UNIT MIN TYP MAX VDD Power Supply Voltage 2.3 3.0 3.6 V VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage −0.3* VDD × 0.22 V VDH Data Retention Supply Voltage 1.5 3.6 V *: −3.0 V when measured at a pulse width of 50 ns DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) SYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT ±1.0 µA IIL Input Leakage Current VIN = 0 V~VDD IOH Output High Current VOH = VDD − 0.5 V −0.5 mA IOL Output Low Current VOL = 0.4 V 2.1 mA ILO Output Leakage Current CE1 = VIH or CE2 = VIL or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ±1.0 µA 55 ns 60 70 ns 50 1 µs 10 55 ns 55 70 ns 45 1 µs 5 2 Ta = 25°C 0.6 Ta = −40~85°C 6 Ta = 25°C 0.7 Ta = −40~85°C 7 Ta = 25°C 0.05 0.5 Ta = −40~40°C 1 Ta = −40~85°C 5 CE1 = VIL and CE2 = VIH and R/W = VIH and IOUT = 0 mA, Other Input = VIH/VIL lDDO1 VDD = tcycle 3 V ± 10% Operating Current CE1 = 0.2 V and CE2 = VDD − 0.2 V and VDD = tcycle R/W = VDD − 0.2 V, IOUT = 0 mA, 3 V ± 10% Other Input = VDD − 0.2 V/0.2 V lDDO2 CE = VIH or CE2 = VIL IDDS1 VDD = 3 V ± 10% CE1 = VDD − 0.2 V or CE2 = 0.2 V VDD = 1.5 V~3.6 V Standby Current IDDS2 (Note) VDD = 3.3 V ± 0.3 V VDD = 3.0 V Note: mA mA mA µA In standby mode with CE1 ≥ VDD − 0.2 V, these limits are assured for the condition CE2 ≥ VDD − 0.2 V or CE2 ≤ 0.2 V. CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 2003-08-06 3/11 TC55V040AFT-55,-70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE TC55V040AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tRC Read Cycle Time 55 70 tACC Address Access Time 55 70 tCO1 Chip Enable( CE1 ) Access Time 55 70 tCO2 Chip Enable(CE2) Access Time 55 70 tOE Output Enable Access Time 30 35 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tOD Chip Enable High to Output High-Z 25 30 tODO Output Enable High to Output High-Z 25 30 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55V040AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tWC Write Cycle Time 55 70 tWP Write Pulse Width 45 50 tCW Chip Enable to End of Write 50 60 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 25 30 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 25 30 tDH Data Hold Time 0 0 ns AC TEST CONDITIONS PARAMETER Output load Input pulse level TEST CONDITION 30 pF + 1 TTL Gate 0.4 V, 2.4 V Timing measurements VDD × 0.5 Reference level VDD × 0.5 tR, tF 5 ns 2003-08-06 4/11 TC55V040AFT-55,-70 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) READ CYCLE TC55V040AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tRC Read Cycle Time 70 85 tACC Address Access Time 70 85 tCO1 Chip Enable( CE1 ) Access Time 70 85 tCO2 Chip Enable(CE2) Access Time 70 85 tOE Output Enable Access Time 35 45 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tOD Chip Enable High to Output High-Z 30 35 tODO Output Enable High to Output High-Z 30 35 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55V040AFT SYMBOL PARAMETER -55 UNIT -70 MIN MAX MIN MAX tWC Write Cycle Time 70 85 tWP Write Pulse Width 50 55 tCW Chip Enable to End of Write 60 70 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 30 35 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 30 35 tDH Data Hold Time 0 0 ns AC TEST CONDITIONS PARAMETER TEST CONDITION Output load 30 pF + 1 TTL Gate Input pulse level VDD − 0.2 V, 0.2 V Timing measurements VDD × 0.5 Reference level VDD × 0.5 tR, tF 5 ns 2003-08-06 5/11 TC55V040AFT-55,-70 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address tACC tOH tCO1 CE1 tCO2 CE2 tOE tOD OE tOEE DOUT tODO Hi-Z VALID DATA OUT Hi-Z tCOE INDETERMINATE WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tOEW tODW DOUT (See Note 2) Hi-Z tDS DIN (See Note 5) (See Note 3) tDH VALID DATA IN (See Note 5) 2003-08-06 6/11 TC55V040AFT-55,-70 WRITE CYCLE 2 ( CE1 CONTROLLED) (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tCOE DOUT tODW Hi-Z Hi-Z tDS DIN (See Note 5) WRITE CYCLE 3 (CE2 CONTROLLED) tDH VALID DATA IN (See Note 4) tWC Address tAS tWP tWR R/W tCW CE1 tCW CE2 tCOE DOUT tODW Hi-Z Hi-Z tDS DIN (See Note 5) tDH VALID DATA IN 2003-08-06 7/11 TC55V040AFT-55,-70 Note: (1) R/W remains HIGH for the read cycle. (2) If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL PARAMETER VDH MIN TYP MAX UNIT 1.5 3.6 V Ta = −40~40°C 1 Ta = −40~85°C 5 VDH = 3.6 V Ta = −40~85°C 7 0 ns ns Data Retention Supply Voltage VDH = 3.0 V IDDS2 Standby Current tCDR Chip Deselect to Data Retention Mode Time tR Recovery Time Note: (See Note) tRC µA Read cycle time CE1 CONTROLLED DATA RETENTION MODE VDD VDD (See Note 1) DATA RETENTION MODE 2.7 V (See Note 2) (See Note 2) VIH tCDR CE1 VDD − 0.2 V TR GND CE2 CONTROLLED DATA RETENTION MODE VDD VDD (See Note 3) DATA RETENTION MODE 2.7 V CE2 VIH VIL tCDR tR 0.2 V GND 2003-08-06 8/11 TC55V040AFT-55,-70 Note: (1) In CE1 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V or CE2 ≥ VDD − 0.2 V. (2) When CE1 is operating at the VIH level (2.2V), the operating current is given by IDDS1 during the transition of VDD from 3.6 to 2.4V. (3) In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 ≤ 0.2 V. 2003-08-06 9/11 TC55V040AFT-55,-70 PACKAGE DIMENSIONS Weight: 0.32 g (typ) 2003-08-06 10/11 TC55V040AFT-55,-70 RESTRICTIONS ON PRODUCT USE 030619EBA • The information contained herein is subject to change without notice. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2003-08-06 11/11