FAIRCHILD 100395

Revised November 1999
100395
Low Power 9-Bit ECL-to-TTL Translator with Registers
General Description
Features
The 100395 is a 9-bit translator for converting F100K logic
levels to TTL logic levels. A HIGH on the output enable
(OE) holds the TTL outputs in a high impedance state. Two
separate clock inputs are available for multiplexing and
system level testing.
■ 64 mA IOL drive capability
The 100395 is designed with TTL 64 mA outputs for bus
driving capability. All inputs have 50 kΩ pull down resistors.
When the inputs are either unconnected or at the same
potential, the outputs will go LOW.
■ TTL outputs
■ 2000V ESD protection
■ −4.2V to −5.7V operating range
■ Registered outputs
Ordering Code:
Order Number
Package Number
100395QC
V28A
Package Description
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Truth Table
Pin Names
Description
D0–D8
Data Inputs (ECL)
Q0–Q8
Data Outputs (TTL)
OE
Output Enable (ECL)
CP1, CP2
Clock Inputs (ECL)
Inputs
CP1
CP2
OE
DN
L
L
L
L
L
L
L
L
L
L
DS010651
QN
L
H
H
L
H
H
NC
H
X
X
X
X
H
X
X
NC
L
L
X
X
NC
X
X
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
© 1999 Fairchild Semiconductor Corporation
Outputs
Z = High Impedance
NC = No Change
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100395 Low Power 9-Bit ECL-to-TTL Translator with Registers
February 1990
100395
Logic Diagram
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2
Recommended Operating
Conditions
−65°C to +150°C
Storage Temperature (TSTG)
+150°C
Maximum Junction Temperature (TJ)
VEE Pin Potential to Ground Pin
−7.0V to +0.5V
VTTL Pin Potential to Ground Pin
−0.5V to +6.0V
Supply Voltage
VEE to +0.5V
ECL Input Voltage (DC)
Output Current
+130 mA
(DC Output HIGH)
≥ 2000V
ESD (Note 2)
VEE
−5.7V to −4.2V
VTTL
+4.5V to +5.5V
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
−0.5V to +7.0V
TTL Input Voltage
0°C to +85°C
Case Temperature (TC)
0°C to +85°C
Case Temperature under Bias (TC)
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics (Note 3)
VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C
Symbol
Parameter
Min
Typ
Max
2.4
Units
Conditions
V
IOH = −15 mA
VIN = VIH (Max)
V
IOL = 64 mA
or VIL (Min)
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
−1165
−870
mV
Guaranteed HIGH Signal for All Inputs
VIL
Input LOW Voltage
−1830
−1475
mV
Guaranteed LOW Signal for All Inputs
0.5
0.55
IIL
Input LOW Current
µA
VIN = VIL (Min)
IIH
Input HIGH Current
240
µA
VIN = VIH (Max)
IOZL
3-STATE Current Output HIGH
−50
µA
VOUT = +0.4V
IOZH
3-STATE Current Output LOW
+50
µA
VOUT = +2.7V
ICEX
Output HIGH Leakage Current
250
µA
VOUT = VCC
IOS
Output Short-Circuit Current
−100
−225
mA
−67
−29
mA
29
mA
IEE
VEE Power Supply Current
ICCH
VTTL Power Supply Current HIGH
ICCL
VTTL Power Supply Current LOW
65
mA
ICCZ
VTTL Power Supply Current 3-STATE
49
mA
Inputs OPEN
Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions.
PLCC AC Electrical Characteristics
VEE = −4.2V to −5.7V, VCC = GND, VTTL = +4.5V to +5.5V
Symbol
Parameter
tPLH
Propagation Delay
TC = 0°C
TC = +25°C
TC = +85°C
Min
Max
Min
Max
Min
Max
2.30
5.00
2.30
5.00
2.30
5.00
tPHL
Clock to Output
3.00
5.60
3.00
5.60
3.40
6.40
tPZL
Output Enable Time
3.20
7.60
3.20
7.60
3.20
7.60
tPZH
OE ↓ to QN
2.40
5.60
2.40
5.60
2.40
5.60
tPLZ
Output Disable Time
3.20
7.60
3.20
7.60
3.20
7.60
tPHZ
OE ↑ to QN
2.40
5.60
2.40
5.60
2.40
5.60
tH
Data to CP EN
1.5
1.5
1.5
Hold Time
1.5
1.5
1.5
Data to CP EN
0.5
0.5
0.5
Setup Time
0.5
0.5
0.5
Clock Pulse Width
2.0
2.0
2.0
tS
tPW(H)
3
Units
Conditions
ns
Figures 1, 2
ns
Figures 1, 3
ns
Figures 1, 3
ns
Figures 1, 2
ns
Figures 1, 2
ns
Figures 1Figure 2
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100395
Absolute Maximum Ratings(Note 1)
100395
Test Circuit
Notes:
VCC = 0V, VCCA = 0V, VEE = −4.5V, VTTL = +5V.
All unused outputs are loaded with 500Ω to GND. Decoupling capacitors are necessary in the test and end application environment. When VCC and VCCA are
common to a single power plane, typically 0.0V, decouple VTTL to that plane with one 0.01 µF capacitor.
FIGURE 1. AC Test Circuit
Switch Positions for Parameter Testing
Parameter
S-Position
tPLH, tPHL
Open
tPHZ, tPZH
Open
tPLZ, tPZL
Closed
Switching Waveforms
FIGURE 2. Propagation Delay and Transition Times
FIGURE 3. Enable and Disable Waveforms, OE to QN
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100395 Low Power 9-Bit ECL-to-TTL Translator with Registers
Physical Dimensions inches (millimeters) unless otherwise noted
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Package Number V28A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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SEMICONDUCTOR CORPORATION. As used herein:
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user.
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