Revised March 2001 100324 Low Power Hex TTL-to-ECL Translator General Description Features The 100324 is a hex translator, designed to convert TTL logic levels to 100K ECL logic levels. The inputs are compatible with standard or Schottky TTL. A common Enable (E), when LOW, holds all inverting outputs HIGH and holds all true outputs LOW. The differential outputs allow each circuit to be used as an inverting/non-inverting translator, or as a differential line driver. The output levels are voltage compensated over the full −4.2V to −5.7V range. ■ Pin/function compatible with 100124 When the circuit is used in the differential mode, the 100324, due to its high common mode rejection, overcomes voltage gradients between the TTL and ECL ground systems. The VEE and VTTL power may be applied in either order. ■ Available to industrial grade temperature range ■ Meets 100124 AC specifications ■ 50% power reduction of the 100124 ■ Differential outputs ■ 2000V ESD protection ■ −4.2V to −5.7V operating range ■ Available to MIL-STD-883 (PLCC package only) The 100324 is pin and function compatible with the 100124 with similar AC performance, but features power dissipation roughly half of the 100124 to ease system cooling requirements. Ordering Code: Order Number Package Number Package Description 100324SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 100324PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide 100324QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square 100324QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Industrial Temperature Range (−40°C to +85°C) Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 24-Pin DIP/SOIC © 2001 Fairchild Semiconductor Corporation 28-Pin PLCC DS009878 www.fairchildsemi.com 100324 Low Power Hex TTL-to-ECL Translator July 1988 100324 Pin Descriptions Pin Names Truth Table Description Inputs Outputs D0–D5 Data Inputs Dn E Qn E Enable Input X L L H Q0–Q5 Data Outputs L H L H Q0–Q5 Complementary H H H L Data Outputs H = HIGH Voltage Level L = LOW Voltage Level Logic Diagram www.fairchildsemi.com 2 Qn Storage Temperature (TSTG) Recommended Operating Conditions −65°C to +150°C +150°C Maximum Junction Temperature (TJ) VEE Pin Potential to Ground Pin −7.0V to +0.5V VTTL Pin Potential to Ground Pin −0.5V to +6.0V Input Voltage (DC) −0.5V to +6.0V Output Current (DC Output HIGH) −50 mA ESD (Note 2) ≥2000V 100324 Absolute Maximum Ratings(Note 1) Case Temperature (TC) 0°C to +85°C Commercial −40°C to +85°C Industrial −5.7V to −4.2V Supply Voltage (VEE) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2: ESD testing conforms to MIL-STD-883, Method 3015. Commercial Version DC Electrical Characteristics (Note 3) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C, VTTL = +4.5V to +5.5V Min Typ Max VOH Symbol Output HIGH Voltage Parameter −1025 −955 −870 Units VOL Output LOW Voltage −1830 −1705 −1620 VOHC Output HIGH Voltage −1035 VOLC Output LOW Voltage VIH Input HIGH Voltage 2.0 5.0 V VIL Input LOW Voltage 0 0.8 V −1610 Conditions mV mV VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH(Min) Loading with or VIL (Max) 50Ω to −2.0V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VCD Input Clamp Diode Voltage IIH Input HIGH Current −1.2 IIN = −18 mA µA All Other Inputs VIN = GND VIN = +2.4V, Data 20 Enable 120 Input HIGH Current 1.0 Breakdown Test, All Inputs IIL V VIN = +5.5V, mA All Other Inputs = GND VIN = +0.4V, Input LOW Current Data −0.9 Enable −5.4 IEE VEE Power Supply Current −70 ITTL VTTL Power Supply Current All Other Inputs VIN = VIH mA −45 −22 mA All Inputs VIN = +4.0V 25 38 mA All Inputs VIN = GND Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. DIP AC Electric Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V TC = +25°C TC = 0°C Symbol Parameter Min Max Min Max tPLH Propagation Delay tPHL Data and Enable to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% TC = +85°C Min Max Units 0.50 3.00 0.50 2.90 0.50 3.00 ns 0.45 1.80 0.45 1.80 0.45 1.80 ns 3 Conditions Figures 1, 2 www.fairchildsemi.com 100324 Commercial Version (Continued) SOIC and PLCC AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V TC = 0°C TC = +25°C Symbol Parameter Min Max Min Max tPLH Propagation Delay tPHL Data and Enable to Output tTLH Transition Time tTHL 20% to 80%, 80% to 20% tOSHL Maximum Skew Common Edge Output-to-Output Variation TC = +85°C Min Max Units 0.50 2.80 0.50 2.70 0.50 2.80 ns 0.45 1.70 0.45 1.70 0.45 1.70 ns Conditions Figures 1, 2 PLCC Only 0.95 0.95 0.95 ns (Note 4) 0.70 0.70 0.70 ns (Note 4) 1.60 1.60 1.60 ns (Note 4) 1.20 1.20 1.20 ns Data to Output Path tOSLH Maximum Skew Common Edge Output-to-Output Variation PLCC Only Data to Output Path tOST Maximum Skew Opposite Edge Output-to-Output Variation PLCC Only Data to Output Path tPS Maximum Skew Pin (Signal) Transition Variation PLCC Only (Note 4) Data to Output Path Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH), or in opposite directions both HL and LH (tOST). Parameters tOST and tPS guaranteed by design. www.fairchildsemi.com 4 100324 Industrial Version DC Electrical Characteristics (Note 5) VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = −40°C to +85°C, VTTL = +4.5V to +5.5V TC = −40°C TC = 0°C to +85°C Symbol Parameter Units Min Max Min Max VOH Output HIGH Voltage −1085 −870 −1025 −870 VOL Output LOW Voltage −1830 −1575 −1830 −1620 VOHC Output HIGH Voltage −1095 VOLC Output LOW Voltage VIH Input HIGH Voltage 2.0 5.0 2.0 5.0 V VIL Input LOW Voltage 0 0.8 0 0.8 V −1035 −1565 −1610 mV mV Conditions VIN =VIH (Max) Loading with or VIL (Min) 50Ω to −2.0V VIN = VIH(Min) Loading with or VIL (Max) 50Ω to −2.0V Guaranteed HIGH Signal for All Inputs Guaranteed LOW Signal for All Inputs VCD Input Clamp Diode Voltage IIH Input HIGH Current −1.2 VIN = +2.4V, 20 20 Enable 120 120 1.0 1.0 Breakdown Test, All Inputs IEE ITTL IIN = −18 mA V Data Input HIGH Current IIL −1.2 µA mA VIN = +5.5V, All Other Inputs = GND VIN = +0.4V, Input LOW Current Data −0.9 Enable −5.4 VEE Power Supply Current All Other Inputs VIN = GND −70 VTTL Power Supply Current −0.9 mA All Other Inputs VIN = VIH −22 mA All Inputs VIN = +4.0V 38 mA All Inputs VIN = GND −5.4 −22 −70 38 Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are chosen to guarantee operation under “worst case” conditions. AC Electrical Characteristics VEE = −4.2V to −5.7V, VCC = VCCA = GND, VTTL = +4.5V to +5.5V TC = −40°C TC = +25°C Symbol Parameter Min Max Min Max tPLH Propagation Delay tPHL Data and Enable to Output tTLH Transition Times tTHL 20% to 80%, 80% to 20% TC = +85°C Min Max Units Conditions 0.50 2.80 0.50 2.70 0.50 2.80 ns Figures 1, 2 0.35 1.80 0.45 1.70 0.45 1.70 ns Figures 1, 2 5 www.fairchildsemi.com 100324 Test Circuit Note: • VCC, VCCA = 0V, VEE = −4.5V, VTTL = +5.0V, VIH = +3.0V • L1, L2 and L3 = equal length 50Ω impedance lines • RT = 50Ω terminator internal to scope • Decoupling 0.1 µF from GND to VCC, VEE and VTTL • All unused outputs are loaded with 50Ω to −2V or with equivalent ECL terminator network • CL = Fixture and stray capacitance ≤ 3 pF FIGURE 1. AC Test Circuit Switching Waveform FIGURE 2. Propagation Delay and Transition Times www.fairchildsemi.com 6 100324 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Package Number N24E 7 www.fairchildsemi.com 100324 Low Power Hex TTL-to-ECL Translator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square Package Number V28A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8