TPD7102F TOSHIBA Intelligent Power Device Silicon Monolithic Power MOS Integrated Circuit TPD7102F 1 channel High-Side N channel Power MOSFET Gate Driver TPD7102F is a 1channel high-side N channel power MOSFET gate driver. This IC contains a charge pump circuit, allowing easy configuration of a high-side switch for large-current applications. Features z Charge pump circuit is built in z The diagnosis function of the voltage between OUT1 and SOURCE is built in z Housed in the PS-8 package and supplied in embossed carrier tape. SON8-P-0303-0.65 Weight: 0.017g (typ.) Pin Assignment (top view) DIAG 1 Marking 8 VDD ENB 2 7 OUT1 IN 3 6 OUT2 D7102 5 SOURCE GND 4 Part No. (or abbreviation code) Lot No. ・Note:● on the lower left of the marking indicates Pin 1 *Weekly code: (Three digits) (TOP VIEW） Week of manufacture (01 for first week of year, continuing up to 52 or 53) Year of manufacture (The last digit of the calendar year) Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. The RoHS is the Directive 2002/95/EC of the European Parliament and of the Council of 27 January 2003 on the restriction of the use of certain Note:That because of its MOS structure, this product is sensitive to static electricity. 1 2011-12-26 TPD7102F Block Diagram / Application circuit BATT VDD Regulator (VREG) Output voltage protection Constant Current Driver Charge pump 1mA → OUT2 VDD+10V 5kΩ 1MΩ Oscillation Circuit IN OUT1 SOURCE ENB Input Logic Load 5V OUT1-SOURCE voltage (VGS) monitor circuit DIAG COMP Diagnosis Logic AMP 1/7 Filter (2.2μs) GND 2 2011-12-26 TPD7102F Pin Description Pin No. Symbol Function 1 DIAG Diagnosis detection pin. N channel open drain. 2 ENB Enable pin. The ENB pin has a pull-down resistor. When VENB is L, OUT1 is Hz and OUT2 is L. 3 IN Input pin. The IN pin has a pull-down resistor. When VIN and VENB are H, OUT1 and OUT2 are H. 4 GND 5 SOURCE Ground pin. 6 OUT2 Output pin 2. 7 OUT1 Output pin 1. 8 VDD Source voltage of the external power MOSFET monitor pin. Power supply pin. Timing Chart VDD over voltage detection VDD Operating supply voltage VDD min H VENB L H VIN L Operating Charge pump Not operating VDD over voltage protection (Oscillation stop) H VOUT1 Hz(High impedance) VOUT2 L H H VGS (VOUT1-VSOURCE) VGS under voltage detection. L Hz(High impedance) VDIAG L Normal (Normality VGS) VGS under voltage detection Note: IN and ENB apply H, after VDD applied operating supply voltage. 3 2011-12-26 TPD7102F Truth Table IN signal ENB signal L L Charge pump circuit Oscillation stop VOUT1 VOUT2 Hz L Hz L Hz L H H L Hz L Hz Hz L Hz L H H Hz Hz VGS DIAG Hz H L L H H H L L H L L H H H L L Hz L H L Hz L L H Hz L H H H H L L L Hz L Hz H L Hz L L H Hz L H H H H Oscillation Oscillation stop Oscillation Oscillation stop Note: VGS=H(VGS>VGSUV) / VGS=L(VGS≤VGSUV) Mode VGS=H VGS=L VGS=H VGS=L Hz Hz Normal (VDD=7 to 18V) Hz Hz Hz Hz VDD over volatage (VDD>18V) Hz Hz Hz *VGS=VOUT1-VSOURCE Note: Hz: High impedance * DIAG is L only when VIN and VENB and VGS are H. 4 2011-12-26 TPD7102F Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit DC VDD(1) -0.3 to 25 V Pulse VDD(2) 35 V VIN -0.3 to 6 V Diagnosis output voltage VDIAG -0.3 to 25 V Diagnosis output current IDIAG 2 mA Output sink current(DC) IOUT2(+) 5 mA -VSOURCE -7 V Power dissipation (Note 1-a) PD(1) 0.7 W Power dissipation (Note 1-b) PD(2) 0.35 W Operating temperature Topr -40 to 125 °C Tj 150 °C Tstg -55 to 150 °C Power supply voltage Input voltage SOURCE pin negative voltage Junction temperature Strage temperature Remarks t=400ms single pulse Sink current t≤0.1μs, SOURCE pin 10kΩ connect Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Thermal Resistance Characteristic Symbol Thermal resistance, junction to ambient Rth (j–a) Rating 178.6(Note 1-a) 357.2(Note 1-b) Unit °C / W Note 1: (a)Glass epoxy board (b)Glass epoxy board Glass epoxy board Glass epoxy board Material: FR-4 25.4mm×25.4mm×0.8mm Material: FR-4 25.4mm×25.4mm×0.8mm 5 2011-12-26 TPD7102F Electrical Characteristics (Unless otherwise specified, Tj = -40 to 125°C, VDD = 7 to 18V) Characteristics Symbol Pin Test Condition Min Typ. Max Unit Operating supply voltage (Charge pump circuit, Input logic, Diagnosis logic operate) VDD(OPR) VDD - 7 12 18 V IDD(off) VDD VDD = 18V, VIN =VENB= 0V - 0.35 2 mA IDD(on) VDD VDD = 18V, VIN =VENB= 5V - 3 8 mA - 3.5 - - - - - 1.5 - 50 200 -1 - 1 VDD-2.7 VDD-1 VDD V VDD + 6.0 VDD +10 VDD +12.5 V - 70 180 Ω Supply current Input voltage VINH VINL IN, ENB IINH, IENBH IN, ENB Input current IINlL, IENBL VIN=VENB= 5V *Each pin current VIN=VENB= 0V *Each pin current V μA VDD = 9 to 18V, VIN=VENB=5V, VOUT1H OUT1 VSOURCE=VDD, OUT1-SOURCE 1MΩ Output voltage VDD = 9 to 18V, VIN=VENB=5V, VOUT2H OUT2 VSOURCE=VDD, OUT2-SOURCE 1MΩ OUT2 sink DMOS ON-Resistance RONOUT2L OUT2 VDD = 7 to 18V, VIN=VENB= 0V, IOUT2=1mA OUT1 high level output current IOH1 OUT1 VDD=9 to 18V, VIN=VENB=5V - -1.0 -0.15 mA OUT1 output leakage current IOL1 OUT1 VDD=9 to 18V, VIN=VENB=0V -1 - - μA IOUT1+ OUT1 VOUT1=12V,VIN=VENB=0V - 5 20 μA IOH2 OUT2 - -100 -30 μA Diagnosis output leakage current IDIAGH DIAG - - 10 μA Diagnosis output voltage VDIAGL DIAG - - 0.4 V VGS under voltage detection (OUT1-SOURCE voltage) VGSUV OUT1, SOURCE 3.3 4.1 4.8 V VDD over voltage detection VDDOV VDD 18 22 25 V - 16 100 - 2 10 OUT1 sink current OUT2 output current Switching time ton toff VDD=9 to 18V, VIN=VENB=5V, VOUT2=VDD+6V VDD = 7 to 18V, VIN=VENB=0V VDIAG = 5V VDD = 7 to 18V, VIN=VENB=5V IDIAG = 1mA VDD = 9 to 18V, VIN=VENB=5V - IN→OUT1 Refer to Test circuit 7 μs Note: Typical condition is VDD=12V, Tj=25°C. Note: Sink current to this IC is expressed by “+”, source current from this IC is expressed by “-”. 6 2011-12-26 TPD7102F Test circuit 1 Supply current IDD(off) IDD(off) DIAG VDD ENB OUT1 IN OUT2 GND SOURCE DIAG VDD ENB OUT1 IN OUT2 A 18V Test circuit 2 Supply current IDD(on) IDD(on) 5V GND SOURCE DIAG VDD ENB OUT1 IN OUT2 A 18V Test circuit 3 5V GND 1MΩ Output voltage VOUT1H V SOURCE 9 to 18V Test circuit 4 DIAG VDD ENB OUT1 IN OUT2 GND 1MΩ Output voltage VOUT2H SOURCE 5V V 9 to 18V Test circuit 5 OUT1 high level output current IOH1 5V DIAG VDD ENB OUT1 IN OUT2 GND IOH1 A SOURCE 9 to 18V 7 2011-12-26 TPD7102F Test circuit 6 1kΩ VGS under voltage detection DIAG VDD ENB OUT1 VGS =VOUT1-VSOURCE IN V GND OUT2 VGS under voltage detection VGS SOURCE 5V VDIAG 9 to 18V Test circuit 7 Switching time ton, toff tr≤0.1μs DIAG VDD ENB OUT1 IN OUT2 tf≤0.1μs 90% VIN P.G SOURCE 1MΩ GND 5V 100pF 5kΩ V 10% VDD+4V 9V VOUT1 1.5V ton 8 toff 2011-12-26 TPD7102F IDD - VDD IDD - Tj 5.0 5.0 VDD=18V Tj=25°C VENB=5V VENB=5V 4.0 Supply current IDD[mA] Supply current IDD[mA] 4.0 3.0 VIN=5V 2.0 VIN=5V 3.0 2.0 1.0 1.0 VIN=0V VIN=0V 0.0 0.0 0 4 8 12 16 -80 20 -40 0 40 80 Supply voltage VDD[V] Junction temperature Tj[°C] VIH,VIL - VDD VIH,VIL - Tj 3.0 VDD=12V IN input voltage VIH,VIL[V] Tj=25°C IN input voltage VIH,VIL[V] 160 4.0 4.0 VIH VIL 2.0 1.0 3.0 VIH VIL 2.0 1.0 0 4 8 12 16 -80 20 -40 0 40 80 120 Supply voltage VDD[V] Junction temperature Tj[°C] VINH,VINL - VDD VINH,VINL - Tj 160 4.0 4.0 3.0 VDD=12V ENB input voltage VINH,VINL[V] Tj=25°C ENB input voltage VINH,VINL[V] 120 VINH VINL 2.0 1.0 3.0 VINH VINL 2.0 1.0 0 4 8 12 16 -80 20 -40 0 40 80 120 160 Junction temperature Tj[°C] Supply voltage VDD[V] 9 2011-12-26 TPD7102F IIN - VIN IINH - Tj 100 100 Tj=25°C VIN=5V 80 Input current IINH[μA] Input current IIN[μA] 80 60 40 60 40 20 20 0 0 0 2 4 6 -80 8 -40 0 40 80 120 160 Junction temperature Tj[°C] Input voltage VIN[V] IENBH - Tj IENB - VENB 100 100 Tj=25°C VDD=12V VENB=5V Input current IENBH[μA] Input current IENB[μA] 80 60 40 80 60 40 20 20 0 0 0 2 4 6 -80 8 -40 0 40 120 160 VOUT1H - Tj VOUT1H - VDD 20 20 VDD=12V Tj=25°C VIN=VENB=5V VIN=VENB=5V 16 Output voltage VOUT1H[V] Output voltage VOUT1H[V] 80 Junction temperature Tj[°C] Input voltage VENB[V] 12 8 4 16 12 8 4 0 0 0 4 8 12 16 -80 20 -40 0 40 80 120 160 Junction temperature Tj[°C] Supply voltage VDD[V] 10 2011-12-26 TPD7102F ΔVOUT1H - VDD ΔVOUT1H - Tj 3.0 Tj=25°C VDD=12V VIN=VENB=5V VIN=VENB=5V Output drop voltage ΔVOUT1H (VDD-VOUT1H)[V] Output drop voltage ΔVOUT1H (VDD-VOUT1H)[V] 3.0 2.0 1.0 0.0 2.0 1.0 0.0 0 4 8 12 16 -80 20 -40 0 120 160 40 VDD=12V VIN=VENB=5V VIN=VENB=5V Output voltage VOUT2H[V] Tj=25°C 30 20 10 0 30 20 10 0 0 4 8 12 16 20 -80 -40 0 40 80 120 160 Junction temperature Tj[°C] Supply voltage VDD[V] ΔVOUT2H - Tj ΔVOUT2H - VDD 20 20 Tj=25°C VDD=12V VIN=VENB=5V Output drop voltage ΔVOUT2H (VDD-VOUT2H)[V] VIN=VENB=5V Output drop voltage ΔVOUT2H (VDD-VOUT2H)[V] 80 VOUT2H - Tj VOUT2H - VDD 40 Output voltage VOUT2H[V] 40 Junction temperature Tj[°C] Supply voltage VDD[V] 16 12 8 4 0 16 12 8 4 0 0 4 8 12 16 -80 20 -40 0 40 80 120 160 Junction temperature Tj[°C] Supply voltage VDD[V] 11 2011-12-26 TPD7102F ΔVOUT2 – - IOUT2 12 18V 12V Output boost voltage ΔVOUT2 (VOUT2-VDD)[V] 10 8V 8 9V VDD=7V 6 4 2 Tj=25°C VENB=VIN=5V 0 1 10 100 Output current - IOUT2[μA] RONOUT2L - VDD RONOUT2L - Tj 160 Tj=25°C VDD=12V VIN=VENB=0V VIN=VENB=5V OUT2 sink DMOS ON-resistance RONOUT2L[Ω] OUT2 sink DMOS ON-resistance RONOUT2L[Ω] 160 IOUT2=1mA 120 80 40 0 IOUT2=1mA 120 80 40 0 0 4 8 12 16 20 -80 -40 0 OUT1 high level output current IOH1[mA] OUT1 high level output current IOH1[mA] Tj=25°C VIN=VENB=5V -1.6 -1.2 -0.8 -0.4 0.0 4 8 12 80 120 160 IOH1 - Tj IOH1 - VDD -2.0 0 40 Junction temperature Tj[°C] Supply voltage VDD[V] 16 20 -2.0 VDD=12V VIN=VENB=5V -1.6 -1.2 -0.8 -0.4 0.0 -80 -40 0 40 80 120 160 Junction temperature Tj[°C] Supply voltage VDD[V] 12 2011-12-26 TPD7102F IOUT1+ - Tj 20 OUT1 sink current IOUT1+[μA] VDD=VOUT1=12V VIN=VENB=0V 16 12 8 4 0 -80 -40 0 40 80 120 160 Junction temperature Tj[°C] VDL - VDD VDL - Tj 0.5 0.5 VDD=12V IDIAG=1mA Diagnosis output voltage VDL[V] Diagnosis output voltage VDL[V] Tj=25°C 0.4 0.3 0.2 0.1 0.0 0.3 0.2 0.1 0.0 0 4 8 12 16 -80 20 -40 0 40 80 120 Supply voltage VDD[V] Junction temperature Tj[°C] VGSUV - VDD VGSUV - Tj 160 5.0 5.0 Tj=25°C VGS under voltage detection VGSUV[V] VGS under voltage detection VGSUV[V] IDIAG=1mA 0.4 4.6 4.2 3.8 3.4 3.0 VDD=12V 4.6 4.2 3.8 3.4 3.0 0 4 8 12 16 -80 20 -40 0 40 80 120 160 Junction temperature Tj[°C] Supply voltage VDD[V] 13 2011-12-26 TPD7102F PD - Ta VDDOV - Tj 1.00 (1)Mount on glass epoxy board (a) (Note 1-a) (2)Mount on glass epoxy board (b) (Note 1-b) 23 Power dissipation PD[W] VDD over voltage detection VDDOV[V] 25 21 19 17 15 0.80 (1) 0.60 0.40 (2) 0.20 0.00 -80 -40 0 40 80 120 160 -40 0 40 80 120 160 Ambient temperature Ta[°C] Junction temperature Tj[°C] 14 2011-12-26 TPD7102F Package Dimensions SON8-P-0303-0.65 Unit；mm 0.33±0.05 A 2.4±0.1 2.8±0.1 0.05 M 0.33±0.05 B 0.17±0.02 0.28 +0.1 A 0.025 S +0.1 0.28 -0.11 S 1.12 0.8±0.05 2.9±0.1 -0.11 0.05 M B 0.65 +0.13 1.12 +0.13 -0.12 -0.12 0.475 Weight：0.017g(Typ.) 15 2011-12-26 TPD7102F RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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