RFM TXC101

Complies with Directive 2002/95/EC (RoHS)
Product Overview
TXC101 is a highly integrated single chip, multi-channel, low power, high
data rate RF transmitter designed to operate in the unlicensed 315/433/868
and 915 MHz frequency bands. All critical RF and baseband functions are
completely integrated in the chip, thus minimizing external component
count and simplifying design-ins. Its small size with low power
consumption makes it ideal for various short range radio applications.
The TXC101 is a dual mode solution. In the Micro controller mode, a
generic 10MHz crystal and a low-cost microcontroller are the only
requirements to create a complete Transmitter link.
In the EEPROM mode, the TXC101 can function as a complete data
transmitter with any SPI compatible EEPROM and does not need a micro
controller. This makes it an ideal solution for a variety of simple short
range radio applications.
Key Features
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Modulation: OOK/FSK
Frequency Hopping Spread Spectrum capability
Operating frequency: 315/433/868/915 MHz
Low current consumption (TX current ~ 10mA)
Wide Operating supply voltage: 2.2 to 5.4V
Low standby current (0.2uA)
OOK Data rate up to 512kbps
FSK Data rate up to 256kbps
Support for Multiple Channels
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[315/433 Bands]: 380 Channels (25kHz)
[868 Band]: 761 Channels (25kHz)
[915 Band]: 1040 Channels (25kHz)
16-TSSOP package
Popular applications
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Remote control applications
Active RFID tags
Wireless PC Peripherals
Automated Meter reading
Home & Industrial Automation
Security systems
Remote keyless entry
Automobile Immobilizers
Sports & Performance monitoring
Wireless Toys
Medical equipment
Low power two way telemetry systems
Wireless mesh sensors
Wireless modules
Generic 10MHz Xtal reference
Processor or EEPROM Mode Operation
Integrated PLL, IF & Baseband Circuitry
Programmable Push Button Control
Programmable Output RF Power
Programmable, Positive/Negative FSK Deviation
Programmable Clock Output Frequency
Standard SPI interface
Integrated, Programmable Low Battery Voltage Detector
External Wake-up Events
TTL/CMOS Compatible I/O pins
Automatic Antenna tuning circuit
Very few external components requirement
No Manual Adjustment Needed for Production
Small size plastic package: 16-pin TSSOP
Standard 13 inch reel, 2000 pieces.
RF Monolithics, Inc.
4441 Sigma Road
Dallas, Texas 75244
rev01
(800) 704-6079 toll-free in U.S. and Canada
www.rfm.com
Email: [email protected]
1
Table of Contents
Table of Contents .......................................................................................................... 2
1.0 Pin Descriptions ...................................................................................................... 3
1.1 Processor Mode Pin Configuration .................................................................. 3
1.2 EEPROM Mode Pin Configuration .................................................................... 4
2.0 Functional Description ........................................................................................... 5
2.1 TXC101 Processor Mode Application .............................................................. 5
RF Transmitter Matching ..................................................................................... 5
Antenna Design Considerations........................................................................... 6
PCB Layout Considerations ................................................................................. 6
2.2 EEPROM Mode Application............................................................................... 8
3.0 TXC101 Functional Characteristics ..................................................................... 11
Output Amplifier ....................................................................................................... 11
Frequency Control (PLL) and Frequency Synthesizer ............................................. 11
Transmit Register..................................................................................................... 11
Crystal Oscillator...................................................................................................... 12
Wake-Up Mode ........................................................................................................ 12
Low Battery Detector ............................................................................................... 12
Key Switch Inputs .................................................................................................... 12
SPI Interface ............................................................................................................ 13
4.0 Control and Configuration Registers .................................................................. 14
Table of Control and Configuration Registers .......................................................... 14
Status Register ........................................................................................................ 15
Configuration Register [POR=8080h] ...................................................................... 16
Transmit Power Configuration Register [POR=B0h] ................................................ 18
Transmit Command Register ................................................................................... 19
Frequency Setting Register [POR=A7D0h].............................................................. 20
Data Rate Setup Register [POR=C800h]................................................................. 21
Button Command Register [POR=CA00h] ............................................................... 22
Sleep/Clock Command Register [POR=C400h]....................................................... 23
Wake-up Timer Period Register [POR=E000h]........................................................ 24
Battery Detect Threshold Register [POR=C200h].................................................... 25
Power Management Register [POR=C000h] ........................................................... 26
5.0 Maximum Ratings.................................................................................................. 27
Recommended Operating Ratings........................................................................... 27
6.0 DC Electrical Characteristics ............................................................................... 27
7.0 AC Electrical Characteristics ............................................................................... 28
8.0 Package Information ............................................................................................. 30
2
1.0 Pin Description
Processor Mode
Pin
1
2
Name
SDI
SCK
3
nCS
4
5
6
7
8
SW1
SW2
SW3
SW4
ClkOut
9
Xtal/Ref
10
11
12
13
14
15
16
GND
MODE
RF_P
RF_N
nIRQ
VDD
MOD
Description
SPI Data In
SPI Data Clock
Chip Select Input– Selects the chip for an SPI data transaction. The pin must be pulled
‘low’ for a 16-bit read or write function. See Figure 4 for timing specifications.
Switch or Push Button Input 1 with Internal pull-up resistor
Switch or Push Button Input 2 with Internal pull-up resistor
Switch or Push Button Input 3 with Internal pull-up resistor
Switch or Push Button Input 4 with Internal pull-up resistor
Optional host processor Clock Output
Xtal - Connects to a 10MHz series crystal or an external oscillator reference. The circuit
contains an integrated load capacitor (See Configuration Register) in order to minimize
the external component count. The crystal is used as the reference for the PLL, which
generates the local oscillator frequency. The accuracy requirements for production
tolerance, temperature drift and aging can be determined from the maximum allowable
local oscillator frequency error. Whenever a low frequency error is essential for the
application, it is possible to “pull” the crystal to the accurate frequency by changing the
load capacitor value.
Ext Ref – An external reference, such as an oscillator, may be connected as a reference
source. Connect through a .01uF capacitor.
System Ground
Mode Select – Connect to VDD for Processor Mode.
RF Diff I/O
RF Diff I/O
Interrupt Request – Interrupt Request Output and Status Register Data Read Output.
Supply Voltage
Modulation Input – Serial data input for FSK or OOK modulation
1.1 Processor Mode Pin Configuration
TOP VIEW
SDI
SCK
nCS
SW1
SW2
SW3
SW4
CLKOUT
1
2
16
3
4
14
13
5
15
TXC101
12
6
11
7
8
10
9
MOD
VDD
nIRQ
RF_N
RF_P
MODE
GND
Xtal/Ref
3
EEPROM Mode
Pin
1
2
Name
SDI
SCK
3
nCS
4
5
6
7
8
SW1
SW2
SW3
SW4
SDO
9
Xtal/Ref
10
11
12
13
GND
MODE
RF_P
RF_N
14
nBD
15
16
VDD
NC
Description
SPI Data In
SPI Data Clock
Chip Select Input - Selects the chip for an SPI data transaction. The pin must be pulled
‘low’ for a 16-bit read or write function. See Figure 4 for timing specifications.
Switch or Push Button Input 1 with Internal pull-up resistor
Switch or Push Button Input 2 with Internal pull-up resistor
Switch or Push Button Input 3 with Internal pull-up resistor
Switch or Push Button Input 4 with Internal pull-up resistor
SPI Data Out
Xtal - Connects to a 10MHz series crystal or an external oscillator reference. The circuit
contains an integrated load capacitor (See Configuration Register) in order to minimize
the external component count. The crystal is used as the reference for the PLL, which
generates the local oscillator frequency. The accuracy requirements for production
tolerance, temperature drift and aging can be determined from the maximum allowable
local oscillator frequency error. Whenever a low frequency error is essential for the
application, it is possible to “pull” the crystal to the accurate frequency by changing the
load capacitor value.
Ext Ref – An external reference, such as an oscillator, may be connected as a reference
source. Connect through a .01uF capacitor.
System Ground
Mode Select – Connect to GND for EEPROM Mode.
RF Diff I/O
RF Diff I/O
Low Battery Detect – When the battery voltage falls below the programmed level this
output goes “low”. The voltage level is programmable through the Battery Detect
Threshold Register.
Supply Voltage
Not used. Tie to VDD or GND
1.2 EEPROM Mode Pin Configuration
TOP VIEW
SDI
SCK
nCS
SW1
SW2
SW3
SW4
SDO
1
2
16
3
4
14
5
15
TXC101
13
12
6
11
7
8
10
9
NC
VDD
nBD
RF_N
RF_P
MODE
GND
Xtal/Ref
4
2.0 Functional Description
The TXC101 is a low power, frequency agile, multi-channel OOK/FSK transmitter for use in the 315, 433,
868, and 916 MHz bands. All RF transmit functions are completely integrated requiring only a single
10MHz crystal as a reference source. The TXC101 has two modes of operation: EEPROM mode and
Processor mode. EEPROM mode is fully compatible with any standard SPI interface EEPROM.
Functions include:
• PLL synthesizer
• Power Amp
• Crystal oscillator
• Sleep Timer
• OOK/FSK Modulation
• 4 Key/Switch Functions
The TXC101 is ideal for Frequency Hopping Spread Spectrum (FHSS) applications requiring frequency
agility to meet FCC and ETSI requirements. Use of a low-cost microcontroller or SPI compatible
EEPROM is all that is needed to create a complete transmitter. The TXC101 also incorporates different
sleep modes to reduce overall current consumption and extend transmitter battery life. It is ideal for
applications operating from typical lithium coin cells.
2.1 TXC101 Processor Mode and Application Circuit
Figure 1. Typical Processor Mode Application Circuit for 50 Ohm Load
The TXC101 may be used with a typical low-cost microcontroller. All internal functions are accessible
through the SPI interface. Figure 1 shows a typical connection for using a microcontroller to control the
TXC101 functions.
RF Transmitter Matching
The RF pins are high impedance and differential. The optimum differential load for the RF port at a given
frequency band is shown in Table 1.
TABLE 1.
Admittance [S] Impedance [Ohm] Lantenna (nH)
9.4e-4 – j4.5e-3
43 + j214
112
315 MHz
21 + j157
59
433 MHz 8.4e-4 – j6.25e-3
7.9 + j83
15.3
868 MHz 1.15e-3 – j1.2e-2
7.6 + j79
13.9
916 MHz 1.2e-3 – j1.25e-2
5
These values are what the RF port pins want to “see” as an antenna load for maximum power transfer.
Antennas ideally suited for this would be a Dipole, Folded Dipole, and Loop. For all transmit antenna
applications a bias or “choke” inductor must be included since the RF outputs are open-collector type.
The TXC101 may also drive a single ended 50 Ohm load, such as a monopole antenna, using the
matching circuit as shown in Figure 1. Use of a balun would provide an optimum power transfer, but the
matching circuit of Figure 1 has been optimized for use with discrete components, reducing the cost
associated with use of a balun.
The matching component values for a 50 Ohm load are given in Table 2.
Ref Des
C1
C2
L1
L2
L3
Table 2.
315
433
3.9pF 2.7 pF
2.2 pF 1.5 pF
72 nH 43 nH
390nH 390nH
110 nH 82 nH
868
1.8 pF
1 pF
10 nH
100nH
27 nH
916
1.8 pF
1 pF
10 nH
100nH
27 nH
Antenna Design Considerations
The TXC101 was designed to drive a differential output such as a Dipole or a Loop antenna. A loop
antenna is recommended for applications where size is critical. The dipole is typically not an attractive
option for compact designs based on its inherent size at resonance and distance needed away from a
ground plane to be an efficient radiating antenna. A monopole is possible with addition of a balun or
using the matching circuit in Figure 1.
PCB Layout Considerations
PCB layout is very critical. For optimal transmit and receive performance, the trace lengths at the RF pins
must be kept as short as possible. Using small, surface mount components, like 0402, will yield the best
performance and also keep the RF port compact. It is recommended that all RF connections are made
short and direct. A good rule of thumb to adhere to is to add 1nH of series inductance to the path for
every 0.1” of trace length. The crystal oscillator is also affected by additional trace length as it adds
parasitic capacitance to the overall load of the crystal. To minimize this effect the crystal must be placed
as close as possible to the chip and all connections must be made short and direct. This will minimize the
effects of “frequency pulling” , that stray capacitance may introduce and allow the internal load
capacitance of the chip to be more effective in properly loading the crystal oscillator circuit.
When an external processor is used, the TXC101 provides an on-chip clock. Even though this is an
integrated function, long runs of the clock signal may radiate and cause interference. This can degrade
receiver performance as well as add harmonics or unwanted modulation to the transmitter. Keep clock
connections as short as possible and surround the clock trace with an adjacent ground plane pour where
needed. This will help in reducing any radiation or crosstalk due to long runs of the clock signal.
Good power supply bypassing is also essential. Large decoupling capacitors should be placed at the
point where power is applied to the PCB. Smaller value decoupling capacitors should then be placed at
each power point of the chip as well as bias nodes for the RF port. Poor bypassing lends itself to
conducted interference which can cause noise and spurious signals to couple into the RF sections, thus
significantly reducing performance.
6
Top
Bottom
Top Assembly
7
2.2 EEPROM Mode
Figure 2. Typical EEPROM Mode Application Circuit for 50 Ohm Load
The TXC101 can operate from a single, SPI compatible EEPROM by simply reading the sequential
codes stored in memory. No external microcontroller is required. The codes are read out and processed
as command and data. In this special mode, four pins are configured as inputs with an internal pull-up
resistor. All that is needed are external key switches connected to GND to activate that key’s code
routine. When the key is pressed, the chip automatically begins executing code from a designated point
within the EEPROM. When not in use, the last command of the code execution should be a sleep
command so as to power down the device for maximum battery life. When the device is put into sleep
one of the following seven (7) events can cause the device to wake up:
• Power-on Reset
• Low pulse on Key 1
• Low pulse on Key 2
• Low pulse on Key 3
• Low pulse on Key 4
• Low supply voltage output warning
• Wake-up timer timeout
For each wake-up event there is an internal address assigned as the starting point in EEPROM memory
to begin executing code. These are defined in TABLE 3 as follows:
TABLE 3.
Wake-up Event
Power up
Low Pulse on SW1
Low Pulse on SW2
Low Pulse on SW3
Low Pulse on SW4
LBD Warning
Wake-up Timer Timeout
EEPROM Address Entry
0000h
0080h
0100h
0180h
0200h
0280h
0300h
8
Another feature allows the use of two keys being pressed at the same time. For this, Bit7 in the Button
Command Register controls whether SW4 is used as a single key press or SW1 and SW2 are used as
simultaneous key presses. By setting Bit7 of the Button Command Register, the EEPROM Address
Entry point of SW4 is used for simultaneous presses of SW1 and SW2. Clearing Bit7 sets the EEPROM
to use SW4 as a single key press. It is also possible to detect multiple key presses and execute
sequential routines. When multiple keys are pressed, all routines associated with the keys are executed
in the same sequence of which the keys were pressed.
When a key is pressed, the chip looks to see if there is a debounce time to recognize before sampling the
pin again. At this time the oscillator is turned on, independent of the state of Bit 5 of the Power
Management Register, because it uses the crystal oscillator signal as a timing reference. After the
debounce time has expired, it begins execution of the code from the EEPROM address entry point.
All sources used to transmit are internal when using EEPROM mode. All external pin functions, such as
external FSK modulation, are disabled and the internal functions are used. During sleep mode, all
internal configurations are maintained as long as power is not interrupted. If there is a supply interruption
the chip reboots from the Power-up EEPROM Address Entry point and all configurations are re-written.
Example EEPROM Hex Code Contents:
Power-On Reset:
00000000
00000010
00000020
00000030
00000040
00000050
00000060
00000070
C0
00
00
00
00
00
00
00
C4
00
00
00
00
00
00
00
CA
00
00
00
00
00
00
00
1E
00
00
00
00
00
00
00
C8
00
00
00
00
00
00
00
23
00
00
00
00
00
00
00
C4
00
00
00
00
00
00
00
64
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
The example above configures the initial settings of the registers at power-up. Other parameters may be
changed as needed when the chip recognizes a key press. The code ends in a sleep command C400h
where 00h is the number of clocks to output before disabling the clock output pin. See Sleep/Clock
Command Register.
Address
Command
Data
Related Register
00–01
C0
C4
02–03
CA
00
Button Command
Single execution for all keys
04–05
C8
8F
Data Rate
BR=10M/29/(143+1)~2400 bps
06-07
C4
64
Sleep
Power down after 100 clocks
Power Management
Description
Crystal– Synthesizer – Power Amplifier auto on/off mode enable
Example Code for Key Press 3:
00000180
00000190
000001A0
000001B0
000001C0
000001D0
000001E0
000001F0
88
AA
AA
AA
AA
AA
AA
00
72
AA
AA
AA
AA
AA
AA
00
A6
AA
AA
AA
AA
AA
AA
00
10
AA
AA
AA
AA
AA
AA
00
C6
AA
AA
AA
AA
AA
AA
00
60
AA
AA
AA
AA
AA
AA
00
AA
AA
AA
AA
AA
AA
C4
00
AA
AA
AA
AA
AA
AA
64
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
AA
AA
AA
AA
AA
AA
00
00
9
In the above example, some commands are one nibble long. For purposes of writing to the EEPROM the
data must be arranged in bytes. The chip automatically distinguishes between command and data. On
power-up, the keys are configured as a single execution. Hence, after this routine is executed, the chip
returns to sleep and wakes up on another key press. If the keys were configured as a continuous
execution, at the end of the sleep command, the chip restarts at address 0180h and re-executes the
routine until the key is released.
Address
180–181
182–183
184–185
186–1B7
1B8–1B9
Command
8
A
C6
C4
Data
872
610
32
50xAA
64
Related Register
Configuration Control
Frequency
Data Transmit
Sleep
Remarks
433MHz band, FSK dev=90kHz, Crystal CL=12pF
fc=(43+1552/4000)*10MHz
Transmit the next 50 bytes
Data
Power down after 100 clocks
10
3.0 TXC101 Functional Characteristics
CONTROL
SDI
SCK
nCS
LOGIC
RF_P
RF_N
nIRQ/nBD
SW1
PA
VCO
PLL
OSC
SW2
SW3
SW4
BATT DET
/N
MODE
Wake-up
CLKOUT/SDO
XTAL/REF
VDD GND
MOD
Figure 3. Functional Block Diagram
Output Power Amplifier
The power amplifier is an open-collector, differential output with programmable output power which can
directly drive a loop or dipole antenna, and with proper matching may also drive a monopole antenna.
Incorporated in the power amplifier is an automatic antenna tuning circuit to avoid manual tuning during
production and to offset “hand effects”. Registers common to the Power Amplifier are:
• Power Management Register
• Transmit Power Configuration Register
Phase Lock Loop (PLL)
The PLL synthesizer is the heart of the operating frequency. It is programmable and completely
integrated, providing all functions required to generate the carriers and tunability for each band. The PLL
requires only a single 10MHz crystal reference source. RF stability is controlled by choosing a crystal
with the particular specifications to satisfy the application.
The PLL is able to perform manual and automatic calibration to compensate for changes in temperature
or operating voltage. When changing band frequencies, re-calibration must be performed. This can be
done by disabling the synthesizer and re-enabling again through the Power Management Register.
Registers common to the PLL are:
• Power Management Register
• Configuration Register
• Frequency Setting Register
• Automatic Frequency Adjust Register
• Transmit Configuration Register
Transmit Register
The transmit register is configured as two 8-bit shift registers connected in series to form a single 16-bit
shift register. On POR the registers are filled with the value AAh. This can be used to generate a
preamble before sending actual data. When the transmitter is enabled through the Power Management
Register, transmission begins immediately and the value in the transmit register begins to be sent out. If
there is nothing written to the register, it will send out the default value of AAh. The next data byte can be
loaded via the SPI bus to the Transmit Register by monitoring the SDO pin for a logic ‘1’ or waiting for an
active low interrupt output from the nIRQ pin. After data has been loaded to the Transmit Register, the
11
processor must wait for the next interrupt before disabling the transmitter – otherwise, the rest of the data
left in the register will be lost. Inserting a dummy byte of all 0’s is recommended for the last byte of data
loaded.
Crystal Oscillator
The TXC101 incorporates an internal crystal oscillator circuit that provides a 10MHz reference, as well as
internal load capacitors. This significantly reduces the component count required. The internal load
capacitance is programmable from 8.5pF to 16pF in 0.5pF steps. This has the advantage of accepting a
wide range of crystals from many different manufacturers having different load capacitance requirements.
Since the crystal is the PLL reference for the carrier, being able to vary the load capacitance also helps
with fine tuning the final carrier frequency
An external clock signal is also provided that may be used to run an external processor. This also has
the advantage of reducing component count by eliminating an additional crystal for the host processor.
The clock frequency is also programmable from eight pre-defined frequencies, each a pre-scaled value of
the 10MHz crystal reference. These values are programmable through the Battery Detect Threshold and
Clock Output Register. The internal clock oscillator may be disabled, thus also disabling the output clock
signal to the host processor. When the oscillator is disabled, the chip provides an additional 196 clock
cycles before releasing the output, which may be used by the host processor to setup any functions
before going to sleep.
Wake-Up Mode
The TXC101 has an internal wake-up timer that has very low current consumption (1.5uA typical) and
may be programmed from 1msec to several days. A calibration is performed to the crystal at startup and
every 30 sec thereafter, even if in sleep mode. If the oscillator circuit is disabled the calibration circuit will
turn it on briefly to perform a calibration to maintain accurate timing and return to sleep.
The TXC101 also incorporates other power saving modes aside from the wake-up timer. Return to active
mode may be initiated from several external events:
• Logic ‘0’ applied to nINT pin (16)
• Low Supply Voltage Detect
• FIFO Fill
• SPI request
If any of these wake-up events occur, including the wake-up timer, the TXC101 generates an external
interrupt which may be used as a wake-up signal to a host processor. The source of the interrupt may be
read out from the Status Register over the SPI bus.
Low Battery Detect
The integrated low battery detector monitors the voltage supply against a preprogrammed value and
generates an interrupt when the supply voltage falls below the programmed value. The detector circuit
has 50mV of hysteresis built in.
Key Switch Inputs
In microcontroller mode, the TXC101 generates an interrupt on the nIRQ pin when a key is pressed. The
source of the interrupt may be determined by reading the Status Register. In EEPROM mode, each
switch has an internal address assigned to it. It uses this address as the entry point to the EEPROM and
executes commands after that address until it sees a sleep command (C400h). The chip has internal
weak pull-up resistors so there is no need for additional components. These weak pull-ups may be
disabled through the Button Command Register. For each mode the chip repeats this function while the
key is pressed if configured by the Button Command Register. In the microcontroller mode, the chip
continuously generates interrupts until the key is released. In the EEPROM mode, the chip continuously
enters the EEPROM at the assigned address and executes the commands following the entry point as
long as the key is active, if enabled through the Button Command Register. There are seven defined
entry points for the EEPROM mode. The chip also has an integrated, programmable de-bounce circuit
for each key. See Button Command Register for a detailed explanation.
12
SPI Interface
The TXC101 is equipped with a standard SPI bus that is compatible to almost all SPI devices. All
functions and status of the chip are accessible through the SPI bus. Typical SPI devices are configured
for byte write operations. The TXC101 uses word writes and hence the nCS (Pin 3) should be pulled low
for 16 bits. All SPI data is written to the TXC101 MSB first.
TABLE 4.
Figure 4. Timing Diagram
13
4.0 Control and Configuration Registers
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
POR
Value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
STATUS
X
X
X
X
X
X
X
X
1
1
0
0
1
1
0
0
--
CONFIG
1
0
0
CAP1
CAP0
MODP
DEV2
DEV1
DEV0
8080h
TX POWER
CONFIG
TX COMMAND
X
X
X
X
X
X
X
X
1
0
1
1
OOKEN PWR2
PWR1
PWR0
XXB0h
1
1
0
0
0
1
1
0
B7
B6
B5
B4
B3
B2
B1
B0
--
FREQ SET
1
0
1
0
Freq5
Freq4
Freq3
Freq2
Freq1
Freq0
A7DOh
DATA RATE
SET
BUTTON CMD
1
1
0
0
1
0
0
0
BITR7 BITR6 BITR5
BITR4
BITR3
BITR2
BITR1
BITR0
C800h
1
1
0
0
1
0
1
0
2KPEN DB1
DB0
SW4
SW3
SW2
SW1
SLEEP/CLK
CMD
WAKE-UP
PERIOD
BATT DETECT
1
1
0
0
0
1
0
0
SLP6
SLP5
SLP4
SLP3
SLP2
SLP1
SLP0
C400h
1
1
1
R4
R3
R2
R1
R0
MUL7 MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
E000h
1
1
0
0
0
0
1
0
0
0
0
LBD4
LBD3
LBD2
LBD1
LBD0
C200h
POWER
MANAGEMENT
1
1
0
0
0
0
0
0
TX1
TX0
BAND1 BAND0 CLK2 CLK1 CLK0 CAP3 CAP2
Freq11 Freq10 Freq9 Freq8 Freq7 Freq6
SLP7
PUPDIS CA00h
OSCEN SYNEN PAEN LBDEN WKUPEN CLKEN C000h
Table 5. Control and Configuration Registers Table
14
Status Register (Read Only)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
1
1
0
0
1
1
0
0
The Status Register provides feedback for:
•
POR
•
Interrupt Request state
•
Low Battery
•
Push Button event
The Status Register requires only the Command Code to be sent. Status bits can be read through the nIRQ pin (14). Clock pulses
are continually sent and data is read out. When this command is issued it clears the last interrupt and starts processing the next
pending interrupt. See Figure 5 for read sequence.
nCS
Figure 5. Status Register Read Through nIRQ (pin 14 Processor Mode)
Bit [7..0]: Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Status Register.
15
Configuration Register [POR=8080h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
0
BAND1
BAND0
CLK2
CLK1
CLK0
CAP3
CAP2
CAP1
CAP0
MODP
DEV2
DEV1
DEV0
The configuration register sets up the following:
•
Frequency Band in use
•
Crystal Load capacitance
•
TX Modulation Polarity
•
TX Modulation Bandwidth
Bit [15..13] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the configuration register.
Bit [12..11] – Band Select: These bits set the frequency band to be used. There are four (4) bands that are supported. See Table
6 for Band configuration.
TABLE 6.
Frequency Band
BAND1
BAND0
315
433
868
916
0
0
1
1
0
1
0
1
Bit [10..8] – Clock Output Frequency: These bits set the output frequency of the on-board clock that may be used to run an
external host processor. See Table 7.
TABLE 7.
Output Clock
Frequency (MHz)
1
1.25
1.66
2
2.5
3.33
5
10
CLK2
CLK1
CLK0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bit [7..4] – Load Capacitance Select: These bits set the load capacitance for the crystal reference. The internal load capacitance
can be varied from 8.5pF to 16pF in 0.5pF steps to accommodate a wide range of crystal vendors and also to adjust the
reference frequency and compensate for stray capacitance that may be introduced due to PCB layout. See Table 8 for
load capacitance configuration.
TABLE 8.
CAP3
0
0
0
0
1
1
CAP2
0
0
0
0
……
1
1
CAP1
0
0
1
1
CAP0
0
1
0
1
1
1
0
1
Crystal Load Capacitance
8.5
9
9.5
10
……
15.5
16
Bit [3] - Modulation Polarity: When clear, a logic ‘0’ is defined as the lower channel frequency and a logic ‘1’ as the higher channel
frequency (positive deviation). When set, a logic ‘0’ is defined as the higher channel frequency and a logic ‘1’ as the lower
channel frequency (negative deviation).
16
Configuration Register – continued
Bit [2..0] - Modulation Bandwidth: These bits set the FSK frequency deviation for transmitting a logic ‘1’ and logic ‘0’. The
deviation is programmable from 15kHz to 240kHz in 15kHz steps. See Table 9 for deviation settings.
TABLE 9.
Modulation Bandwidth
15 kHz
30 kHz
45 kHz
60 kHz
75 kHz
90 kHz
105 kHz
DEV3
DEV2
DEV1
DEV0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
……………..
………….
………….
………….
………….
210 kHz
225 kHz
240 kHz
1
1
1
1
1
1
0
1
1
1
0
1
17
Transmit Power Configuration Register [POR=B0h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
1
0
1
1
OOKEN
PWR2
PWR1
PWR0
The Power Configuration Register configures the output transmit power desired.
Bit [7..4] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Transmit Power Configuration Register.
Bit [3] – OOKEN: This bit enables OOK mode for the power amplifier. In this mode, data is applied to the MOD pin (16). When a
logic ‘1’ is applied, the power amplifier is On. When a logic ‘0’ is applied, the power amplifier is Off.
Bit [2..0] – Output Transmit Power: These bits set the transmit output power. The output power is programmable from Max to
-21dB in -3dB steps. See Table 10 for Output Power settings.
TABLE 10.
Output Power (Relative)
Max
-3dB
-6dB
-9dB
-12dB
-15dB
-18dB
-21dB
PWR2
PWR1
PWR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
18
Transmit Command Register [POR=C600h]
(EEPROM Mode)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
1
1
0
B7
B6
B5
B4
B3
B2
B1
B0
(Processor Mode)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
1
1
0
0
0
1
1
0
The Transmit Command Register in EEPROM mode holds the count of the number of data bytes to follow. In processor mode, only
the command code is sent and the data is applied to the SDI pin WITHOUT a clock. If clock pulses are sent, the data will be
interpreted as command data. In this mode the SDI pin acts like the MOD input pin (16). See Figure 6.
nCS
SCK
SDI
Tsx is the oscillator startup time
Tsp is the synthesizer start-up and lock time
Figure 6. Data Transmit through SDI pin
The MOD pin(16) may also be used to manually send modulated data. The Oscillator and Synthesizer must manually be enabled
through the Power Management Register. Startup and settle time must be allowed before applying a modulating signal to the MOD
pin(16).
Bit [15..8] - Command Code (EEPROM Mode Only): These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Transmit Command Register.
Bit [7..0] – Byte Count (EEPROM Mode Only): These bits are the 8-bit value of the number of data bytes to be transmitted. Before
issuing this command the power amplifier must be enabled either by setting the respective Power Management Register
bits PAEN bit (3) or TX0 bit (6).
Bit [7..0] - Command Code (Processor Mode Only): These bits are the command code that is sent serially to the processor that
identifies the bits to be written to the Transmit Command Register.
Note: When manually controlling the oscillator and synthesizer turn-on, valid data can only be transmitted when the oscillator has
had time to start-up and the synthesizer has had time to lock.
19
Frequency Setting Register [POR=A7D0h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
Freq11
Freq10
Freq9
Freq8
Freq7
Freq6
Freq5
Freq4
Freq3
Freq2
Freq1
Freq0
The Frequency Setting Register sets the exact frequency within the selected band for transmit or receive. Each band has a range of
frequencies available for channelization or frequency hopping. The selectable frequencies for each band are:
Frequency Band
300 MHz
400 MHz
800 MHz
900 MHz
Min (MHz)
310.24
430.24
860.48
900.72
Max (MHz)
319.75
439.75
879.51
929.27
Tuning Resolution
2.5 kHz
2.5 kHz
5.0 kHz
7.5 kHz
Bit descriptions are as follows:
Bit [15..12] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Frequency Setting Register.
Bit [11..0] – Frequency Setting: These bits set the center frequency to be used during transmit or receive. The value of bits[11..0]
must be in the decimal range of 96 to 3903. Any value outside of this range will cause the previous value to be kept
and no frequency change will occur. To calculate the center frequency fc, use Table 11 and the following equation:
fc = 10 * B1 * (B0 + fVAL/4000) MHz
where fVAL = decimal value of Freq[11..0] = 96<fVAL<3903.
Use Table 11 to select the frequency band and substitute into the above equation to calculate the center frequency of the desired
band.
TABLE 11.
Range
315 MHz
433 MHz
868 MHz
916 MHz
B1
1
1
2
3
B0
31
43
43
30
20
Data Rate Setup Register [POR=C800h]
[EEPROM Mode ONLY]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
1
0
0
0
BITR7
BITR6
BITR5
BITR4
BITR3
BITR2
BITR1
BITR0
The Data Rate Setup Register configures the effective transmit data rate for the transmitter.
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Data Rate Setup Register.
Bit [7..0] – Data Rate Parameter Value: These bits represent the decimal value of the 7-bit parameter used to calculate the
expected data rate. The definable data rates range from 1.346kpbs to 344.828kbps. To calculate the expected data
rate, use the following formula:
DRexp(kbps) = 10000 / [29 * (BITR[6..0]+1)]
where BITR[6..0] is the decimal value 0 to 255.
To calculate the BITR[6..0] decimal value for a given bit rate, use the following formula:
BITR[6..0] = (10000 / [29 * DRexp]) - 1
where DRexp is the expected data rate.
TABLE 12. Conversion for Common Data Rates
Hex Value
0x8E
0x47
0x23
0x19
0x17
0x11
0x0B
0x02
Common Data Rate (bps)
2400
4800
9600
13200
14400
19200
28800
115200
21
Button Command Register [POR=CA00h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
1
0
1
0
2KPEN
DB1
DB0
SW4
SW3
SW2
SW1
PUPDIS
The Button Command Register configures:
•
Key press de-bounce time
•
Key press events
•
Weak Pull-ups
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Button Command Register.
Bit [7] – 2-Key Press Enable: This bit enables simultaneous key press of SW1 and SW2 to execute the same address entry point
as SW4. Enabling this bit does NOT disable SW4 function.
Bit [6..5] – De-Bounce Time Set: These bits set the key press de-bounce time. See Table 13 for settings.
TABLE 13.
DB1
0
0
1
1
DB0
0
1
0
1
De-Bounce Time
160msec
40msec
10msec
NONE
Bit [4] – SW4 Continuous Execute Enable: This bit, when set, enables the chip to continuously execute the routine as long as the
key is pressed.
Bit [3] – SW3 Continuous Execute Enable: This bit, when set, enables the chip to continuously execute the routine as long as the
key is pressed.
Bit [2] – SW2 Continuous Execute Enable: This bit, when set, enables the chip to continuously execute the routine as long as the
key is pressed.
Bit [1] – SW1 Continuous Execute Enable: This bit, when set, enables the chip to continuously execute the routine as long as the
key is pressed.
Bit [0] – Weak Internal Pull-ups: This bit DISABLES the internal weak pull-up resistors for all keys when set. This bit defaults to
clear so that the weak pull-ups are enabled.
22
Sleep/Clock Command Register [POR=C400h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
1
0
0
SLP7
SLP6
SLP5
SLP4
SLP3
SLP2
SLP1
SLP0
The Sleep Command Register defines the byte command and the number of clock cycles to generate after a sleep instruction to put
the chip into sleep mode. When the chip sees this command issued, it immediately disables the power amplifier, turns off the
synthesizer, and turns off the oscillator after SLP[7..0] clock cycles.
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Sleep Command Register.
Bit [7..0] – Sleep Command Value: These bits define the sleep command value that is issued by a host controller instructing the
chip to go into sleep mode. This also sets the number of clock cycles that are generated after the oscillator has been
disabled and before the chip goes into sleep mode.
23
Wake-up Timer Period Register [POR=E000h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
R4
R3
R2
R1
R0
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
MUL0
The Wake-up Timer Period register sets the wake-up interval for the TXC101. After setting the wake-up interval, the WKUPEN (bit
1 of Power Management Register) should be cleared and set at the end of every wake-up cycle. To calculate the wake-up interval
desired, use the following:
TWAKE = MUL[7..0] * 2 R[4..0]
where MUL[7..0] = decimal value 0 to 255 and R[4..0] = decimal value 0 to 31.
Bit [15..13] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Wake-up Timer Period register.
Bit [12..8] – Exponential: These bits define the exponential value as used in the above equation. The value used must be the
decimal equivalent between 0 and 31.
Bit [7..0] – Multiplier: These bits define the multiplier value as used in the above equation. The value used must be the decimal
equivalent between 0 and 255.
24
Battery Detect Threshold Register [POR=C200h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
1
0
0
0
0
LBD4
LBD3
LBD2
LBD1
LBD0
The Battery Detect Threshold and Clock Output Register configures the following:
•
Low Battery Detect Threshold
The Low Battery Threshold is programmable from 2.2V to 5.3V using the following equation:
VT = (LBD[4..0] / 10) + 2.2 (V)
where LBD[4..0] is the decimal value 0 to 31.
Bit [15..8] - Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Battery Detect Threshold Register.
Bit [7..5] – Not Used. Write a logic ‘0’.
Bit [4..0] – Low Battery Detect Value: These bits set the decimal value as used in the equation above to calculate the battery
detect threshold voltage value. When the battery level falls 50mV below this value, the LBD bit (5) in the status register is
set indicating that the battery level is below the programmed threshold. This is useful in monitoring discharge sensitive
batteries such as Lithium cells.
The Low Battery Detect can be enabled by setting the LBDEN bit (2) of the Power Management Register and disabled by clearing
the bit.
25
Power Management Register [POR=C000h]
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
TX1
TX0
OSCEN
SYNEN
PAEN
LBDEN
WKUPEN
CLKEN
The Power Management Register enables/disables the following:
•
Transmit Chain
•
PLL
•
Power Amplifier
•
Synthesizer
•
Crystal Oscillator
•
Low battery Detect Circuit
•
Wake-up Timer
•
Clock Output
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
written to the Power Management register.
Bit [7..6] – Transmit Chain Automatic Enable: These bits enable the entire transmit chain when set. When TX1 is set, the
oscillator and synthesizer turn-on are controlled by the chip. When the Data Transmit Command is issued, the oscillator
is enabled. As soon as a stable frequency is reached the synthesizer is enabled. When TX0 is set, this turns on the
power amplifier after the PLL has successfully achieved lock.
Bit [5] – Crystal Oscillator Enable: This bit enables the oscillator circuit when set. The oscillator provides the reference signal for
the synthesizer when setting the transmit frequency of use.
Bit [4] – Synthesizer Enable: This bit enables the synthesizer when set. The synthesizer contains the PLL, oscillator, and VCO for
controlling the channel frequency. This must be enabled when the transmitter is enabled. The oscillator also must be
enabled to provide the reference frequency for the PLL. On power-up the synthesizer performs a calibration automatically.
If there are significant changes in voltage or temperature, recalibration can be performed by simply disabling the synthesizer
and re-enabling it.
Bit [3] –Power Amplifier Enable: This bit enables the power amplifier when set. The power amplifier may be manually enabled
from other functions.
Bit [2] – Low Battery Detector: This bit enables the battery voltage detect circuit when set. The battery detector can be
programmed to 32 different threshold levels. See Battery Detect Threshold and Clock Output Register section for
programming.
Bit [1] – Wake-up Timer Enable: This bit enables the wake-up timer when set. See Wake-up Timer Period Register section for
programming the wake-up timer interval value.
Bit [0] – Clock Output Disable: This bit disables the oscillator clock output when set. On chip reset or power up, clock output is on
so that a processor may begin execution of any special setup sequences as required by the designer. See Battery Detect
Threshold and Clock Output Register section for programming details.
26
5.0 Maximum Ratings
Absolute Maximum Ratings
Symbol
VDD
Vin
Voc
Parameter
Min
Max
Positive supply voltage
Notes
-0.5
6
V
Voltage on any pin (except RF_P and RF_N)
-0.5
Vdd+0.5
V
-0.5
6
25
mA
Voltage on open collector outputs (RF1, RF2)
Iin
Input current into any pin except VDD and VSS
ESD
Electrostatic discharge with human body model
Tstg
Storage temperature
Tlead
Lead temperature (soldering, max 10 s)
1
-25
Units
V
1000
-55
125
V
°C
260
°C
Note 1: At maximum, VDD+1.5 V cannot be higher than 7 V.
Recommended Operation Ratings
Symbol
VDD
VDCRF
Top
Parameter
Notes
Min
Max
Units
5.4
1,2
2.2
Vdd-1
-40
V
V
°C
Positive supply voltage
DC voltage on open collector outputs (RF1, RF2)
Ambient operating temperature
Vdd+1
85
Note 1: At minimum, VDD - 1.5 V cannot be lower than 1.2 V.
Note 2: At maximum, VDD+1.5 V cannot be higher than 5.5 V.
6.0 DC Electrical Characteristics
(Min/max values are valid over the whole recommended operating range Vdd = 2.2-5.4V. Typical conditions: Top = 27°C; Vdd = 3.0 V)
Digital I/O
Sym
Parameter
Supply current (TX mode, Pout = Pmax,
into 50 Ohm Load)
Sleep current
Limit
Values
Notes
Min
IddTX
Unit
typ
max
10
12
10
12
12
14
13
15
315MHz Band
mA
0.2
µA
1.5
mA
Idle current
IIDLE
Low battery voltage detector current
consumption
Wake-up timer current consumption
IVD
0.5
µA
IWUT
1.5
µA
Low battery detect threshold
Vlb
Low battery detection accuracy
5.3
±75
Digital input low level
Vil
Digital input high level
433MHz Band
868MHz Band
916MHz Band
IS
2.2
Test Conditions
V
All blocks disabled
Oscillator and baseband
enabled
Programmable in 0.1 V
steps
mV
0.3*Vdd
V
Vih
0.7*Vdd
Digital input current low
Iil
-1
1
µA
Vil = 0 V
Digital input current high
Iih
-1
1
µA
Vih = Vdd, Vdd = 5.4 V
0.4
V
Iol = 2 mA
V
Ioh = -2 mA
Digital output low level
Vol
Digital output high level
Voh
V
Vdd-0.4
Digital input capacitance
2
pF
Digital output rise/fall time
10
ns
Load = 15 pF
27
7.0 AC Electrical Characteristics
(Min/max values are valid over the whole recommended operating range Vdd = 2.2-5.4V. Typical conditions: Top = 27°C; Vdd = 3.0 V)
Transmitter
Sym
Notes
Parameter
min
Open collector output DC
current
0.1
Limit
Values
typ
Unit
max
2.5
mA
+3
Output power (Differential Load)
Output power (into 50 Ohms)
dBm
+1
916 MHz Band
315MHz Band
dBm
-60
315MHz Band
dBm
868MHz Band
916MHz Band
-35
315MHz Band
dBm
-40
433MHz Band
868MHz Band
-45
916MHz Band
-35
315MHz Band
-35
dBm
-50
2.3
868MHz Band
315MHz Band
3.1
pF
Antenna tuning capacitance
2.2
433MHz Band
916MHz Band
-55
1.6
433MHz Band
-65
-35
1.5
868 MHz Band
916 MHz Band
-65
3rd Harmonics
433 MHz Band
-4
-65
2nd Harmonics
868 MHz Band
0
-4
Reference Spur
433 MHz Band
+1
-1
PO
Programmable
315MHz Band
+3
PDL
Test Conditions
2.8
433MHz Band
868MHz Band
916MHz Band
315MHz Band
Output capacitance Quality
factor
16
18
433MHz Band
22
868MHz Band
916MHz Band
-75
Phase noise
dBc/Hz
-85
FSK bit rate
256
kbps
OOK bit rate
512
kbps
240
kHz
FSK frequency deviation
30
100 kHz from carrier
1 MHz from carrier
∆FSK = 240kHz
Programmable in 15 kHz
steps
28
Timing
Sym
Notes
Parameter
Limit Values
min
Typ
Internal POR timeout
1
Wake-up Time
PLL Characteristics
1
Sym
Parameter
PLL reference freq
Notes
2e+9
Limit Values
typ
max
8
10
12
10
PLL startup time
Crystal load capacitance
CL
8.5
Xtal oscillator startup time
Tuning Range (w/ 10MHz ref xtal)
1.25
ms
Vdd at 90% of final value
ms
Calibrated every 30 seconds
ms
Unit
min
PLL lock time
Test Conditions
max
100
Wake-up timer period
Unit
Test Conditions
MHz
us
within 1kHz settle, 10MHz step
250
us
Crystal running
16
pF
Programmable in 0.5 pF steps,
tolerance +/- 10%
5
ms
Crystal ESR < 100
310.24
319.75
430.24
439.75
860.48
879.51
900.72
929.27
315MHz Band (2.5kHz steps)
MHz
433MHz Band (2.5kHz steps)
868MHz Band (5.0kHz steps)
916MHz Band (7.5kHz steps)
29
8.0 Package Dimensions – 5x4.4mm 16-pin TSSOP Package
(all values in mm)
Detail
A
C
θ2
B
0.20
F
G
R1
R
D
E
Gauge Plane
θ1
0.25
L
θ3
L1
Detail
Symbol
4441 Sigma Road
Dallas, Texas 75244
(800) 704-6079 toll-free in U.S. and Canada
Email: [email protected]
www.rfm.com
www.wirelessis.com
rev01
A
B
C
D
E
F
G
L
L1
R
R1
θ1
θ2
θ3
Dimensions in mm
Min
Nom
Max
4.30
4.40
4.50
4.90
5.00
5.10
6.40 BSC.
0.19
0.30
0.65 BSC.
0.80
0.90
1.05
1.20
0.50
0.60
0.75
1.00 REF.
0.09
0.09
0
8
12 REF.
12 REF.
Dimensions in Inches
Min
Nom
Max
0.169 0.173
0.177
0.193 0.197
0.201
0.252 BSC.
0.007
0.012
0.026 BSC.
0.031 0.035
0.041
0.47
0.020 0.024
0.030
0.39 REF
0.004
0.004
0
8
12 REF.
12 REF.
© 2005 RF Monolithics, Inc.
TXC101 2006-03-06
30