FAIRCHILD FMS6407MTF20

www.fairchildsemi.com
FMS6407
Triple Video Drivers with Selectable
HD/Progressive/SD/Bypass Filters
Features
Description
• Three video anti-aliasing or reconstruction filters
• 2:1 Mux inputs for YPbPr / RGB or YPbPr / YC-CV inputs
• Supports D1, D2, D3 and D4 video D-connector
(EIAJ CP-4120)
• Selectable 8MHz/15MHz/30MHz 6th order filters plus
bypass for SD (480i), Progressive (480p) and HD
(1080i/ 720p)
• AC-coupled inputs include DC restore /bias circuitry
• All outputs can drive AC or DC coupled 75Ω loads and
provide either 0dB or 6dB of gain
• 0.26% differential gain, 0.11° differential phase
• Lead-free packaging
The FMS6407 offers comprehensive filtering for TV, set top
box or DVD applications. This part consists of a triple 6th
order filter with selectable 30MHz, 15MHz, or 8MHz cutoff
frequencies. The filters may also be bypassed so that the
bandwidth is limited only by the output amplifiers.
Applications
• Progressive scan
• Cable set top boxes
• Satellite set top boxes
• DVD players
• HDTV
• Personal Video Recorders (PVR)
• Video On Demand (VOD)
A 2 to 1 multiplexer is provided on each filter channel.
The triple filters are intended for YPbPr, RGB and YC-CV
signals. The DC clamp levels are set according to the input
mux selection and the CV_SEL control input. YPbPr sync
tips are clamped to 250mV, 1.125V and 1.125V respectively
while RGB sync tips are all clamped to 250mV. CV mode
clamps Y and CV to 250mV while C is clamped to 1.l25V.
Sync clamp timing can be derived from the Y or Green input
channel or from the external SYNC_IN pin.
All channels nominally accept AC coupled 1Vpp signals.
Selectable 0dB or 6dB gain allows the outputs to drive 1Vpp
or 2Vpp signals into AC or DC coupled terminated loads
with a 1Vpp input. Input signals cannot exceed 1.5Vpp and
outputs cannot exceed 2.5Vpp.
The FMS6407 draws 525mW from a single 5.0V supply.
Functional Block Diagram
SYNC_IN
Sync Strip
YIN
GIN / YIN
YOUT / GOUT / YOUT
8MHz, 15MHz, 30MHz, Bypass
EXT_SYNC
gM
250mV
PbIN
BIN / CIN
CV_SEL
Clamp
Control
gM
Selectable
0dB or 6dB
output gain
1.125V
250mV
PrIN
RIN / CVIN
RGB
PbOUT / BOUT/ COUT
8MHz, 15MHz, 30MHz, Bypass
8MHz, 15MHz, 30MHz, Bypass
PrOUT / ROUT/ CVOUT
1.125V
250mV
gM
FSEL0
0dB
FSEL1
REV. 1I July 2005
DATA SHEET
FMS6407
DC Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, all inputs AC coupled with 0.1µF, all outputs AC coupled with 220µF into 150Ω,
referenced to 400kHz; unless otherwise noted)
Symbol
Parameter
Conditions
Current1
Min
Typ
Max Units
105
130
ICC
Supply
Vi
Input Voltage Max
Vil
Digital Input Low1
FSEL1, FSEL2, RGB, 0dB,
EXT_SYNC, CV_SEL, SYNC_IN
0
0.8
V
Vih
Digital Input High1
FSEL1, FSEL2, RGB, 0dB,
EXT_SYNC, CV_SEL, SYNC_IN
2.4
VCC
V
VCLAMP1
Output Clamp Voltage
R,G,B,Y,CV
VCLAMP2
Output Clamp Voltage
Pb,Pr,C
PSRR
Power Supply Rejection Ratio
DC (all channels)
VCC no load
1.5
mA
Vpp
250
mV
1.125
V
-40
dB
Standard Definition Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
AVSD
AVSD
Parameter
SD Gain, 0dB =
‘0’1
1
SD Gain, 0dB = ‘1’
1
f1dBSD
-1dB Bandwidth for SD
fCSD
-3dB Bandwidth for SD
Conditions
Min
Typ
Max Units
All Channels SD Mode
5.6
6.0
6.4
dB
All Channels SD Mode
-0.4
0
0.4
dB
All Channels
5.5
6.75
MHz
8.2
MHz
56
dB
%
All Channels
1
fSBSD
Attenuation: SD (Stopband Reject)
All Channels at f = 27MHz
40
dG
Differential Gain
All Channels
0.26
dθ
Differential Phase
All Channels
0.11
°
THD
Output Distortion (All Channels)
Vout = 1.8Vpp at 1MHz
0.4
%
XTALK
Crosstalk (Channel-to-Channel)
at 1.0MHz
-65
dB
INMUXISO
INMUX Isolation
at 1.0MHz
-70
dB
SNR
Signal-to-Noise Ratio
All Channels, NTC-7 Weighting,
4.2MHz lowpass, 100kHz Highpass
73
dB
tpdSD
Propagation Delay for SD
Delay from Input to Output at 4.5MHz
80
ns
T1
SYNC to SYNC_IN Delay
10
ns
T2
SYNC_IN Min Pulse Width
4
µs
Progressive Scan (PS) Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
AVPS
AVPS
f1dBPS
Parameter
1
PS Gain, 0dB = ‘0’
1
PS Gain, 0dB = ‘1’
1
-1dB Bandwidth for PS
Conditions
Min
Typ
Max Units
All Channels PS Mode
5.6
6.0
6.4
dB
All Channels PS Mode
-0.4
0
0.4
dB
10
13.5
All Channels
MHz
Note:
1. 100% tested at 25°C.
2
REV. 1I July 2005
FMS6407
DATA SHEET
Progressive Scan (PS) Electrical Specifications (Continued)
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
Parameter
Conditions
fCPS
-3dB Bandwidth for PS
fSBPS
Attenuation: PS (Stopband
tpdPS
Propagation Delay for PS
T1
T2
Min
All Channels
Reject)1
All Channels at f = 54MHz
40
Typ
Max Units
15
MHz
48
dB
45
ns
SYNC to SYNC_IN Delay
10
ns
SYNC_IN Min Pulse Width
2
µs
Delay from Input to Output at 10MHz
High Definition Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with 0.1µF,
all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
AVHD
AVHD
Parameter
1
HD Gain, 0dB = ‘0’
1
HD Gain, 0dB = ‘1’
HD1
f1dBHD
-1dB Bandwidth for
fCHD
-3dB Bandwidth for HD
fSBHD
Attenuation: HD (Stopband
Conditions
Min
Typ
Max Units
All Channels HD Mode
5.6
6.0
6.4
dB
All Channels HD Mode
-0.4
0
0.4
dB
20
28
MHz
32
MHz
40
dB
All Channels
All Channels
Reject)1
All Channels at f = 74.25MHz
30
tpdHD
Propagation Delay for HD
26
ns
T1
SYNC to SYNC_IN Delay
10
ns
T2
SYNC_IN Min Pulse Width
1.5
µs
Delay from Input to Output at 20MHz
Bypass (Wide Bandwidth) Electrical Specifications
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
Symbol
Conditions
Min
Typ
Max Units
WB Gain, 0dB =
‘0’1
All Channels WB Mode
5.6
6.0
6.4
dB
AVWB
WB Gain, 0dB =
‘1’1
All Channels WB Mode
-0.4
0
0.4
dB
AVWB
Parameter
f1dBWB
-1dB Bandwidth for WB
All Channels
50
MHz
fCWB
-3dB Bandwidth for WB
All Channels
80
MHz
tpdWB
Propagation Delay for WB
Delay from Input to Output at 20MHz
10
ns
Note:
1. 100% tested at 25°C.
REV. 1I July 2005
3
DATA SHEET
FMS6407
Absolute Maximum Ratings (beyond which the device may be damaged)
Parameter
Min
Max
Units
DC Supply Voltage
-0.3
6
V
Analog and Digital I/O
-0.3
VCC + 0.3
V
60
mA
Output Current, Any One Channel (Do not exceed)
Note:
Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if operating
conditions are not exceeded.
Reliability Information
Parameter
Min
Typ
Junction Temperature
Storage Temperature Range
-65
Lead Temperature (Soldering, 10s)
θJA), TSSOP-20
Thermal Resistance (θ
θJA), ePAD TSSOP-20
Thermal Resistance (θ
Max
Units
150
°C
150
°C
300
°C
74
°C/W
37.6
°C/W
Note:
θJA), JEDEC standard multi-layer test boards, still air.
Package thermal resistance (θ
Recommended Operating Conditions
Parameter
Operating Temperature Range
VCC Range
Input Source Resistance (RSOURCE)
4
Min
Typ
0
4.75
5.0
Max
Units
70
°C
5.25
V
150
Ω
REV. 1I July 2005
FMS6407
DATA SHEET
Standard Definition Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
SD Group Delay vs. Frequency
SD Frequency Response
60
10
1 2
40
-10
1
Delay (ns)
Gain (10dB/div)
0
-20
-30
-40
-50
-60
Mkr Frequency
Gain
Ref 400kHz
6dB
1
7.65MHz
-1dB BW
2
8.54MHz
-3dB BW
3
27MHz
-53.82dB
20
0
-20
-40
3
1 = 8.2MHz (38.13ns)
fSBSD = Gain(ref) – Gain(3) = 59.82dB
-60
-70
400kHz
5
10
15
20
25
30
400kHz
5
10
Frequency (MHz)
15
20
25
30
Frequency (MHz)
SD Differential Gain
SD Noise vs. Frequency
-50
0.1
NTSC
Differential Gain (%)
-60
Noise (dB)
-70
-80
-90
-100
0
-0.1
-0.2
-0.3
-110
Min = -0.26
Max = 0.00
ppMax = 0.26
-0.4
-120
0
1.0
2.0
3.0
4.0
5.0
6.0
1st
2nd
3rd
4th
5th
6th
Frequency (MHz)
SD Differential Phase
Differential Phase (deg)
0.12
NTSC
0.08
0.04
0.00
Min = -0.00
Max = 0.11
ppMax = 0.11
-0.04
1st
REV. 1I July 2005
2nd
3rd
4th
5th
6th
5
DATA SHEET
FMS6407
Progressive Scan Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 0, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
PS Frequency Response
PS Group Delay vs. Frequency
10
30
12
20
Delay (10ns/div)
Gain (10dB/div)
0
-10
-20
-30
-40
-50
-60
Mkr Frequency
Ref 400kHz
Gain
6dB
1
15.02MHz
-1dB BW
2
16.67MHz
-3dB BW
3
54MHz
-56.37dB
1
10
0
-10
-20
1 = 15MHz (20.32ns)
3
fSBPS = Gain(ref) – Gain(3) = 62.37dB
-30
-70
400kHz
10
20
30
40
50
60
400kHz
10
Frequency (MHz)
20
30
40
50
Frequency (MHz)
High Definition Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 0, FSEL1 = 1, gain = 6dB, RS = 37.5Ω, all inputs AC coupled with 0.1µF, all
outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
HD Frequency Response
HD Group Delay vs. Frequency
10
15
1
10
2
Delay (5ns/div)
Gain (10dB/div)
0
-10
-20
-30
-40
-50
Mkr
Ref
1
2
Frequency
400kHz
29.52MHz
33.10MHz
Gain
6dB
-1dB BW
-3dB BW
3
74.25MHz
-35.36dB
3
0
-5
-10
-15
1 = 32MHz (8.60ns)
fSBHD = Gain(ref) – Gain(3) = 41.36dB
-60
400kHz 10
-20
20
30
40
50
60
Frequency (MHz)
6
1
5
70
80
90
400kHz 10
20
30
40
50
60
70
80
90
Frequency (MHz)
REV. 1I July 2005
FMS6407
DATA SHEET
Bypass (Wide Bandwidth) Typical Performance Characteristics
(TC = 25°C, Vi = 1Vpp, VCC = 5.0V, FSEL0 = 1, FSEL1 = 1, gain = 6dB, RSOURCE = 37.5Ω, all inputs AC coupled with
0.1µF, all outputs AC coupled with 220µF into 150Ω, referenced to 400kHz; unless otherwise noted)
WB Group Delay vs. Frequency
1.2
6.0
1.0
5.5
0.8
Delay (0.2ns/div)
Gain (0.5dB/div)
WB Frequency Response
6.5
5.0
1
4.5
4.0
3.5
3.0
2.5
Mkr Frequency
Ref 400kHz
1
2
Gain
6dB
60.16MHz
87.55MHz
2.0
400kHz 10
0.4
0.2
1
0
-0.2
-0.4
-1dB BW
-3dB BW
2
-0.6
1 = 80MHz (0.29ns)
-0.8
20
30
40
50
60
Frequency (MHz)
REV. 1I July 2005
0.6
70
80
90
400kHz 10
20
30
40
50
60
70
80
90 100
Frequency (MHz)
7
DATA SHEET
FMS6407
Pin Configuration
EXT_SYNC
1
20
VCC
CV_SEL
2
19
VCC
YIN
3
18
SYNC_IN
17
RGB
8
FMS6407
20-pin
TSSOP
or
ePAD TSSOP
GIN/Y
4
PbIN
5
16
YOUT
BIN/C
6
15
PbOUT
PrIN
7
14
PrOUT
RIN/CV
8
13
0dB
Pin#
Pin
Type
Description
1
EXT_SYNC
Input
Selects the external SYNC_IN
signal when set to logic ‘1’, do not
float
2
CV_SEL
Input
Selects CV mode when set to logic
‘1’ (sets C clamp to 1.125V and CV
clamp to 250mV), do not float
3
YIN
Input
Y (Luminance) input may be
connected to a signal which
includes sync
4
GIN
Input
Green or Y input
5
PbIN
Input
Pb input
6
BIN
Input
Blue or C (Chrominance) input
FSEL0
9
12
GND
7
PrIN
Input
Pr input
FSEL1
10
11
GND
8
RIN
Input
Red or CV (Composite Video) input
9
FSEL0
Input
Selects filter corner frequency or
bypass, see table, do not float
10
FSEL1
Input
Selects filter corner frequency or
bypass, see table, do not float
11
GND
Input
Must be tied to Ground, do not float
12
GND
Input
Must be tied to Ground, do not float
13
0dB
Input
Selects output gain of 0dB when set
to logic ‘1’, do not float
14
PrOUT
Output
Pr, Red, or CV output
15
PbOUT
Output
Pb, Blue, or C output
16
YOUT
Output
Y, Green, or Y output
17
RGB
Input
Selects RGB MUX inputs and clamp
mode when set to logic ‘1’, do not
float
18
SYNC_IN
Input
External sync input signal, square
wave crossing Vil and Vih input
thresholds, do not float
19
VCC
Input
+5V supply, do not float
20
VCC
Input
+5V supply, do not float
REV. 1I July 2005
FMS6407
DATA SHEET
Gain Settings
Sync Settings
0dB, Pin 13
Gain (dB)
VIN*
VOUT*
EXT_SYNC, Pin1
Sync Source
0
6
1Vpp
2Vpp
0
Y/G input, Pin 3/4
1
0
1Vpp
1Vpp
1
SYNC_IN input, Pin 2
* Video level, does not include clamp voltage which will offset the input
above ground.
Filter Settings
FSEL1, Pin 10
FSEL0, Pin 9
Filter -3dB Freq
Video Format
Sync Format
0
0
8.2MHz
SD, 480i
Bi-level, 4.7µs pulse width
0
1
15MHz
PS, 480p
Bi-level, 2.35µs pulse width
1
0
32MHz
HD, 1080i, 720p
Tri-level, 589ns pulse width
1
1
Filter Bypass
–
Bi-level, 2.35µs pulse width
Input
Output
Clamp Voltage
I/O and Clamp Settings
RGB, Pin 17
CV_SEL, Pin 2
0
X
Y, Pin 3
Y, Pin 16
250mV
(don’t care)
Pb, Pin 5
Pb, Pin 15
1.125V
Pr, Pin 7
Pr, Pin 14
1.125V
G/Y, Pin 4
G, Pin 16
250mV
B/C, Pin 6
B, Pin 15
250mV
R/CV, Pin 8
R, Pin 14
250mV
Y/G, Pin 4
Y, Pin 16
250mV
C/B, Pin 6
C, Pin 15
1.125V
CV/R, Pin 8
CV, Pin 14
250mV
1
1
REV. 1I July 2005
0
1
9
DATA SHEET
Functional Description
Introduction
The FMS6407 is a next generation filter solution from
Fairchild Semiconductor addressing the expanding filtering
needs for televisions, set top boxes, and DVD players including
progressive scan capability. The product provides selectable
filtering with cutoff frequencies of 30MHz, 15MHz, and
8.0MHz on the YPbPr, RGB and YC-CV channels. In addition, the filters can be bypassed for wider bandwidth applications. The FMS6407 allows consumer devices to support a
variety of resolution standards with the same hardware.
Multiplexers on the YPbPr / RGB / YC-CV channels provide
further flexibility. When the input multiplexer is changed
from YPbPr to RGB mode the sync tip clamp voltages are
changed appropriately. All three channels are set for 250mV
sync tips to reduce DC-coupled power dissipation for RGB
inputs. The lower output bias voltage is not suitable for the
PbPr outputs so for YPbPr inputs these signals are clamped
to 1.125V while Y is still clamped to 250mV. For systems
running YPbPr and YC-CV signals, the Y and CV signals
will be clamped to 250mV while C is clamped to 1.125V.
Sync tip clamping voltages are set by forcing the desired DC
bias level during the active sync period. For systems without
sync on green, an external sync input is provided. If sync
exists on the Y input signal but not on the G input signal, the
RGB and EXT_SYNC control inputs may be wired together
on the PCB to switch the sync source with the input source.
Both standard definition (bi-level) and high definition (trilevel) sync are supported at YIN and SYNC_IN depending
on the FSEL[1:0] inputs.
Standard definition (480i) and progressive (480p) signals are
clamped by forcing the signal to the desired voltage during
the sync pulse. For signals with sync, the sync tip itself will
be forced to the clamp voltage (typically 250mV). When
high definition sync is present (tri-level sync) the sync tip
duration is too short to allow this approach. In order to accurately clamp HD signals, the sync pulse starts a timer and the
actual clamping is done at the blanking level right after the
sync pulse. The sync tip will still typically be placed at 250mV.
All three outputs are driven by amplifiers with selectable gains
of 0dB or +6dB. These amplifiers can drive two terminated
video loads (75Ω) to 2Vpp with a 1Vpp input when set to 6dB
gain. The input range is limited to 1.5Vpp and the output range
is limited to 2.5Vpp.
All control inputs must be tied to VSS or VCC. Do not leave
them floating.
External Sync Mode
The FMS6407 can properly recover sync timing from video
signals that include sync. If the Y-input video signals does
10
FMS6407
not include sync, the FMS6407 can be used in External
SYNC Mode. When the FMS6407 is used in external sync
mode, (EXT_SYNC pin is high), a pulsed input must be
applied to the SYNC_IN pin. If there is no video signal
present, therefore no sync signal present, there must still be
an input applied to the SYNC_IN pin. When there is no
video signal on the video inputs SYNC_IN can be a sync
pulse every 60µs to mimic the slowest sync in a regular
video signal. The following two sections discuss the sync
processing and timing required in more detail.
SD and Progressive Scan
Video Sync Processing
The FMS6407 must control the DC offset of AC-coupled
input signals since the average DC level of video varies with
image content. If the input offset is allowed to wander, the
common mode input range of the amplifiers can be exceeded
leading to signal distortion. DC offset adjustment is referred
to as clamping or in some cases, biasing, and must be done at
the correct time during each video line. The optimum time is
during the sync pulse since it is the lowest input voltage.
This approach works well for 480i and 480p signals since the
sync tip duration is long enough to allow the DC-offset
errors to be compensated from line to line. The DC-offset of
the sync tip is adjusted as illustrated in Figure 1 by forcing a
current on the input during the sync pulse. The sync tip will
be clamped to approximately 250mV. Signals like Pb and Pr
with a symmetric voltage range (±350mV) will be clamped
to approximately 1.125V. Note that the following diagrams
indicate output voltage levels for both 0dB and 6dB gain
(1Vpp and 2Vpp video signals at the FMS6407 output pin).
0dB Gain 6dB
Required Pb Offset
1475mV 1875mV
1125mV 1125mV
775mV
425mV
1250mV 2250mV
Av = 1 (0dB) or 2 (6dB)
Av*700mV
550mV
850mV
250mV
250mV
0mV
0mV
Active
Active
Video
Av*300mV
Required Sync Tip Offset
Figure 1. Bi-Level Sync
Tip Clamping and Bias
In some cases, the sync voltage may be compressed to less
than the nominal 300mV value. The FMS6407 can successfully recover SD and Progressive Scan sync which is greater
than 100mV (compressed to 33% of nominal).
The FMS6407 can properly recover sync timing from luma
and green which include sync. If none of the video signals
includes sync, the EXT_SYNC control input can be set high
REV. 1I July 2005
FMS6407
DATA SHEET
and an external sync signal must be input on the SYNC_IN
pin. Refer to the External Sync section for more details. The
timing required for this operating mode is shown in Figure 2.
0dB Gain 6dB
Av = 1 (0dB) or 2 (6dB)
950mV 1650mV
Active
Video
Av*700mV
250mV
250mV
0mV
0mV
Required Blanking Offset
Sync Timing
Normally, the FMS6407 will respond to bi-level sync and
clamp the sync tip during period ‘B’ in Figure 4(a). When
the filters are switched to high definition mode (30MHz) the
sync processing will respond to tri-level sync and clamp to
the blanking level during period ‘C’ in Figure 4(b).
(a)
2250mV
480i and 480p
True Sync Position
850mV
T1
T2
250mV
Allowable SYNC_IN
A
Figure 2. Bi-Level External
Sync Clamping and Bias
(b)
720p and 1080i
When the input signal is a high definition signal, the tri-level
sync pulse is too short to allow proper clamp operation.
Rather than clamp during the sync pulse, the sync pulse is
located and the signal is clamped to the blanking level. This
is done in such a way that the sync tip will still be set to
approximately 250mV. The EXT_SYNC control input
selects the sync stripper output or the SYNC_IN pin for use
by the clamp circuit. This means that the SYNC_IN timing
for HD signals is different than the timing for SD or PS signals. For HD signals, the SYNC_IN signal must be high
when the clamp must be active. This is during the time
immediately after the sync pulse while the signal is at the
blanking level. This operation is shown in Figure 3. Note that
the following diagrams indicate output voltage levels for
both 0dB and 6dB gain (1Vpp and 2Vpp video signals at the
FMS6407 output pin).
Av = 1 (0dB) or 2 (6dB)
0H
550mV
850mV
250mV
250mV
0mV
Av*700mV
Active
Video
Av*300mV
0mV
1450mV
850mV
250mV
A
B
B
C
Figure 4. Sync Timing; Bi-Level (a), Tri-Level (b)
The tri-level sync pulse is located such that the broad pulses
in the vertical interval do not trigger the clamp. In order to
improve the system settling at turn-on, the broad pulses will
be clamped to just above ground. Once the broad pulses (and
tri-level sync tips) are above ground, the normal clamping
process takes over and clamps to the blanking level during
period ‘C’ in Figure 4(b).
The FMS6407 is designed to support the video standards
and associated sync timings shown in Table I on page 12
(additional standards such as 483p59.94 will also work
correctly). The filter settings table from page 9 is repeated on
page 12 for convenience.
0dB Gain 6dB
850mV 1450mV
C
2250mV
HD Video Sync Processing
1250mV 2250mV
B
Av*300mV
Required Sync Tip
Offset (Next Sync Tip
Will Be Offset Correctly)
True Sync Position
T1
T2
Allowable SYNC_IN
Figure 3. Tri-Level Blanking Clamp
NOTE: Tri-level sync may only be compressed 5%. If
tri-level sync is compressed more than 5% it may not be
properly located.
REV. 1I July 2005
11
DATA SHEET
FMS6407
Filter Settings
FSEL1, Pin 10
FSEL0, Pin 9
Filter -3dB Freq
Video Format
Sync Format
0
0
8.2MHz
SD, 480i
Bi-level, 4.7µs pulse width
0
1
15MHz
PS, 480p
Bi-level, 2.35µs pulse width
1
0
32MHz
HD, 1080i, 720p
Tri-level, 589ns pulse width
1
1
Filter Bypass
–
Bi-level, 2.35µs pulse width
Table I
Format
Refresh
Sample Rate
Period (T)
A
B
C
H-Rate
480i
30Hz
13.5MHz
74ns
20T = 1.5µs
64T = 4.7µs
61T = 4.5µs
15.75kHz
480p
60Hz
27MHz
37ns
20T = 750ns
64T = 2.35µs
61T = 2.25µs
31.5kHz
720p
60Hz
74.25MHz
13.4ns
70T = 938ns
40T = 536ns
220T = 2.95µs
45kHz
1080i
30Hz
74.25MHz
13.4ns
44T = 589ns
44T = 589ns
148T = 1.98µs
33.75kHz
Note: Timing values are approximate for 30Hz/60Hz refresh rates.
Application Information
Input Circuitry
The DC restore circuit in the FMS6407 requires a source
impedance (Rsource = Rs || RT) of less than or equal to 150Ω
for correct operation. Driving the FMS6407 with a highimpedance source (e.g. a DAC loaded with 330Ω) will not
yield optimum results.
Output Drive
The FMS6407 is specified to operate with output currents
typically less than 60mA, more than sufficient for a dual
(75Ω) video load. Internal amplifiers are current limited to
approximately 100mA and should withstand brief duration
short circuit conditions, however this capability is not
guaranteed.
The maximum specified input voltage of 1.5Vpp can be sustained for all inputs. When the input is clamped to 1.125V,
this does not result in a meaningful output signal. With a
gain of 6dB, the output should be 1.125V ±1.5V which is not
possible since the output cannot drive below ground. This
condition will not damage the part; however, the output will
be clipped. For signals which are clamped to 250mV, this
does not occur.
Signals that are at midscale during SYNC (Pb, Pr, C) must
be clamped to 1.125V and signals that are at their lowest
during SYNC (Y, CV, R, G, B) must be clamped to 250mV
12
for proper operation. Clamping a CV signal to 1.125V will
result in clipping the top of the signal and clamping a Pr signal to 250mV will result in clipping the bottom of the signal.
The 220µF capacitor coupled with the 150Ω termination, as
shown in the Typical Application Circuit of Figure 5, forms a
high pass filter that blocks the DC while passing the video
frequencies and avoiding tilt. Any value lower than 220µF
will create problems, such as video tilt. Higher values, such
as 470µF - 1000µF are the most optimal output coupling
capacitor. By AC coupling, the average DC level is zero.
Thus, the output voltages of all channels will be centered
around zero.
Sync Recovery
The FMS6407 will typically recover bi-level sync with
amplitude greater than 100mV (33% compressed relative to
the nominal 300mV amplitude). The FMS6407 looks for the
lowest signal voltage and clamps this to approximately
250mV at the output.
Tri-level sync may not be compressed more than 5% (15mV)
for correct operation. Tri-level sync is located by finding the
edges of the tri-level pulse and running a timer to operate the
clamp during the back porch interval.
Since only the Y/G channel is processed for sync recovery, Y
and CV inputs must be synchronous.
REV. 1I July 2005
FMS6407
DATA SHEET
Power Dissipation
•
Include 10µF and 0.1µF ceramic bypass capacitors
The FMS6407 output drive configuration must be considered
when calculating overall power dissipation. Care must be
taken not to exceed the maximum die junction temperature.
The following example can be used to calculate the
FMS4607’s power dissipation and internal temperature rise.
•
Place the 10µF capacitor within 0.75 inches of the
power pin
•
Place the 0.1µF capacitor within 0.1 inches of the
power pin
•
Connect all external ground pins as tightly as possible,
preferably with a large ground plane under the package
•
Layout channel connections to reduce mutual trace
inductance
•
Minimize all trace lengths to reduce series inductances.
If routing across a board, place device such that longer
traces are at the inputs rather than the outputs.
Tj = TA + Pd • ΘJA
where Pd = PCH1 + PCH2 + PCH3
and PCHx = Vs • ICH -
(VO2/RL)
where
VO = 2Vin + 0.280V
ICH = (ICC / 3) + (VO/RL)
Vin = RMS value of input signal
ICC = 105mA
Vs = 5V
RL = channel load resistance
Board layout can also affect thermal characteristics. Refer to
the Layout Considerations Section for more information.
The FMS6407 is specified to operate with output currents
typically less than 60mA, more than sufficient for a single
(150Ω) video load. Internal amplifiers are current limited
to a maximum of 100mA and should withstand brief duration short circuit conditions, however this capability is not
guaranteed.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance and thermal characteristics.
Fairchild offers a demonstration board, FMS6407DEMO, to
use as a guide for layout and to aid in device testing and
characterization. The FMS6407DEMO is a 4-layer board
with a full power and ground plane. For optimum results,
follow the steps below as a basis for high frequency layout:
REV. 1I July 2005
If using multiple, low impedance DC coupled outputs, special
layout techniques may be employed to help dissipate heat.
For dual-layer boards, place a 0.5” to 1” (1.27cm to 2.54cm)
square ground plane directly under the device and on the
bottom side of the board. Use multiple vias to connect the
ground planes. For multi-layer boards, additional planes
(connected with vias) can be used for additional thermal
improvements.
Worse case additional die power due to DC loading can be
estimated at (VCC2/4Rload) per output channel. This assumes
a constant DC output voltage of VCC2. For 5V VCC with a
dual DC video load, add 25/(4*75) = 83mW, per channel.
A package option with an exposed DAP is available for
improved thermal performance, see Ordering Information on
page 16. For layout recommendations using the ePAD package , refer to the following: http://www.amkor.com/products/
notes_papers/epad.pdf
13
DATA SHEET
YIN
FMS6407
0.1μF
Rs
3
75Ω
RT
75Ω
GIN/Y
VCC
Rs
4
75Ω
PbIN
YOUT
5
75Ω
PbIN
PbOUT
RT
75Ω
BIN/C
6
75Ω
BIN/C
RT
75Ω
PrIN
75Ω Video Cables
15 75Ω
220μF
75Ω Video Cables
PrOUT
14 75Ω
220μF
75Ω Video Cables
75Ω
0.1μF
Rs
220μF
75Ω
0.1μF
Rs
16 75Ω
75Ω
0.1μF
Rs
1μF
May also be DC
coupled
GIN/Y
RT
75Ω
0.1μF
19
FMS6407
20L TSSOP
Rsource = RS || RT
0.1μF
VCC
YIN
+5V
20
7
75Ω
PrIN
RT
75Ω
RIN/CV
0.1μF
Rs
75Ω
RT
75Ω
8
GND
RIN/CV
GND
12
11
Note: Pins 1, 2, 9, 10, 13, 17, and 18 will need
to be set according to the input signal format
Figure 5. Typical Application Circuit
14
REV. 1I July 2005
FMS6407
DATA SHEET
Package Dimensions
TSSOP-20 and ePAD TSSOP-20
4
1.00
B
1.00 DIA.
C
B
3 2 1
B
E/2
1.00
C
L
E
E1 5
0.20
C
A-B
D
N
7
2X N/2 TIPS
D
A
4
SEE DETAIL "A"
e/2
X
4
X
TOP VIEW
b
bbb M C A-B
A2
D
ODD LEAD SIDES
TOPVIEW
(14°)
SIDE VIEW
9
X = A AND B
X = A AND B
EVEN LEAD SIDES
TOPVIEW
END VIEW
(b)
0.05 C
A
b1
C
WITH PLATING
H
aaa
3
e
A1
D
5
C
8
0.25
SEATING
PLANE
c1
PARTING
LINE
(c)
H
13
L 6
P
(OC)
BASE METAL
(1.00)
SECTION "B-B"
(14°)
SCALE: 120/1
(SEE NOTE 10)
DETAIL "A"
SCALE: 30/1
(VIEW ROTATED 90° C.W.)
P1 13
SYM
EXPOSED PAD VIEW
NOM.
0.05
0.85
b
0.19
b1
0.19
0.15
0.90
0.30
0.22
c
c1
D
0.09
0.09
6.40
E1
e
4.30
1.
2.
DIE THICKNESS ALLOWABLE IS 0.279±0.0127 (.0110±.0005 INCHES)
DIMENSIONING & TOLERANCES PER ASME. Y14.5M-1994.
3.
DATUM PLANE H LOCATED AT MOLD PARTING LINE AND COINCIDENT
WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
4.
DATUM A-B AND D TO BE DETERMINED WHERE CENTERLINE
0.95
9
BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H.
0.25
5.
0.10
bbb
0.127
6.50
0.20
0.16
6.60
5
4.40
4.50
5
6.
0.65 BSC
7.
6.40 BSC
E
0.50
P
P1
OC
Note
0.076
aaa
L
N
MAX.
1.10
A
A1
A2
NOTES:
Common Dimensions
MIN.
0.60
0.70
6
20
7
4.2
13
3.0
0°
8.
9.
13
8°
Note: For 0.65mm pitch.
All dimensions in millimeters.
10.
11.
12.
13.
REV. 1I July 2005
"D" & "E1" ARE REFERENCE DATUM AND DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS, AND ARE MEASURED AT THE BOTTOM PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm ON D AND 0.25mm
ON E PER SIDE.
DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY.
FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.076mm AT SEATING PLANE.
THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE
0.07mm TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION
AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND AN ADJACENT LEAD SHOULD
BE 0.07mm FOR 0.65MM PITCH, 0.08MM FOR 0.50MM PITCH AND
0.07MM FOR 0.40MM PITCH PACKAGES. SEE SECTION "B-B".
SECTION "B-B" TO BE DETERMINED AT 0.10
TO 0.25 MM FROM THE LEAD TIP.
CONTROLLING DIMENSION: MILLIMETERS.
THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153
VARIATIONS AA/AAT, AB-1/ABT-1, AB/ABT, AC/ACT, AD/ADT, AE/AET
BC-1/BCT-1, BD-1/BDT-1, BE/BET, CA/CAT & CD/CDT
AND MO-194 VARIATIONS AC/ACT & AF/AFT.
DIMENSIONS "P" AND "P1" ARE THERMALLY ENHANCED VARIATIONS. VALUES
SHOWN ARE MAXIMUM SIZE OF EXPOSED PAD WITHIN LEAD COUNT AND BODY SIZE.
END USER SHOULD VERIFY AVAILABLE SIZE OF EXPOSED PAD FOR SPECIFIC
DEVICE APPLICATION.
15
DATA SHEET
FMS6407
Ordering Information
Model
Part Number
Lead
Free
Package
Container
Pack Qty
FMS6407
FMS6407MTC20
Yes
TSSOP-20
Tube
94
FMS6407
FMS6407MTC20X
Yes
TSSOP-20
Tape and Reel
2500
FMS6407
FMS6407MTF20
Yes
ePAD TSSOP-20
Tube
94
FMS6407
FMS6407MTF20X
Yes
ePAD TSSOP-20
Tape and Reel
2500
Temperature range for all parts: 0°C to +70°C.
16
REV. 1I July 2005
FMS6407
DATA SHEET
75$'(0$5.6
7KHIROORZLQJDUHUHJLVWHUHGDQGXQUHJLVWHUHGWUDGHPDUNV)DLUFKLOG6HPLFRQGXFWRURZQVRULVDXWKRUL]HGWRXVHDQGLV
QRWLQWHQGHGWREHDQH[KDXVWLYHOLVWRIDOOVXFKWUDGHPDUNV
$&([Œ
,QWHOOL0$;Œ
)$67¡
$FWLYH$UUD\Œ
,623/$1$5Œ
)$67UŒ
%RWWRPOHVVŒ
/LWWOH)(7Œ
)36Œ
&RRO)(7Œ
0,&52&283/(5Œ
)5)(7Œ
&526692/7Œ *OREDO2SWRLVRODWRUŒ 0LFUR)(7Œ
'20(Œ
0LFUR3DNŒ
*72Œ
(FR63$5.Œ +L6H&Œ
0,&52:,5(Œ
(&026Œ
06;Œ
,&Œ
(Q6LJQDŒ
06;3URŒ
L/RŒ
)$&7Œ
,PSOLHG'LVFRQQHFWŒ 2&;Œ
)$&74XLHW6HULHVŒ
2&;3URŒ
¡
$FURVVWKHERDUG$URXQGWKHZRUOGΠ2372/2*,&
23723/$1$5Œ
7KH3RZHU)UDQFKLVH¡
3$&0$1Œ
3URJUDPPDEOH$FWLYH'URRSŒ
323Œ
3RZHUŒ
3RZHU(GJHŒ
3RZHU6DYHUŒ
3RZHU7UHQFK¡
4)(7¡
46Œ
472SWRHOHFWURQLFVŒ
4XLHW6HULHVŒ
5DSLG&RQILJXUHŒ
5DSLG&RQQHFWŒ
M6HU'HVŒ
6,/(176:,7&+(5¡
60$5767$57Œ
630Œ
6WHDOWKŒ
6XSHU)(7Œ
6XSHU627Œ
6XSHU627Œ
6XSHU627Œ
6\QF)(7Œ
7LQ\/RJLF¡
7,1<2372Œ
7UX7UDQVODWLRQŒ
8+&Œ
8OWUD)(7¡
8QL)(7Œ
9&;Œ
',6&/$,0(5
)$,5&+,/'6(0,&21'8&7255(6(59(67+(5,*+7720$.(&+$1*(6:,7+287)857+(5127,&(72$1<
352'8&76+(5(,172,03529(5(/,$%,/,7<)81&7,2125'(6,*1)$,5&+,/''2(6127$6680($1</,$%,/,7<
$5,6,1*2872)7+($33/,&$7,212586(2)$1<352'8&725&,5&8,7'(6&5,%('+(5(,11(,7+(5'2(6,7
&219(<$1</,&(16(81'(5,763$7(175,*+761257+(5,*+762)27+(56
/,)(683325732/,&<
)$,5&+,/'¶6352'8&76$5(127$87+25,=(')2586($6&5,7,&$/&20321(176,1/,)(6833257
'(9,&(6256<67(06:,7+2877+((;35(66:5,77(1$33529$/2))$,5&+,/'6(0,&21'8&725&25325$7,21
$V XVHG KHUHLQ
$FULWLFDOFRPSRQHQWLVDQ\FRPSRQHQWRIDOLIH
/LIH VXSSRUW GHYLFHV RU V\VWHPV DUH GHYLFHV RU
VXSSRUWGHYLFHRUV\VWHPZKRVHIDLOXUHWRSHUIRUPFDQ
V\VWHPVZKLFKDDUHLQWHQGHGIRUVXUJLFDOLPSODQWLQWR
EHUHDVRQDEO\H[SHFWHGWRFDXVHWKHIDLOXUHRIWKHOLIH
WKH ERG\ RU E VXSSRUW RU VXVWDLQ OLIH RU F ZKRVH
VXSSRUW GHYLFH RU V\VWHP RU WR DIIHFW LWV VDIHW\ RU
IDLOXUH WR SHUIRUP ZKHQ SURSHUO\ XVHG LQ DFFRUGDQFH
ZLWKLQVWUXFWLRQVIRUXVHSURYLGHGLQWKHODEHOLQJFDQEH
HIIHFWLYHQHVV
UHDVRQDEO\H[SHFWHGWRUHVXOWLQVLJQLILFDQWLQMXU\WRWKH
XVHU
352'8&767$786'(),1,7,216
'HILQLWLRQ RI 7HUPV
'DWDVKHHW ,GHQWLILFDWLRQ
3URGXFW6WDWXV
'HILQLWLRQ
$GYDQFH,QIRUPDWLRQ
)RUPDWLYHRU
,Q'HVLJQ
7KLV GDWDVKHHW FRQWDLQV WKH GHVLJQ VSHFLILFDWLRQV IRU
SURGXFWGHYHORSPHQW6SHFLILFDWLRQVPD\FKDQJHLQ
DQ\PDQQHUZLWKRXWQRWLFH
3UHOLPLQDU\
)LUVW3URGXFWLRQ
7KLVGDWDVKHHWFRQWDLQVSUHOLPLQDU\GDWDDQG
VXSSOHPHQWDU\GDWDZLOOEHSXEOLVKHGDWDODWHUGDWH
)DLUFKLOG6HPLFRQGXFWRUUHVHUYHVWKHULJKWWRPDNH
FKDQJHVDWDQ\WLPHZLWKRXWQRWLFHLQRUGHUWRLPSURYH
GHVLJQ
1R,GHQWLILFDWLRQ1HHGHG
)XOO3URGXFWLRQ
7KLV GDWDVKHHW FRQWDLQV ILQDO VSHFLILFDWLRQV )DLUFKLOG
6HPLFRQGXFWRUUHVHUYHVWKHULJKWWRPDNHFKDQJHVDW
DQ\WLPHZLWKRXWQRWLFHLQRUGHUWRLPSURYHGHVLJQ
2EVROHWH
1RW,Q3URGXFWLRQ
7KLV GDWDVKHHW FRQWDLQV VSHFLILFDWLRQV RQ D SURGXFW
WKDWKDVEHHQGLVFRQWLQXHGE\)DLUFKLOGVHPLFRQGXFWRU
7KHGDWDVKHHWLVSULQWHGIRUUHIHUHQFHLQIRUPDWLRQRQO\
5HY,
www.fairchildsemi.com
© 2005 Fairchild Semiconductor Corporation