www.fairchildsemi.com KH231 Fast Settling, Wideband Buffer/Amplifier (Av = ±1 to ±5) Features ■ ■ ■ ■ ■ ■ General Description The KH231 Buffer/Amplifier is a wideband operational amplifier designed specifically for high-speed, lowgain applications. The KH231 is based on a current feedback op amp topology-a unique design that both eliminates the gain-bandwidth tradeoff and permits unprecedented high-speed performance. (See table below.) 165MHz closed-loop – -3dB bandwidth 15ns settling to 0.05% 1mV input offset voltage, 10µV/°C drift 100mA output current Excellent AC and DC linearity Direct replacement for CLC231 Applications ■ ■ ■ ■ Driving flash A/D converters Precision line driving (a gain of 2 cancels matched-line losses) DAC current-to-voltage conversion Low-power, high-speed applications (50mW @ ±5V) Output Voltage (400mV/div) Small Signal Pulse Response Av = 2 Offsets and drifts, usually a low priority in conventional high-speed op amp designs, were not ignored in the KH231; the input offset voltage is typically 1mV and input offset voltage drift is only 10µV/°C. The KH231 is stable and oscillation-free across the entire gain range and since it’s internally compensated, the user is saved the trouble of designing external compensation networks and having to “tweak” them in production. The absence of a gain-bandwidth tradeoff in the KH231 allows performance to be predicted easily; the table below shows how the bandwidth is affected very little by changing the gain setting. Av = -2 Time (5ns/div) Bottom View ICC Adjust Case ground GND 7 Supply Voltage Adjust -VCC 9 8 -VCC Non-Inverting Input 10 V+ 6 Inverting Input V- 5 Not Connected NC 4 4 - 4 GND Collector Supply 11 Vo Output 12 Collector Supply +VCC 3 Case ground + The KH231 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: 1 2 Adjust +VCC Supply Voltage The KH231 is constructed using thin film resistor/bipolar transistor technology, and available in these versions: ICC Adjust Pins 2 and 8 are used to adjust the supply current or to adjust the offset voltage (see text). These pins are normally left unconnected. Typical Performance Gain Setting Parameter 1 2 5 -3dB bandwidth 180 165 130 rise time (2V) 1.8 2.0 2.5 slew rate 2.5 3.0 3.0 settling time (to 0.1%) 12 12 12 -1 The KH231 Buffer/Amplifier is the ideal design alternative to low precision open-loop buffers and oscillationprone conventional op amps. The KH231 offers precise gains from ±1.000 to ±-5.000 and linearity that is a true 0.1%-even for demanding 50Ω loads. Open-loop buffers, on the other hand, offer a nominal gain of 0.95 ±0.03 and a linearity of only 3% for typical loads. A buffer’s settling time may look impressive but it is usually specified at unrealistically large load resistances or when the effects of thermal tail are not included; the KH231 Buffer/Amplifier settles to 0.05% in 15ns-while driving a 100Ω load. -2 -5 165 150 115 2.0 2.2 2.9 3.0 3.0 3.0 12 12 15 KH231AI KH231AK -25°C to +85°C -55°C to +125°C KH231AM -55°C to +125°C KH231HXC KH231HXA -55°C to +125°C -55°C to +125°C Units MHz ns V/ns ns 12-pin TO-8 can 12-pin TO-8 can, features burn-in & hermetic testing 12-pin TO-8 can, environmentally screened and electrically tested to MIL-STD-883 SMD#: 5962-8959401HXC SMD#: 5962-8959401HXA REV. 1A February 2001 DATA SHEET KH231 KH231 Electrical Characteristics (TA = +25°C, Av = +2V, VCC = ±15V, RL = 100Ω, Rf = 250Ω; unless specified) PARAMETERS CONDITIONS Ambient Temperature KH231AI +25°C -25°C +25°C +85°C Ambient Temperature KH231AK/AM/HXC/HXA +25°C -55°C +25°C +125°C 165 95 >145 >80 >145 >80 0.1 0.1 0.4 3.5 ± 0.5 0.5 <0.6 <1.5 <0.6 – <2.0 53 36 FREQUENCY DOMAIN RESPONSE ✝ -3dB bandwidth (note 2) large-signal bandwidth gain flatness (note 2) ✝ peaking ✝ peaking ✝ rolloff group delay linear phase deviation reverse isolation non-inverting inverting TIME DOMAIN RESPONSE rise and fall time settling time to 0.05% to 0.1% overshoot slew rate (overdriven input) overload recovery <50ns pulse, 200% overdrive Vo ≤2Vpp Vo ≤10Vpp Vo ≤2Vpp 0.1 to 50MHz >50MHz at 100MHz to 100MHz to 100MHz 2V step 10V step 5V step 2.5V step 5V step TYP MIN & MAX RATINGS UNITS SYM >120 >60 MHz MHz SSBW FPBW <0.3 <0.3 <0.6 – <2.0 <0.6 <0.8 <1.0 – <2.0 dB dB dB ns ° GFPL GFPH GFR GD LPD >43 >26 >43 >26 >43 >26 dB dB RINI RIIN 2.0 5.0 15 12 5 3.0 <2.4 <7.0 – <22 <15 >2.5 <2.3 <6.5 – <17 <10 >2.5 <2.7 <6.5 – <22 <15 >1.8 ns ns ns ns % V/ns TRS TRL TS TSP OS SR 120 – – – ns OR <1% error NOISE AND DISTORTION RESPONSE ✝ 2nd harmonic distortion 0dBm, 20MHz ✝ 3rd harmonic distortion 0dBm, 20MHz equivalent input noise noise floor >5MHz integrated noise 5MHz to 200MHz -55 -59 <-47 <-47 <-47 <-47 <-47 <-47 dBc dBc HD2 HD3 -153 70 <-150 <100 <-150 <100 <-150 <100 dBm(1Hz) µVrms SNF INV STATIC, DC PERFORMANCE * input offset voltage average temperature coefficient * input bias current average temperature coefficient * input bias current average temperature coefficient * power supply rejection ratio common mode rejection ratio * supply current 1 10 5.0 50 10 125 50 46 18 <4.0 <25 <29 <125 <31 <200 >45 >40 <22 <2.0 <25 <21 <125 <15 <200 >45 >40 <22 <4.5 <25 <31 <125 < 35 <200 >45 >40 <22 mV µV/°C µA nA/°C µA nA/°C dB dB mA VIO DVIO IBN DIBN IBI DIBI PSRR CMRR ICC 400 1.3 5, 37 ±12 >100 <2.5 – >±11 >200 <2.5 – >±11 >400 <2.5 – >±11 kΩ pF Ω, nH V RIN CIN RO VO MISCELLANEOUS PERFORMANCE non-inverting input resistance non-inverting input capacitance output impedance output voltage range non-inverting inverting no load DC @ 100MHz no load Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Absolute Maximum Ratings VCC Io common mode input voltage, Vo differential input voltage thermal resistance junction temperature operating temperature storage temperature lead temperature (soldering 10s) note 1: note 2: 2 * ✝ Recommended Operating Conditions ±20V ±100mA (see Vcm and Vo limits plot on page 3) ±3V (see thermal model) +175°C AI: -25°C to +85°C AK/AM: -55°C to +125°C -65°C to +150°C +300°C AI/AK/AM/HXC/HXA 100% tested at +25°C AK/AM/HXC/HXA 100% tested at +25°C and sample tested at -55°C and +125°C ✝ AI sample tested at +25°C The output amplitude used in testing is 0.63Vpp. Performance is guaranteed for conditions listed. VCC Io common mode input voltage gain range note 3: note 4: ±5V to ±15V ±75mA ±(|VCC| -5)V ±1 to ±5 In the noninverting configuration, care should be taken when choosing Ri, the input impedance setting resistor; bias currents of typically 5µA but as high as 24µA can create an input signal large enough to cause overload. It is therefore recommended that Ri < (VCC/Av)/24µA. These ratings protect against damage to the input stage caused by saturation of either the input or output stages at lower supply voltages, and against exceeding transistor collector-emitter breakdown ratings at high supply voltages. Vout(max) is calculated by assuming no output saturation. Saturation is allowed to occur up to this calculated level of Vout. Vcm is defined as the voltage at the non-inverting input, pin 6. REV. 1A February 2001 KH231 DATA SHEET KH231 Typical Performance Characteristics (T A Av = 2 Phase (45 deg/div) Av = 5 Av = 1 Phase Av = 5 Av = 2 Av = 1 0 100 Gain Av = -5 Phase Av = -1 Av = -5 Av = -2 Av = -1 0 200 Av = 2 Gain Av = -2 100 Frequency (MHz) Magnitude (10dB/div) Gain Broadband Gain and Phase Phase (180 deg/div) Normalized Magnitude (1dB/div) Inverting Frequency Response Phase (45 deg/div) Normalized Magnitude (1dB/div) Non-Inverting Frequency Response = +25°C, Av = +2, VCC = ±15V, RL = 100Ω, Rf = 250Ω; unless specified) Phase 0 200 500 Frequency (MHz) Bandwidth vs. VCC 1000 Frequency (MHz) Frequency Response vs. RL Full Power Gain vs. Frequency 1.2 Av = 2 Vo = 10Vpp RL = 1K Pins 1 and 2 Shorted Pins 8 and 9 shorted Inverting 0.8 (1dB/div) 1.0 (1dB/div) Relative Bandwidth Av = 2 RL = 200 RL = 50 Non-Inverting 0.6 RL = 100 0.4 4 6 8 10 12 14 16 0 125 ±VCC (V) 0 250 100 Frequency (MHz) 2nd and 3rd Harmonic Distortion Intercept Equivalent Input Noise 2-Tone, 3rd Order Intermod. Intercept 130 200 Frequency (MHz) 100 100 50 I2 90 70 3rd harmonic intercept exceeds +65dBm below 350KHz 50 I3 30 45 Inverting Current 23.8pA/√Hz Noise Voltage (nV/√Hz) 2nd harmonic intercept exceeds +120dBm below 350KHz Intercept Point (+dBm) 110 40 35 30 25 10k 100k 1M 10M 10 Voltage 2.8nV/√Hz 1 20 1k Non-Inverting Current 2.5pA/√Hz 10 100M 20 0 Frequency (Hz) 40 60 80 1k 100 100 100k 1M 10M 1 100M Frequency (Hz) Frequency (MHz) Small Signal Pulse Response 10k Noise Current (pA/√Hz) Intercept Point (+dBm) Av = 2 Settling Time Large Signal Pulse Response 0.15 Output Voltage (2V/div) Av = 2 Av = -2 Av = 2 Settling Error (%) Output Voltage (400mV/div) 0.20 Av = -2 0.10 5ns/div 0.05 0 50ns/div -0.05 -0.10 -0.15 -0.20 Time (5ns/div) Time (ns) Time (5ns/div) CMRR and PSRR Vcm and Vo Voltage Limits 20 PSRR |Vout| max |Vcm| max Indicated Voltage PSRR/CMRR (dB) 50 CMRR 40 30 20 15 |Vout| max 10 note 4 on page 2 5 |Vcm| max 10 0 1 10 100 1k 10k 100k Frequency (Hz) REV. 1A February 2001 1M 10M 100M 0 5 10 15 20 |±VCC| (V) 3 DATA SHEET KH231 Operation The KH231 Buffer/Amplifier is based on the current feedback op amp topology, a design that uses current feedback instead of the usual voltage feedback. The use of the KH231 is basically the same as that of the conventional op amp (see Figures 1 and 2). Since the device is designed specifically for low gain applications, the best performance is obtained when the circuit is used at gains between ±1 and ±5. Additionally, performance is optimum when a 250Ω feedback resistor is used. 33Ω +15V 3.9 0.1 .01 Capactance in µF 6 Vin + 12 KH231 Rg Ri 49.9Ω 1 5 11 Vo 10 - 3,7 250Ω 9 RL 100Ω 33Ω -15V 3.9 0.1 A v = 1+ .01 Rf Rg Rf = 250Ω Figure 1: Recommended non-inverting gain circuit +15V 3.9 33Ω 0.1 .01 Capactance in µF 100Ω Rg Vin 6 1 + 12 KH231 5 - 3,7 9 Ri 11 Vo 10 250Ω 33Ω -15V 3.9 0.1 .01 RL 100Ω Rf Av = − Rg Rf = 250Ω For Zin = 50Ω, select Rg || Ri = 50Ω Figure 2: Recommended inverting gain circuit Layout Considerations To assure optimum performance the user should follow good layout practices which minimize the unwanted coupling of signals between nodes. During initial breadboarding of the circuit use direct point to point wiring, keeping the lead lengths to less than 0.25”. The use of solid, unbroken ground plane is helpful. Avoid wire-wrap 4 type pc boards and methods. Sockets with small, short pin receptacles may be used with minimal performance degradation although their use is not recommended. During pc board layout keep all traces short and direct The resistive body of Rg should be as close as possible to pin 5 to minimize capacitance at that point. For the same reason, remove ground plane from the vicinity of pins 5 and 6. In other areas, use as much ground plane as possible on one side of the board. It is especially important to provide a ground return path for current from the load resistor to the power supply bypass capacitors. Ceramic capacitors of 0.01 to 0.1µf (with short leads) should be less than 0.15 inches from pins 1 and 9. Larger tantalum capacitors should be placed within one inch of these pins. VCC connections to pins 10 and 12 can be made directly from pins 9 and 1, but better supply rejection and settling time are obtained if they are separately bypassed as in figures 1 and 2. To prevent signal distortion caused by reflections from impedance mismatches, use terminated microstrip or coaxial cable when the signal must traverse more than a few inches. Since the pc board forms such an important part of the circuit, much time can be saved if prototype boards of any high frequency sections are built and tested early in the design phase. Evaluation boards designed for either inverting or non-inverting gains are available. Distortion and Noise The graphs of intercept point, I2 and I3, versus frequency on the preceding page make it easy to predict the distortion at any frequency given the output voltage of the KH231. First, convert the output voltage (Vo) to Vrms = (Vpp/2√2) and then to P = [(10log10(20Vrms2)] to get the power output in dBm. At the frequency of interest, its 2nd harmonic will be S2 = (I2-P)dB below the level of P. Its third harmonic will be S3 = 2(I3- P)dB below P, as will the two-tone third order intermodulation products. These approximations are useful for P < -1dB compression levels. Approximate noise figure can be determined for the KH231 using the equivalent input noise graph on the preceding page. The following equation can be used to determine noise figure (F) in dB. i n2 R f 2 2 Vn + Av2 F = 10log 1 + 4kTR s ∆f Where Vn is the rms noise voltage and in is the rms noise current. Beyond the breakpoint of the curves (i.e., where they are flat), broadband noise figure equals spot noise figure, so ∆f should equal one (1) and Vn and in should be read directly off the graph. Below the breakpoint, the noise must be integrated and ∆f set to the appropriate bandwidth. REV. 1A February 2001 KH231 DATA SHEET Offset Voltage Adjustment If trimming of the input offset voltage (Vos = Vni -Vin) is desired, a resistor value of 10kΩ to 1MΩ placed between pins 8 and 9 will cause Vos to become more negative by 8mV to 0.2mV respectively. Similarly, a resistor placed between pins 1 and 2 will cause Vos, to become more positive. Thermal Considerations At high ambient temperatures or large internal power dissipations, heat sinking is required to maintain acceptable junction temperatures. Use the thermal model on the previous page to determine junction temperatures. Many styles of heat sinks are available for TO-8 packages; the Thermalloy 2240 and 2268 are good examples. Some heat sinks are the radial fin type which cover the pc board and may interfere with external components. An excellent solution to this problem is to use surface mounted resistors and capacitors. They have a very low profile and actually improve high frequency performance. For use of these heat sinks with conventional components, a 0.1” high spacer can be inserted under the TO-8 package to allow sufficient clearance. Tcase 100°C/W Tj(pnp) Ppnp 100°C/W Tj(npn) Pnpn 17.5°C/W θca Tj(circuit) Pcircuit + Tambient P(circuit) = (ICC)((+VCC) – (VCC)) where ICC = 16mA at ±15V P(xxx) = [(±VCC) – Vout – (Icol) (Rcol + 4)] (Icol) (%Duty) For positive Vo and VCC, this is the power in the npn device. For negative Vo and VCC, this is the power in the pnp device. θca = 65°C/W for the KH231 without heat sink in still air. 30°C/W for the KH231 with a Wakefield 215 heat sink in still air. 10°C/W for the KH231 with a Wakefield 215 heat sink at 300 ft/min air. 30°C/W for the KH231 with a Thermalloy 2240A heat sink in still air. 5°C/W for the KH231 with a Thermalloy 2240A heat sink at 500 ft/min air. For example, with the KH231 operating at ±15V while driving a 100Ω load at 15Vpp output (50% duty cycle pulse waveform, DC = 0), P(npn) = P(pnp) = 190mW (Rcol = 33) and P(cir) = 0.48W. Then with the Wakefield 215 heat sink and air flow of 300 ft/min the output transistors’ Tj is 28°C above ambient and worst case Tj in the rest of the circuit is 32°C above ambient. In still air, however, the rise in Tj is 45°C and 49°C, respectively. With no heat sink, the rise in Tj is 75°C and 79°C, respectively! Under most conditions, HEAT SINKING IS REQUIRED. Other methods of heat sinking may be used, but for best results, make contact with the base of the KH231 package, use a large thermal capacity heat sink and use forced air convection. Low VCC Operation: Supply Current Adjustment The KH231 is designed to operate on supplies as low as ±5V. In order to improve full bandwidth at reduced supply voltages, the supply current (ICC) must be increased. The plot of Bandwidth vs. VCC, shows the effect of shorting pins 1 and 2 and pins 8 and 9; this will increase both bandwidth and supply current. Care should be taken to not exceed the maximum junction temperatures; for this reason this technique should not be used with supplies exceeding ±10V. For intermediate values of VCC, external resistors between pins 1 and 2 and pins 8 and 9 can be used. Icol = Vo/RL or 4mA, whichever is greater. (Include feedback R in RL.) Rcol is a resistor (33Ω recommended) between the xxx collector and ±VCC. The limiting factor for output current and voltage is junction temperature. Of secondary importance is I(out), which should not exceed 150mA. Tj(pnp) = P(pnp) (100 + θca) + (P(cir) + P(npn))(θca) + Ta, similar for Tj(npn). Tj(cir) = P(cir)(48 + θca) + (P(pnp) + P(npn))(θca) + Ta. REV. 1A February 2001 5 DATA SHEET KH231 KH231 Package Dimensions L A e1 e2 7 φD e D1 8 9 6 10 5 11 4 12 k φb 3 2 1 α F k1 TO-8 SYMBOL INCHES Minimun Maximum MILIMETERS Minimum Maximum A 0.142 0.181 3.61 4.60 φb 0.016 0.019 0.41 0.48 φD 0.595 0.605 15.11 15.37 φD1 0.543 0.555 13.79 14.10 e 0.400 BSC 10.16 BSC e1 0.200 BSC 5.08 BSC e2 0.100 BSC 2.54 BSC F 0.016 0.030 0.41 0.76 k 0.026 0.036 0.66 0.91 k1 0.026 0.036 0.66 0.91 L 0.310 0.340 7.87 8.64 α 45° BSC NOTES: Seal: cap weld Lead finish: gold per MIL-M-38510 Package composition: Package: metal Lid: Type A per MIL-M-38510 45° BSC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2001 Fairchild Semiconductor Corporation