T6LD4 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic T6LD4 Gate Driver for TFT LCD Panels Unit : mm The T6LD4 is a 350 / 342-channel output gate driver for TFT LCD panels. T6LD4 User Pitch Area IN OUT For the latest TCP / COF specifications and product line-up, contact Toshiba or your local sales office. Features • LCD drive output pins • Logic power supply voltage : Switchable 350 / 342 pins : 2.3 to 3.6V • LCD drive voltage : max 43.5V • Data transfer method : Bidirectional shift register • Operating temperature : −20 to 75°C • Package : COF • Built-in power on reset circuit COF (Chip On Film) Application Modules for PC monitor and Note PC 1 2006-09-20 T6LD4 Block Diagram DO/I DI/O CPV Bidirectional shift registers U/D MODE Input circuit block Control circuit block OE VGG Output circuit block VEE VDD VSS G1 2 G2 G3 G348 G349 G350 2006-09-20 T6LD4 Pin Assignment G350 G349 G348 365 364 363 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T6LD4 (chip top view) G3 G2 G1 VGG VEE VDD DO/I OE CPV (VDD) U/D (VSS) MODE (VDD) DI/O VSS VEE VGG 18 17 16 The above diagram shows the device’s pin configuration only and does not necessarily correspond to the pad layout on the chip. Please contact Toshiba or our distributors for the latest COF specification. 3 2006-09-20 T6LD4 Pin Description Signal Name I/O Function Vertical shift data input/output pins These pins are used to input and output shift data. The function of these pins is switched for input or output by U/D as shown below: DI/O DO/I I/O U/D DI/O DO/I H Input Output L Output Input When set for input The data is latched into the internal shift registers synchronously with the rising edge of CPV. When set for output When two or more T6LD4s are cascaded, this pin outputs the data to be fed into the next stage. This data changes state synchronously with the falling edge of CPV. U/D I Transfer direction select pin This pin specifies the direction in which data is transferred through the shift registers. The shift register data is shifted synchronously with each rising edge of CPV as follows: When U/D is high, data is shifted in the direction U/D = “H”: G1 → G2 → G3 → G4 → ··· → G350 When U / D is low, the direction is reversed to give U/D = “L”: G350 → G349 → G348 → G347 → ··· → G1 The voltage applied to this pin must be a DC-level voltage that is either high (VDD) or low (VSS). Apply the same DC-level voltage to these pins. CPV I Vertical shift clock pin This is the shift clock for the shift registers. Data is shifted through the shift registers synchronously with the rising edge of CPV. I Output enable pin This signal controls the data appearing at the TFT -LCD panel drive pins (G1 to G350). This pin operates asynchronously with CPV. OE = high level : controls the LCD panel drive output to VEE OE = low level : outputs shift data and data contents. OE Output select pin This signal selects 350 / 342-pin mode for the LCD panel driver. MODE I MODE Output mode The unapplied LCD panel drive pins H 350-out ⎯ L 342-out G171 to G178 (VEE level) The voltage applied to this pin must be a DC -level voltage that is either high (VDD) or low (VSS). G1 to G350 O TFT-LCD panel driver pins These pins output the shift register data or the voltage of VGG or VEE depending on the control OE signal. VGG Power supply for TFT-LCD drive pin VEE Power supply for TFT-LCD drive pin VDD Power supply for the internal logic pin These signals arranged right and left is connected on the film. Apply the same voltage to these pins. The (VDD) is the pin for connection. VSS Power supply for the internal logic pin These signals arranged right and left is connected on the film. Apply the same voltage to these pins. The (VSS) is the pin for connection. 4 2006-09-20 T6LD4 Device Operation ● Shift data transfer method MODE H L Output Mode 350-out Shift data U/DPin Data Transfer Method Input Output H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G350 L DO/I DI/O G350 → G349 → G348 → ··· → G1 H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G170→ G179 → ··· → G350 L DO/I DI/O G350 → G349 → G348 → ···→ G179 → G170 → ··· → G1 342-out The input data (DI/O or DO/I) is latched into the internal register synchronously with the rising edge of the shift clock CPV. At the same time that the data is shifted to the next register at the next rise of CPV, new vertical shift data is latched into. In the output operation, the data in the last shift register (G350 or G1) is output synchronously with the falling edge of CPV. (The output high voltage is the VDD level; the output low voltage is the VSS level.) 5 2006-09-20 T6LD4 Timing Chart 1 ( 350-out mode, U/D = high level, MODE = high level ) DI/O (Input) 1 2 3 4 5 350 351 CPV OE G1 G2 G3 G4 G350 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin Timing Chart 2 ( 350-out mode, U/D = low level, MODE = high level ) DO/I (Input) 1 2 3 4 5 350 351 CPV OE G350 G349 G348 G347 G1 DI/O (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin 6 2006-09-20 T6LD4 Timing Chart 3 ( 342-out mode, U/D = high level, MODE = low level ) DI/O (Input) 1 2 3 4 5 342 343 CPV OE G1 G2 G3 G4 G171 to G178 VEE G350 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin Timing Chart 4 ( 342-out mode, U/D = low level, MODE = low level ) DO/I (Input) 1 2 3 4 5 342 343 CPV OE G350 G349 G348 G347 G178 to G171 VEE G1 DI/O (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin 7 2006-09-20 T6LD4 Maximum Ratings (VSS = 0 V) Characteristics Symbol Rating Unit Supply voltage (1) VDD −0.3 to 4.0 Supply voltage (2) VGG −0.3 to 45.0 Supply voltage (3) VEE −20.0 to 0.3 Supply voltage (1) VGG − VEE −0.3 to 45.0 Input voltage VIN −0.3 to VDD + 0.3 V Storage temperature Tstg −55 to 125 °C Symbol Rating Unit Supply voltage (3) VDD 2.3 to 3.6 Supply voltage (2) VGG 10 to 35 Supply voltage (4) VEE −15 to −5 Supply voltage (1) VGG − VEE 15.0 to 43.5 Operating temperature Topr −20 to 75 Operating frequency fCPV 100 (max) kHz CL 600 (max) pF/PIN V Operating Range (VSS = 0 V) Characteristics Output load capacitance V °C Electrical Characteristics unless otherwise specified, VGG − VEE = 30.0 to 43.5 V, VDD = 2.3 to 3.6 V, VSS = 0 V, Ta = －20 to 75°C DC Characteristics Symbol Test Circuit Low level VIL ⎯ High level VIH ⎯ Low level VOL ⎯ IOL = 40 µA High level VOH ⎯ IOH = −40 µA Low level ROL High level ROH Characteristics Input voltage Output voltage Output resistance Input current Current dissipation ⎯ IIN ⎯ IGG ⎯ IDD ⎯ IEE ⎯ Test Condition ⎯ VOUT = VEE + 0.5 V VOUT = VGG − 0.5 V ⎯ no load (Note 2) Unit Relevant Pin V (Note 1) V DI/O, DO/I 1000 Ω G1 to G350 −1 1 µA (Note 1) ⎯ 200 Min Max VSS 0.3 × VDD 0.7 × VDD VDD VSS VSS + 0.4 VDD − 0.4 VDD ⎯ ⎯ 50 ⎯ 200 VGG µA VDD VEE Note1: DI/O , DO/I , CPV, OE Note2: fCPV = 50 kHz, Shift data input : 60Hz 1pulse, OE = low level, MODE = high level 8 2006-09-20 T6LD4 AC Characteristics unless otherwise specified, VGG − VEE = 30.0 to 43.5 V, VDD = 2.3 to 3.6 V, VSS = 0 V, Ta = －20 to 75°C Symbol Test Circuit Test Condition Min Max Unit Clock pulse frequency tCPV ⎯ ⎯ ⎯ 100 kHz Clock pulse width (H) tCPVH ⎯ ⎯ 500 ⎯ Clock pulse width (L) tCPVL ⎯ ⎯ 500 ⎯ Data setup time tsDI ⎯ ⎯ 200 ⎯ Data hold time thDI ⎯ ⎯ 200 ⎯ OE pulse width twOE ⎯ ⎯ 1 ⎯ Output delay time (1) tpdDO ⎯ CL = 50 pF ⎯ 200 Output delay time (2) tpdG ⎯ CL = 600 pF ⎯ 1000 Output delay time (3) tpdOE ⎯ CL = 600 pF ⎯ 1000 Characteristics tCPVH CPV 50% ns µs ns tCPVL 50% 50% 50% tsDI DI/O, DO/I (Input) ns 50% thDI 50% 50% tpdG tpdG VGG G1 50% 50% VEE tpdG tpdG VGG G2 to G350 50% 50% VEE CPV 50% 50% VGG G350 VEE tpdDO DO/I, DI/O (Output) tpdDO 50% 50% twOE OE 50% 50% tpdOE tpdOE VGG G1 to G350 50% 50% VEE 9 2006-09-20 T6LD4 Power Supply Sequence Turn power on in the order VDD → VEE → Input signal → VGG. Turn power off in th reverse order. It may input VEE, input signal and VGG simultaneously. T6LD4 have the Power On Reset function. (TrG≥10µs) TrG VGG VDD VSS VEE Instruction for operating circumstances • Light striking a semiconductor device can generate electromotive force due to photoelectric effects. In some cases this may cause the device to malfunction. This is more likely to be affected for the devices in which the surface (back), or side of the chip is exposed. At the design phase, please make sure that devices are protected against incident light from external sources. Please take into account of incident light from external sources during actual operation and during inspection. • Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Please design and manufacture products so that there is no chance of users touching the film after assembly, or if they do that, there is no chance of them injuring themselves. When cutting out the film, please ensure that the film shavings do not cause accidents. After use, please treat the leftover film and reel spacers as industrial waste. 10 2006-09-20 T6LD4 RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. • The products described in this document are subject to foreign exchange and foreign trade control laws. 021023_E 11 2006-09-20